1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CMOV Instruction support required */
48 /* FXSR Instruction support required */
50 /* CLFLUSH Instruction support required */
52 /* NOP Instruction support required */
54 /* SYSCALL Instructions support required */
56 /* Floating point support required */
58 /* i287 support required */
60 /* i387 support required */
62 /* i686 and floating point support required */
64 /* SSE3 and floating point support required */
66 /* MMX support required */
68 /* SSE support required */
70 /* SSE2 support required */
72 /* 3dnow! support required */
74 /* 3dnow! Extensions support required */
76 /* SSE3 support required */
78 /* VIA PadLock required */
80 /* AMD Secure Virtual Machine Ext-s required */
82 /* VMX Instructions required */
84 /* SMX Instructions required */
86 /* SSSE3 support required */
88 /* SSE4a support required */
90 /* LZCNT support required */
92 /* POPCNT support required */
94 /* SSE4.1 support required */
96 /* SSE4.2 support required */
98 /* AVX support required */
100 /* AVX2 support required */
102 /* Intel AVX-512 Foundation Instructions support required */
104 /* Intel AVX-512 Conflict Detection Instructions support required */
106 /* Intel AVX-512 Exponential and Reciprocal Instructions support
109 /* Intel AVX-512 Prefetch Instructions support required */
111 /* Intel AVX-512 VL Instructions support required. */
113 /* Intel AVX-512 DQ Instructions support required. */
115 /* Intel AVX-512 BW Instructions support required. */
117 /* Intel L1OM support required */
119 /* Intel K1OM support required */
121 /* Intel IAMCU support required */
123 /* Xsave/xrstor New Instructions support required */
125 /* Xsaveopt New Instructions support required */
127 /* AES support required */
129 /* PCLMUL support required */
131 /* FMA support required */
133 /* FMA4 support required */
135 /* XOP support required */
137 /* LWP support required */
139 /* BMI support required */
141 /* TBM support required */
143 /* MOVBE Instruction support required */
145 /* CMPXCHG16B instruction support required. */
147 /* EPT Instructions required */
149 /* RDTSCP Instruction support required */
151 /* FSGSBASE Instructions required */
153 /* RDRND Instructions required */
155 /* F16C Instructions required */
157 /* Intel BMI2 support required */
159 /* HLE support required */
161 /* RTM support required */
163 /* INVPCID Instructions required */
165 /* VMFUNC Instruction required */
167 /* Intel MPX Instructions required */
169 /* 64bit support available, used by -march= in assembler. */
171 /* RDRSEED instruction required. */
173 /* Multi-presisionn add-carry instructions are required. */
175 /* Supports prefetchw and prefetch instructions. */
177 /* SMAP instructions required. */
179 /* SHA instructions required. */
181 /* CLFLUSHOPT instruction required */
183 /* XSAVES/XRSTORS instruction required */
185 /* XSAVEC instruction required */
187 /* PREFETCHWT1 instruction required */
189 /* SE1 instruction required */
191 /* CLWB instruction required */
193 /* Intel AVX-512 IFMA Instructions support required. */
195 /* Intel AVX-512 VBMI Instructions support required. */
197 /* Intel AVX-512 4FMAPS Instructions support required. */
199 /* Intel AVX-512 4VNNIW Instructions support required. */
201 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
203 /* Intel AVX-512 VBMI2 Instructions support required. */
205 /* Intel AVX-512 VNNI Instructions support required. */
207 /* Intel AVX-512 BITALG Instructions support required. */
209 /* Intel AVX-512 BF16 Instructions support required. */
211 /* Intel AVX-512 VP2INTERSECT Instructions support required. */
212 CpuAVX512_VP2INTERSECT
,
213 /* mwaitx instruction required */
215 /* Clzero instruction required */
217 /* OSPKE instruction required */
219 /* RDPID instruction required */
221 /* PTWRITE instruction required */
223 /* CET instructions support required */
226 /* AMX-INT8 instructions required */
228 /* AMX-BF16 instructions required */
230 /* AMX-TILE instructions required */
232 /* GFNI instructions required */
234 /* VAES instructions required */
236 /* VPCLMULQDQ instructions required */
238 /* WBNOINVD instructions required */
240 /* PCONFIG instructions required */
242 /* WAITPKG instructions required */
244 /* CLDEMOTE instruction required */
246 /* MOVDIRI instruction support required */
248 /* MOVDIRR64B instruction required */
250 /* ENQCMD instruction required */
252 /* SERIALIZE instruction required */
254 /* RDPRU instruction required */
256 /* MCOMMIT instruction required */
258 /* SEV-ES instruction(s) required */
260 /* TSXLDTRK instruction required */
262 /* 64bit support required */
264 /* Not supported in the 64bit mode */
266 /* The last bitfield in i386_cpu_flags. */
270 #define CpuNumOfUints \
271 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
272 #define CpuNumOfBits \
273 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
275 /* If you get a compiler error for zero width of the unused field,
277 #define CpuUnused (CpuMax + 1)
279 /* We can check if an instruction is available with array instead
281 typedef union i386_cpu_flags
285 unsigned int cpui186
:1;
286 unsigned int cpui286
:1;
287 unsigned int cpui386
:1;
288 unsigned int cpui486
:1;
289 unsigned int cpui586
:1;
290 unsigned int cpui686
:1;
291 unsigned int cpucmov
:1;
292 unsigned int cpufxsr
:1;
293 unsigned int cpuclflush
:1;
294 unsigned int cpunop
:1;
295 unsigned int cpusyscall
:1;
296 unsigned int cpu8087
:1;
297 unsigned int cpu287
:1;
298 unsigned int cpu387
:1;
299 unsigned int cpu687
:1;
300 unsigned int cpufisttp
:1;
301 unsigned int cpummx
:1;
302 unsigned int cpusse
:1;
303 unsigned int cpusse2
:1;
304 unsigned int cpua3dnow
:1;
305 unsigned int cpua3dnowa
:1;
306 unsigned int cpusse3
:1;
307 unsigned int cpupadlock
:1;
308 unsigned int cpusvme
:1;
309 unsigned int cpuvmx
:1;
310 unsigned int cpusmx
:1;
311 unsigned int cpussse3
:1;
312 unsigned int cpusse4a
:1;
313 unsigned int cpulzcnt
:1;
314 unsigned int cpupopcnt
:1;
315 unsigned int cpusse4_1
:1;
316 unsigned int cpusse4_2
:1;
317 unsigned int cpuavx
:1;
318 unsigned int cpuavx2
:1;
319 unsigned int cpuavx512f
:1;
320 unsigned int cpuavx512cd
:1;
321 unsigned int cpuavx512er
:1;
322 unsigned int cpuavx512pf
:1;
323 unsigned int cpuavx512vl
:1;
324 unsigned int cpuavx512dq
:1;
325 unsigned int cpuavx512bw
:1;
326 unsigned int cpul1om
:1;
327 unsigned int cpuk1om
:1;
328 unsigned int cpuiamcu
:1;
329 unsigned int cpuxsave
:1;
330 unsigned int cpuxsaveopt
:1;
331 unsigned int cpuaes
:1;
332 unsigned int cpupclmul
:1;
333 unsigned int cpufma
:1;
334 unsigned int cpufma4
:1;
335 unsigned int cpuxop
:1;
336 unsigned int cpulwp
:1;
337 unsigned int cpubmi
:1;
338 unsigned int cputbm
:1;
339 unsigned int cpumovbe
:1;
340 unsigned int cpucx16
:1;
341 unsigned int cpuept
:1;
342 unsigned int cpurdtscp
:1;
343 unsigned int cpufsgsbase
:1;
344 unsigned int cpurdrnd
:1;
345 unsigned int cpuf16c
:1;
346 unsigned int cpubmi2
:1;
347 unsigned int cpuhle
:1;
348 unsigned int cpurtm
:1;
349 unsigned int cpuinvpcid
:1;
350 unsigned int cpuvmfunc
:1;
351 unsigned int cpumpx
:1;
352 unsigned int cpulm
:1;
353 unsigned int cpurdseed
:1;
354 unsigned int cpuadx
:1;
355 unsigned int cpuprfchw
:1;
356 unsigned int cpusmap
:1;
357 unsigned int cpusha
:1;
358 unsigned int cpuclflushopt
:1;
359 unsigned int cpuxsaves
:1;
360 unsigned int cpuxsavec
:1;
361 unsigned int cpuprefetchwt1
:1;
362 unsigned int cpuse1
:1;
363 unsigned int cpuclwb
:1;
364 unsigned int cpuavx512ifma
:1;
365 unsigned int cpuavx512vbmi
:1;
366 unsigned int cpuavx512_4fmaps
:1;
367 unsigned int cpuavx512_4vnniw
:1;
368 unsigned int cpuavx512_vpopcntdq
:1;
369 unsigned int cpuavx512_vbmi2
:1;
370 unsigned int cpuavx512_vnni
:1;
371 unsigned int cpuavx512_bitalg
:1;
372 unsigned int cpuavx512_bf16
:1;
373 unsigned int cpuavx512_vp2intersect
:1;
374 unsigned int cpumwaitx
:1;
375 unsigned int cpuclzero
:1;
376 unsigned int cpuospke
:1;
377 unsigned int cpurdpid
:1;
378 unsigned int cpuptwrite
:1;
379 unsigned int cpuibt
:1;
380 unsigned int cpushstk
:1;
381 unsigned int cpuamx_int8
:1;
382 unsigned int cpuamx_bf16
:1;
383 unsigned int cpuamx_tile
:1;
384 unsigned int cpugfni
:1;
385 unsigned int cpuvaes
:1;
386 unsigned int cpuvpclmulqdq
:1;
387 unsigned int cpuwbnoinvd
:1;
388 unsigned int cpupconfig
:1;
389 unsigned int cpuwaitpkg
:1;
390 unsigned int cpucldemote
:1;
391 unsigned int cpumovdiri
:1;
392 unsigned int cpumovdir64b
:1;
393 unsigned int cpuenqcmd
:1;
394 unsigned int cpuserialize
:1;
395 unsigned int cpurdpru
:1;
396 unsigned int cpumcommit
:1;
397 unsigned int cpusev_es
:1;
398 unsigned int cputsxldtrk
:1;
399 unsigned int cpu64
:1;
400 unsigned int cpuno64
:1;
402 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
405 unsigned int array
[CpuNumOfUints
];
408 /* Position of opcode_modifier bits. */
412 /* has direction bit. */
414 /* set if operands can be both bytes and words/dwords/qwords, encoded the
415 canonical way; the base_opcode field should hold the encoding for byte
418 /* load form instruction. Must be placed before store form. */
420 /* insn has a modrm byte. */
422 /* special case for jump insns; value has to be 1 */
428 /* special case for intersegment leaps/calls */
429 #define JUMP_INTERSEGMENT 4
430 /* absolute address for jump */
431 #define JUMP_ABSOLUTE 5
433 /* FP insn memory format bit, sized by 0x4 */
435 /* src/dest swap for floats. */
437 /* needs size prefix if in 32-bit mode */
439 /* needs size prefix if in 16-bit mode */
441 /* needs size prefix if in 64-bit mode */
444 /* check register size. */
446 /* instruction ignores operand size prefix and in Intel mode ignores
447 mnemonic size suffix check. */
449 /* default insn size depends on mode */
450 #define DEFAULTSIZE 2
452 /* any memory size */
454 /* b suffix on instruction illegal */
456 /* w suffix on instruction illegal */
458 /* l suffix on instruction illegal */
460 /* s suffix on instruction illegal */
462 /* q suffix on instruction illegal */
464 /* long double suffix on instruction illegal */
466 /* instruction needs FWAIT */
468 /* IsString provides for a quick test for string instructions, and
469 its actual value also indicates which of the operands (if any)
470 requires use of the %es segment. */
471 #define IS_STRING_ES_OP0 2
472 #define IS_STRING_ES_OP1 3
474 /* RegMem is for instructions with a modrm byte where the register
475 destination operand should be encoded in the mod and regmem fields.
476 Normally, it will be encoded in the reg field. We add a RegMem
477 flag to indicate that it should be encoded in the regmem field. */
479 /* quick test if branch instruction is MPX supported */
481 /* quick test if NOTRACK prefix is supported */
483 /* quick test for lockable instructions */
485 /* fake an extra reg operand for clr, imul and special register
486 processing for some instructions. */
488 /* An implicit xmm0 as the first operand */
490 /* The HLE prefix is OK:
491 1. With a LOCK prefix.
492 2. With or without a LOCK prefix.
493 3. With a RELEASE (0xf3) prefix.
495 #define HLEPrefixNone 0
496 #define HLEPrefixLock 1
497 #define HLEPrefixAny 2
498 #define HLEPrefixRelease 3
500 /* An instruction on which a "rep" prefix is acceptable. */
502 /* Convert to DWORD */
504 /* Convert to QWORD */
506 /* Address prefix changes register operand */
508 /* opcode is a prefix */
510 /* instruction has extension in 8 bit imm */
512 /* instruction don't need Rex64 prefix. */
514 /* deprecated fp insn, gets a warning */
516 /* insn has VEX prefix:
517 1: 128bit VEX prefix (or operand dependent).
518 2: 256bit VEX prefix.
519 3: Scalar VEX prefix.
525 /* How to encode VEX.vvvv:
526 0: VEX.vvvv must be 1111b.
527 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
528 the content of source registers will be preserved.
529 VEX.DDS. The second register operand is encoded in VEX.vvvv
530 where the content of first source register will be overwritten
532 VEX.NDD2. The second destination register operand is encoded in
533 VEX.vvvv for instructions with 2 destination register operands.
534 For assembler, there are no difference between VEX.NDS, VEX.DDS
536 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
537 instructions with 1 destination register operand.
538 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
539 of the operands can access a memory location.
545 /* How the VEX.W bit is used:
546 0: Set by the REX.W bit.
547 1: VEX.W0. Should always be 0.
548 2: VEX.W1. Should always be 1.
549 3: VEX.WIG. The VEX.W bit is ignored.
555 /* VEX opcode prefix:
556 0: VEX 0x0F opcode prefix.
557 1: VEX 0x0F38 opcode prefix.
558 2: VEX 0x0F3A opcode prefix
559 3: XOP 0x08 opcode prefix.
560 4: XOP 0x09 opcode prefix
561 5: XOP 0x0A opcode prefix.
570 /* number of VEX source operands:
571 0: <= 2 source operands.
572 1: 2 XOP source operands.
573 2: 3 source operands.
575 #define XOP2SOURCES 1
576 #define VEX3SOURCES 2
578 /* Instruction with a mandatory SIB byte:
579 1: 128bit vector register.
580 2: 256bit vector register.
581 3: 512bit vector register.
589 /* SSE to AVX support required */
591 /* No AVX equivalent */
594 /* insn has EVEX prefix:
595 1: 512bit EVEX prefix.
596 2: 128bit EVEX prefix.
597 3: 256bit EVEX prefix.
598 4: Length-ignored (LIG) EVEX prefix.
599 5: Length determined from actual operands.
608 /* AVX512 masking support:
609 1: Zeroing or merging masking depending on operands.
611 3: Both zeroing and merging masking.
613 #define DYNAMIC_MASKING 1
614 #define MERGING_MASKING 2
615 #define BOTH_MASKING 3
618 /* AVX512 broadcast support. The number of bytes to broadcast is
619 1 << (Broadcast - 1):
625 #define BYTE_BROADCAST 1
626 #define WORD_BROADCAST 2
627 #define DWORD_BROADCAST 3
628 #define QWORD_BROADCAST 4
631 /* Static rounding control is supported. */
634 /* Supress All Exceptions is supported. */
637 /* Compressed Disp8*N attribute. */
638 #define DISP8_SHIFT_VL 7
641 /* Default mask isn't allowed. */
644 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
645 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
649 /* Two source operands are swapped. */
652 /* Support encoding optimization. */
661 /* ISA64: Don't change the order without other code adjustments.
662 0: Common to AMD64 and Intel64.
669 #define INTEL64ONLY 3
671 /* The last bitfield in i386_opcode_modifier. */
675 typedef struct i386_opcode_modifier
680 unsigned int modrm
:1;
682 unsigned int floatmf
:1;
683 unsigned int floatr
:1;
685 unsigned int checkregsize
:1;
686 unsigned int mnemonicsize
:2;
687 unsigned int anysize
:1;
688 unsigned int no_bsuf
:1;
689 unsigned int no_wsuf
:1;
690 unsigned int no_lsuf
:1;
691 unsigned int no_ssuf
:1;
692 unsigned int no_qsuf
:1;
693 unsigned int no_ldsuf
:1;
694 unsigned int fwait
:1;
695 unsigned int isstring
:2;
696 unsigned int regmem
:1;
697 unsigned int bndprefixok
:1;
698 unsigned int notrackprefixok
:1;
699 unsigned int islockable
:1;
700 unsigned int regkludge
:1;
701 unsigned int implicit1stxmm0
:1;
702 unsigned int hleprefixok
:2;
703 unsigned int repprefixok
:1;
704 unsigned int todword
:1;
705 unsigned int toqword
:1;
706 unsigned int addrprefixopreg
:1;
707 unsigned int isprefix
:1;
708 unsigned int immext
:1;
709 unsigned int norex64
:1;
712 unsigned int vexvvvv
:2;
714 unsigned int vexopcode
:3;
715 unsigned int vexsources
:2;
717 unsigned int sse2avx
:1;
718 unsigned int noavx
:1;
720 unsigned int masking
:2;
721 unsigned int broadcast
:3;
722 unsigned int staticrounding
:1;
724 unsigned int disp8memshift
:3;
725 unsigned int nodefmask
:1;
726 unsigned int implicitquadgroup
:1;
727 unsigned int swapsources
:1;
728 unsigned int optimize
:1;
729 unsigned int attmnemonic
:1;
730 unsigned int attsyntax
:1;
731 unsigned int intelsyntax
:1;
732 unsigned int isa64
:2;
733 } i386_opcode_modifier
;
735 /* Operand classes. */
737 #define CLASS_WIDTH 4
741 Reg
, /* GPRs and FP regs, distinguished by operand size */
742 SReg
, /* Segment register */
743 RegCR
, /* Control register */
744 RegDR
, /* Debug register */
745 RegTR
, /* Test register */
746 RegMMX
, /* MMX register */
747 RegSIMD
, /* XMM/YMM/ZMM registers, distinguished by operand size */
748 RegMask
, /* Vector Mask register */
749 RegBND
, /* Bound register */
752 /* Special operand instances. */
754 #define INSTANCE_WIDTH 3
755 enum operand_instance
758 Accum
, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
759 RegC
, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
760 RegD
, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
761 RegB
, /* %bl / %bx / %ebx / %rbx */
764 /* Position of operand_type bits. */
768 /* Class and Instance */
769 ClassInstance
= CLASS_WIDTH
+ INSTANCE_WIDTH
- 1,
770 /* 1 bit immediate */
772 /* 8 bit immediate */
774 /* 8 bit immediate sign extended */
776 /* 16 bit immediate */
778 /* 32 bit immediate */
780 /* 32 bit immediate sign extended */
782 /* 64 bit immediate */
784 /* 8bit/16bit/32bit displacements are used in different ways,
785 depending on the instruction. For jumps, they specify the
786 size of the PC relative displacement, for instructions with
787 memory operand, they specify the size of the offset relative
788 to the base register, and for instructions with memory offset
789 such as `mov 1234,%al' they specify the size of the offset
790 relative to the segment base. */
791 /* 8 bit displacement */
793 /* 16 bit displacement */
795 /* 32 bit displacement */
797 /* 32 bit signed displacement */
799 /* 64 bit displacement */
801 /* Register which can be used for base or index in memory operand. */
805 /* WORD size. 2 byte */
807 /* DWORD size. 4 byte */
809 /* FWORD size. 6 byte */
811 /* QWORD size. 8 byte */
813 /* TBYTE size. 10 byte */
823 /* Unspecified memory size. */
826 /* The number of bits in i386_operand_type. */
830 #define OTNumOfUints \
831 ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
832 #define OTNumOfBits \
833 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
835 /* If you get a compiler error for zero width of the unused field,
837 #define OTUnused OTNum
839 typedef union i386_operand_type
843 unsigned int class:CLASS_WIDTH
;
844 unsigned int instance
:INSTANCE_WIDTH
;
847 unsigned int imm8s
:1;
848 unsigned int imm16
:1;
849 unsigned int imm32
:1;
850 unsigned int imm32s
:1;
851 unsigned int imm64
:1;
852 unsigned int disp8
:1;
853 unsigned int disp16
:1;
854 unsigned int disp32
:1;
855 unsigned int disp32s
:1;
856 unsigned int disp64
:1;
857 unsigned int baseindex
:1;
860 unsigned int dword
:1;
861 unsigned int fword
:1;
862 unsigned int qword
:1;
863 unsigned int tbyte
:1;
864 unsigned int xmmword
:1;
865 unsigned int ymmword
:1;
866 unsigned int zmmword
:1;
867 unsigned int tmmword
:1;
868 unsigned int unspecified
:1;
870 unsigned int unused
:(OTNumOfBits
- OTUnused
);
873 unsigned int array
[OTNumOfUints
];
876 typedef struct insn_template
878 /* instruction name sans width suffix ("mov" for movl insns) */
881 /* base_opcode is the fundamental opcode byte without optional
883 unsigned int base_opcode
;
884 #define Opcode_D 0x2 /* Direction bit:
885 set if Reg --> Regmem;
886 unset if Regmem --> Reg. */
887 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
888 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
889 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
890 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
892 /* extension_opcode is the 3 bit extension for group <n> insns.
893 This field is also used to store the 8-bit opcode suffix for the
894 AMD 3DNow! instructions.
895 If this template has no extension opcode (the usual case) use None
897 unsigned short extension_opcode
;
898 #define None 0xffff /* If no extension_opcode is possible. */
901 unsigned char opcode_length
;
903 /* how many operands */
904 unsigned char operands
;
906 /* cpu feature flags */
907 i386_cpu_flags cpu_flags
;
909 /* the bits in opcode_modifier are used to generate the final opcode from
910 the base_opcode. These bits also are used to detect alternate forms of
911 the same instruction */
912 i386_opcode_modifier opcode_modifier
;
914 /* operand_types[i] describes the type of operand i. This is made
915 by OR'ing together all of the possible type masks. (e.g.
916 'operand_types[i] = Reg|Imm' specifies that operand i can be
917 either a register or an immediate operand. */
918 i386_operand_type operand_types
[MAX_OPERANDS
];
922 extern const insn_template i386_optab
[];
924 /* these are for register name --> number & type hash lookup */
927 const char *reg_name
;
928 i386_operand_type reg_type
;
929 unsigned char reg_flags
;
930 #define RegRex 0x1 /* Extended register. */
931 #define RegRex64 0x2 /* Extended 8 bit register. */
932 #define RegVRex 0x4 /* Extended vector register. */
933 unsigned char reg_num
;
934 #define RegIP ((unsigned char ) ~0)
935 /* EIZ and RIZ are fake index registers. */
936 #define RegIZ (RegIP - 1)
937 /* FLAT is a fake segment register (Intel mode). */
938 #define RegFlat ((unsigned char) ~0)
939 signed char dw2_regnum
[2];
940 #define Dw2Inval (-1)
944 /* Entries in i386_regtab. */
947 #define REGNAM_EAX 41
949 extern const reg_entry i386_regtab
[];
950 extern const unsigned int i386_regtab_size
;
955 unsigned int seg_prefix
;
959 extern const seg_entry cs
;
960 extern const seg_entry ds
;
961 extern const seg_entry ss
;
962 extern const seg_entry es
;
963 extern const seg_entry fs
;
964 extern const seg_entry gs
;