opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2022 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #include <limits.h>
  23 #ifndef CHAR_BIT
  24 #define CHAR_BIT 8
  25 #endif
  26
  27 /* Position of cpu flags bitfiled.  */
  28
  29 enum
  30 {
  31   /* i186 or better required */
  32   Cpu186 = 0,
  33   /* i286 or better required */
  34   Cpu286,
  35   /* i386 or better required */
  36   Cpu386,
  37   /* i486 or better required */
  38   Cpu486,
  39   /* i585 or better required */
  40   Cpu586,
  41   /* i686 or better required */
  42   Cpu686,
  43   /* CMOV Instruction support required */
  44   CpuCMOV,
  45   /* FXSR Instruction support required */
  46   CpuFXSR,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* LZCNT support required */
  88   CpuLZCNT,
  89   /* POPCNT support required */
  90   CpuPOPCNT,
  91   /* SSE4.1 support required */
  92   CpuSSE4_1,
  93   /* SSE4.2 support required */
  94   CpuSSE4_2,
  95   /* AVX support required */
  96   CpuAVX,
  97   /* AVX2 support required */
  98   CpuAVX2,
  99   /* Intel AVX-512 Foundation Instructions support required */
 100   CpuAVX512F,
 101   /* Intel AVX-512 Conflict Detection Instructions support required */
 102   CpuAVX512CD,
 103   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 104      required */
 105   CpuAVX512ER,
 106   /* Intel AVX-512 Prefetch Instructions support required */
 107   CpuAVX512PF,
 108   /* Intel AVX-512 VL Instructions support required.  */
 109   CpuAVX512VL,
 110   /* Intel AVX-512 DQ Instructions support required.  */
 111   CpuAVX512DQ,
 112   /* Intel AVX-512 BW Instructions support required.  */
 113   CpuAVX512BW,
 114   /* Intel IAMCU support required */
 115   CpuIAMCU,
 116   /* Xsave/xrstor New Instructions support required */
 117   CpuXsave,
 118   /* Xsaveopt New Instructions support required */
 119   CpuXsaveopt,
 120   /* AES support required */
 121   CpuAES,
 122   /* PCLMUL support required */
 123   CpuPCLMUL,
 124   /* FMA support required */
 125   CpuFMA,
 126   /* FMA4 support required */
 127   CpuFMA4,
 128   /* XOP support required */
 129   CpuXOP,
 130   /* LWP support required */
 131   CpuLWP,
 132   /* BMI support required */
 133   CpuBMI,
 134   /* TBM support required */
 135   CpuTBM,
 136   /* MOVBE Instruction support required */
 137   CpuMovbe,
 138   /* CMPXCHG16B instruction support required.  */
 139   CpuCX16,
 140   /* EPT Instructions required */
 141   CpuEPT,
 142   /* RDTSCP Instruction support required */
 143   CpuRdtscp,
 144   /* FSGSBASE Instructions required */
 145   CpuFSGSBase,
 146   /* RDRND Instructions required */
 147   CpuRdRnd,
 148   /* F16C Instructions required */
 149   CpuF16C,
 150   /* Intel BMI2 support required */
 151   CpuBMI2,
 152   /* HLE support required */
 153   CpuHLE,
 154   /* RTM support required */
 155   CpuRTM,
 156   /* INVPCID Instructions required */
 157   CpuINVPCID,
 158   /* VMFUNC Instruction required */
 159   CpuVMFUNC,
 160   /* Intel MPX Instructions required  */
 161   CpuMPX,
 162   /* 64bit support available, used by -march= in assembler.  */
 163   CpuLM,
 164   /* RDRSEED instruction required.  */
 165   CpuRDSEED,
 166   /* Multi-presisionn add-carry instructions are required.  */
 167   CpuADX,
 168   /* Supports prefetchw and prefetch instructions.  */
 169   CpuPRFCHW,
 170   /* SMAP instructions required.  */
 171   CpuSMAP,
 172   /* SHA instructions required.  */
 173   CpuSHA,
 174   /* CLFLUSHOPT instruction required */
 175   CpuClflushOpt,
 176   /* XSAVES/XRSTORS instruction required */
 177   CpuXSAVES,
 178   /* XSAVEC instruction required */
 179   CpuXSAVEC,
 180   /* PREFETCHWT1 instruction required */
 181   CpuPREFETCHWT1,
 182   /* SE1 instruction required */
 183   CpuSE1,
 184   /* CLWB instruction required */
 185   CpuCLWB,
 186   /* Intel AVX-512 IFMA Instructions support required.  */
 187   CpuAVX512IFMA,
 188   /* Intel AVX-512 VBMI Instructions support required.  */
 189   CpuAVX512VBMI,
 190   /* Intel AVX-512 4FMAPS Instructions support required.  */
 191   CpuAVX512_4FMAPS,
 192   /* Intel AVX-512 4VNNIW Instructions support required.  */
 193   CpuAVX512_4VNNIW,
 194   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 195   CpuAVX512_VPOPCNTDQ,
 196   /* Intel AVX-512 VBMI2 Instructions support required.  */
 197   CpuAVX512_VBMI2,
 198   /* Intel AVX-512 VNNI Instructions support required.  */
 199   CpuAVX512_VNNI,
 200   /* Intel AVX-512 BITALG Instructions support required.  */
 201   CpuAVX512_BITALG,
 202   /* Intel AVX-512 BF16 Instructions support required.  */
 203   CpuAVX512_BF16,
 204   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 205   CpuAVX512_VP2INTERSECT,
 206   /* TDX Instructions support required.  */
 207   CpuTDX,
 208   /* Intel AVX VNNI Instructions support required.  */
 209   CpuAVX_VNNI,
 210   /* Intel AVX-512 FP16 Instructions support required.  */
 211   CpuAVX512_FP16,
 212   /* mwaitx instruction required */
 213   CpuMWAITX,
 214   /* Clzero instruction required */
 215   CpuCLZERO,
 216   /* OSPKE instruction required */
 217   CpuOSPKE,
 218   /* RDPID instruction required */
 219   CpuRDPID,
 220   /* PTWRITE instruction required */
 221   CpuPTWRITE,
 222   /* CET instructions support required */
 223   CpuIBT,
 224   CpuSHSTK,
 225   /* AMX-INT8 instructions required */
 226   CpuAMX_INT8,
 227   /* AMX-BF16 instructions required */
 228   CpuAMX_BF16,
 229   /* AMX-TILE instructions required */
 230   CpuAMX_TILE,
 231   /* GFNI instructions required */
 232   CpuGFNI,
 233   /* VAES instructions required */
 234   CpuVAES,
 235   /* VPCLMULQDQ instructions required */
 236   CpuVPCLMULQDQ,
 237   /* WBNOINVD instructions required */
 238   CpuWBNOINVD,
 239   /* PCONFIG instructions required */
 240   CpuPCONFIG,
 241   /* WAITPKG instructions required */
 242   CpuWAITPKG,
 243   /* UINTR instructions required */
 244   CpuUINTR,
 245   /* CLDEMOTE instruction required */
 246   CpuCLDEMOTE,
 247   /* MOVDIRI instruction support required */
 248   CpuMOVDIRI,
 249   /* MOVDIRR64B instruction required */
 250   CpuMOVDIR64B,
 251   /* ENQCMD instruction required */
 252   CpuENQCMD,
 253   /* SERIALIZE instruction required */
 254   CpuSERIALIZE,
 255   /* RDPRU instruction required */
 256   CpuRDPRU,
 257   /* MCOMMIT instruction required */
 258   CpuMCOMMIT,
 259   /* SEV-ES instruction(s) required */
 260   CpuSEV_ES,
 261   /* TSXLDTRK instruction required */
 262   CpuTSXLDTRK,
 263   /* KL instruction support required */
 264   CpuKL,
 265   /* WideKL instruction support required */
 266   CpuWideKL,
 267   /* HRESET instruction required */
 268   CpuHRESET,
 269   /* INVLPGB instructions required */
 270   CpuINVLPGB,
 271   /* TLBSYNC instructions required */
 272   CpuTLBSYNC,
 273   /* SNP instructions required */
 274   CpuSNP,
 275
 276   /* NOTE: These last three items need to remain last and in this order. */
 277
 278   /* 64bit support required  */
 279   Cpu64,
 280   /* Not supported in the 64bit mode  */
 281   CpuNo64,
 282   /* The last bitfield in i386_cpu_flags.  */
 283   CpuMax = CpuNo64
 284 };
 285
 286 #define CpuNumOfUints \
 287   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 288 #define CpuNumOfBits \
 289   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 290
 291 /* If you get a compiler error for zero width of the unused field,
 292    comment it out.  */
 293 #define CpuUnused       (CpuMax + 1)
 294
 295 /* We can check if an instruction is available with array instead
 296    of bitfield. */
 297 typedef union i386_cpu_flags
 298 {
 299   struct
 300     {
 301       unsigned int cpui186:1;
 302       unsigned int cpui286:1;
 303       unsigned int cpui386:1;
 304       unsigned int cpui486:1;
 305       unsigned int cpui586:1;
 306       unsigned int cpui686:1;
 307       unsigned int cpucmov:1;
 308       unsigned int cpufxsr:1;
 309       unsigned int cpuclflush:1;
 310       unsigned int cpunop:1;
 311       unsigned int cpusyscall:1;
 312       unsigned int cpu8087:1;
 313       unsigned int cpu287:1;
 314       unsigned int cpu387:1;
 315       unsigned int cpu687:1;
 316       unsigned int cpufisttp:1;
 317       unsigned int cpummx:1;
 318       unsigned int cpusse:1;
 319       unsigned int cpusse2:1;
 320       unsigned int cpua3dnow:1;
 321       unsigned int cpua3dnowa:1;
 322       unsigned int cpusse3:1;
 323       unsigned int cpupadlock:1;
 324       unsigned int cpusvme:1;
 325       unsigned int cpuvmx:1;
 326       unsigned int cpusmx:1;
 327       unsigned int cpussse3:1;
 328       unsigned int cpusse4a:1;
 329       unsigned int cpulzcnt:1;
 330       unsigned int cpupopcnt:1;
 331       unsigned int cpusse4_1:1;
 332       unsigned int cpusse4_2:1;
 333       unsigned int cpuavx:1;
 334       unsigned int cpuavx2:1;
 335       unsigned int cpuavx512f:1;
 336       unsigned int cpuavx512cd:1;
 337       unsigned int cpuavx512er:1;
 338       unsigned int cpuavx512pf:1;
 339       unsigned int cpuavx512vl:1;
 340       unsigned int cpuavx512dq:1;
 341       unsigned int cpuavx512bw:1;
 342       unsigned int cpuiamcu:1;
 343       unsigned int cpuxsave:1;
 344       unsigned int cpuxsaveopt:1;
 345       unsigned int cpuaes:1;
 346       unsigned int cpupclmul:1;
 347       unsigned int cpufma:1;
 348       unsigned int cpufma4:1;
 349       unsigned int cpuxop:1;
 350       unsigned int cpulwp:1;
 351       unsigned int cpubmi:1;
 352       unsigned int cputbm:1;
 353       unsigned int cpumovbe:1;
 354       unsigned int cpucx16:1;
 355       unsigned int cpuept:1;
 356       unsigned int cpurdtscp:1;
 357       unsigned int cpufsgsbase:1;
 358       unsigned int cpurdrnd:1;
 359       unsigned int cpuf16c:1;
 360       unsigned int cpubmi2:1;
 361       unsigned int cpuhle:1;
 362       unsigned int cpurtm:1;
 363       unsigned int cpuinvpcid:1;
 364       unsigned int cpuvmfunc:1;
 365       unsigned int cpumpx:1;
 366       unsigned int cpulm:1;
 367       unsigned int cpurdseed:1;
 368       unsigned int cpuadx:1;
 369       unsigned int cpuprfchw:1;
 370       unsigned int cpusmap:1;
 371       unsigned int cpusha:1;
 372       unsigned int cpuclflushopt:1;
 373       unsigned int cpuxsaves:1;
 374       unsigned int cpuxsavec:1;
 375       unsigned int cpuprefetchwt1:1;
 376       unsigned int cpuse1:1;
 377       unsigned int cpuclwb:1;
 378       unsigned int cpuavx512ifma:1;
 379       unsigned int cpuavx512vbmi:1;
 380       unsigned int cpuavx512_4fmaps:1;
 381       unsigned int cpuavx512_4vnniw:1;
 382       unsigned int cpuavx512_vpopcntdq:1;
 383       unsigned int cpuavx512_vbmi2:1;
 384       unsigned int cpuavx512_vnni:1;
 385       unsigned int cpuavx512_bitalg:1;
 386       unsigned int cpuavx512_bf16:1;
 387       unsigned int cpuavx512_vp2intersect:1;
 388       unsigned int cputdx:1;
 389       unsigned int cpuavx_vnni:1;
 390       unsigned int cpuavx512_fp16:1;
 391       unsigned int cpumwaitx:1;
 392       unsigned int cpuclzero:1;
 393       unsigned int cpuospke:1;
 394       unsigned int cpurdpid:1;
 395       unsigned int cpuptwrite:1;
 396       unsigned int cpuibt:1;
 397       unsigned int cpushstk:1;
 398       unsigned int cpuamx_int8:1;
 399       unsigned int cpuamx_bf16:1;
 400       unsigned int cpuamx_tile:1;
 401       unsigned int cpugfni:1;
 402       unsigned int cpuvaes:1;
 403       unsigned int cpuvpclmulqdq:1;
 404       unsigned int cpuwbnoinvd:1;
 405       unsigned int cpupconfig:1;
 406       unsigned int cpuwaitpkg:1;
 407       unsigned int cpuuintr:1;
 408       unsigned int cpucldemote:1;
 409       unsigned int cpumovdiri:1;
 410       unsigned int cpumovdir64b:1;
 411       unsigned int cpuenqcmd:1;
 412       unsigned int cpuserialize:1;
 413       unsigned int cpurdpru:1;
 414       unsigned int cpumcommit:1;
 415       unsigned int cpusev_es:1;
 416       unsigned int cputsxldtrk:1;
 417       unsigned int cpukl:1;
 418       unsigned int cpuwidekl:1;
 419       unsigned int cpuhreset:1;
 420       unsigned int cpuinvlpgb:1;
 421       unsigned int cputlbsync:1;
 422       unsigned int cpusnp:1;
 423       /* NOTE: These last three fields need to remain last and in this order. */
 424       unsigned int cpu64:1;
 425       unsigned int cpuno64:1;
 426 #ifdef CpuUnused
 427       unsigned int unused:(CpuNumOfBits - CpuUnused);
 428 #endif
 429     } bitfield;
 430   unsigned int array[CpuNumOfUints];
 431 } i386_cpu_flags;
 432
 433 /* Position of opcode_modifier bits.  */
 434
 435 enum
 436 {
 437   /* has direction bit. */
 438   D = 0,
 439   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 440      canonical way; the base_opcode field should hold the encoding for byte
 441      operands  */
 442   W,
 443   /* load form instruction. Must be placed before store form.  */
 444   Load,
 445   /* insn has a modrm byte. */
 446   Modrm,
 447   /* special case for jump insns; value has to be 1 */
 448 #define JUMP 1
 449   /* call and jump */
 450 #define JUMP_DWORD 2
 451   /* loop and jecxz */
 452 #define JUMP_BYTE 3
 453   /* special case for intersegment leaps/calls */
 454 #define JUMP_INTERSEGMENT 4
 455   /* absolute address for jump */
 456 #define JUMP_ABSOLUTE 5
 457   Jump,
 458   /* FP insn memory format bit, sized by 0x4 */
 459   FloatMF,
 460   /* src/dest swap for floats. */
 461   FloatR,
 462   /* needs size prefix if in 32-bit mode */
 463 #define SIZE16 1
 464   /* needs size prefix if in 16-bit mode */
 465 #define SIZE32 2
 466   /* needs size prefix if in 64-bit mode */
 467 #define SIZE64 3
 468   Size,
 469   /* check register size.  */
 470   CheckRegSize,
 471   /* Instrucion requires that destination must be distinct from source
 472      registers.  */
 473   DistinctDest,
 474   /* instruction ignores operand size prefix and in Intel mode ignores
 475      mnemonic size suffix check.  */
 476 #define IGNORESIZE      1
 477   /* default insn size depends on mode */
 478 #define DEFAULTSIZE     2
 479   MnemonicSize,
 480   /* any memory size */
 481   Anysize,
 482   /* b suffix on instruction illegal */
 483   No_bSuf,
 484   /* w suffix on instruction illegal */
 485   No_wSuf,
 486   /* l suffix on instruction illegal */
 487   No_lSuf,
 488   /* s suffix on instruction illegal */
 489   No_sSuf,
 490   /* q suffix on instruction illegal */
 491   No_qSuf,
 492   /* long double suffix on instruction illegal */
 493   No_ldSuf,
 494   /* instruction needs FWAIT */
 495   FWait,
 496   /* IsString provides for a quick test for string instructions, and
 497      its actual value also indicates which of the operands (if any)
 498      requires use of the %es segment.  */
 499 #define IS_STRING_ES_OP0 2
 500 #define IS_STRING_ES_OP1 3
 501   IsString,
 502   /* RegMem is for instructions with a modrm byte where the register
 503      destination operand should be encoded in the mod and regmem fields.
 504      Normally, it will be encoded in the reg field. We add a RegMem
 505      flag to indicate that it should be encoded in the regmem field.  */
 506   RegMem,
 507   /* quick test if branch instruction is MPX supported */
 508   BNDPrefixOk,
 509   /* fake an extra reg operand for clr, imul and special register
 510      processing for some instructions.  */
 511   RegKludge,
 512   /* An implicit xmm0 as the first operand */
 513   Implicit1stXmm0,
 514 #define PrefixNone              0
 515 #define PrefixRep               1
 516 #define PrefixHLERelease        2 /* Okay with an XRELEASE (0xf3) prefix. */
 517 #define PrefixNoTrack           3
 518   /* Prefixes implying "LOCK okay" must come after Lock. All others have
 519      to come before.  */
 520 #define PrefixLock              4
 521 #define PrefixHLELock           5 /* Okay with a LOCK prefix.  */
 522 #define PrefixHLEAny            6 /* Okay with or without a LOCK prefix.  */
 523   PrefixOk,
 524   /* Address prefix changes register operand */
 525   AddrPrefixOpReg,
 526   /* opcode is a prefix */
 527   IsPrefix,
 528   /* instruction has extension in 8 bit imm */
 529   ImmExt,
 530   /* instruction don't need Rex64 prefix.  */
 531   NoRex64,
 532   /* deprecated fp insn, gets a warning */
 533   Ugh,
 534   /* Intel AVX Instructions support via {vex} prefix */
 535   PseudoVexPrefix,
 536   /* insn has VEX prefix:
 537         1: 128bit VEX prefix (or operand dependent).
 538         2: 256bit VEX prefix.
 539         3: Scalar VEX prefix.
 540    */
 541 #define VEX128          1
 542 #define VEX256          2
 543 #define VEXScalar       3
 544   Vex,
 545   /* How to encode VEX.vvvv:
 546      0: VEX.vvvv must be 1111b.
 547      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 548         the content of source registers will be preserved.
 549         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 550         where the content of first source register will be overwritten
 551         by the result.
 552         VEX.NDD2.  The second destination register operand is encoded in
 553         VEX.vvvv for instructions with 2 destination register operands.
 554         For assembler, there are no difference between VEX.NDS, VEX.DDS
 555         and VEX.NDD2.
 556      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 557      instructions with 1 destination register operand.
 558      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 559         of the operands can access a memory location.
 560    */
 561 #define VEXXDS  1
 562 #define VEXNDD  2
 563 #define VEXLWP  3
 564   VexVVVV,
 565   /* How the VEX.W bit is used:
 566      0: Set by the REX.W bit.
 567      1: VEX.W0.  Should always be 0.
 568      2: VEX.W1.  Should always be 1.
 569      3: VEX.WIG. The VEX.W bit is ignored.
 570    */
 571 #define VEXW0   1
 572 #define VEXW1   2
 573 #define VEXWIG  3
 574   VexW,
 575   /* Opcode encoding space (values chosen to be usable directly in
 576      VEX/XOP mmmmm and EVEX mm fields):
 577      0: Base opcode space.
 578      1: 0F opcode prefix / space.
 579      2: 0F38 opcode prefix / space.
 580      3: 0F3A opcode prefix / space.
 581      5: EVEXMAP5 opcode prefix / space.
 582      6: EVEXMAP6 opcode prefix / space.
 583      8: XOP 08 opcode space.
 584      9: XOP 09 opcode space.
 585      A: XOP 0A opcode space.
 586    */
 587 #define SPACE_BASE      0
 588 #define SPACE_0F        1
 589 #define SPACE_0F38      2
 590 #define SPACE_0F3A      3
 591 #define SPACE_EVEXMAP5  5
 592 #define SPACE_EVEXMAP6  6
 593 #define SPACE_XOP08     8
 594 #define SPACE_XOP09     9
 595 #define SPACE_XOP0A     0xA
 596   OpcodeSpace,
 597   /* Opcode prefix (values chosen to be usable directly in
 598      VEX/XOP/EVEX pp fields):
 599      0: None
 600      1: Add 0x66 opcode prefix.
 601      2: Add 0xf3 opcode prefix.
 602      3: Add 0xf2 opcode prefix.
 603    */
 604 #define PREFIX_NONE     0
 605 #define PREFIX_0X66     1
 606 #define PREFIX_0XF3     2
 607 #define PREFIX_0XF2     3
 608   OpcodePrefix,
 609   /* number of VEX source operands:
 610      0: <= 2 source operands.
 611      1: 2 XOP source operands.
 612      2: 3 source operands.
 613    */
 614 #define XOP2SOURCES     1
 615 #define VEX3SOURCES     2
 616   VexSources,
 617   /* Instruction with a mandatory SIB byte:
 618         1: 128bit vector register.
 619         2: 256bit vector register.
 620         3: 512bit vector register.
 621    */
 622 #define VECSIB128       1
 623 #define VECSIB256       2
 624 #define VECSIB512       3
 625 #define SIBMEM          4
 626   SIB,
 627
 628   /* SSE to AVX support required */
 629   SSE2AVX,
 630
 631   /* insn has EVEX prefix:
 632         1: 512bit EVEX prefix.
 633         2: 128bit EVEX prefix.
 634         3: 256bit EVEX prefix.
 635         4: Length-ignored (LIG) EVEX prefix.
 636         5: Length determined from actual operands.
 637    */
 638 #define EVEX512                1
 639 #define EVEX128                2
 640 #define EVEX256                3
 641 #define EVEXLIG                4
 642 #define EVEXDYN                5
 643   EVex,
 644
 645   /* AVX512 masking support:
 646         1: Zeroing or merging masking depending on operands.
 647         2: Merging-masking.
 648         3: Both zeroing and merging masking.
 649    */
 650 #define DYNAMIC_MASKING 1
 651 #define MERGING_MASKING 2
 652 #define BOTH_MASKING    3
 653   Masking,
 654
 655   /* AVX512 broadcast support.  The number of bytes to broadcast is
 656      1 << (Broadcast - 1):
 657         1: Byte broadcast.
 658         2: Word broadcast.
 659         3: Dword broadcast.
 660         4: Qword broadcast.
 661    */
 662 #define BYTE_BROADCAST  1
 663 #define WORD_BROADCAST  2
 664 #define DWORD_BROADCAST 3
 665 #define QWORD_BROADCAST 4
 666   Broadcast,
 667
 668   /* Static rounding control is supported.  */
 669   StaticRounding,
 670
 671   /* Supress All Exceptions is supported.  */
 672   SAE,
 673
 674   /* Compressed Disp8*N attribute.  */
 675 #define DISP8_SHIFT_VL 7
 676   Disp8MemShift,
 677
 678   /* Default mask isn't allowed.  */
 679   NoDefMask,
 680
 681   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 682      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 683    */
 684   ImplicitQuadGroup,
 685
 686   /* Two source operands are swapped.  */
 687   SwapSources,
 688
 689   /* Support encoding optimization.  */
 690   Optimize,
 691
 692   /* AT&T mnemonic.  */
 693   ATTMnemonic,
 694   /* AT&T syntax.  */
 695   ATTSyntax,
 696   /* Intel syntax.  */
 697   IntelSyntax,
 698   /* ISA64: Don't change the order without other code adjustments.
 699         0: Common to AMD64 and Intel64.
 700         1: AMD64.
 701         2: Intel64.
 702         3: Only in Intel64.
 703    */
 704 #define AMD64           1
 705 #define INTEL64         2
 706 #define INTEL64ONLY     3
 707   ISA64,
 708   /* The last bitfield in i386_opcode_modifier.  */
 709   Opcode_Modifier_Num
 710 };
 711
 712 typedef struct i386_opcode_modifier
 713 {
 714   unsigned int d:1;
 715   unsigned int w:1;
 716   unsigned int load:1;
 717   unsigned int modrm:1;
 718   unsigned int jump:3;
 719   unsigned int floatmf:1;
 720   unsigned int floatr:1;
 721   unsigned int size:2;
 722   unsigned int checkregsize:1;
 723   unsigned int distinctdest:1;
 724   unsigned int mnemonicsize:2;
 725   unsigned int anysize:1;
 726   unsigned int no_bsuf:1;
 727   unsigned int no_wsuf:1;
 728   unsigned int no_lsuf:1;
 729   unsigned int no_ssuf:1;
 730   unsigned int no_qsuf:1;
 731   unsigned int no_ldsuf:1;
 732   unsigned int fwait:1;
 733   unsigned int isstring:2;
 734   unsigned int regmem:1;
 735   unsigned int bndprefixok:1;
 736   unsigned int regkludge:1;
 737   unsigned int implicit1stxmm0:1;
 738   unsigned int prefixok:3;
 739   unsigned int addrprefixopreg:1;
 740   unsigned int isprefix:1;
 741   unsigned int immext:1;
 742   unsigned int norex64:1;
 743   unsigned int ugh:1;
 744   unsigned int pseudovexprefix:1;
 745   unsigned int vex:2;
 746   unsigned int vexvvvv:2;
 747   unsigned int vexw:2;
 748   unsigned int opcodespace:4;
 749   unsigned int opcodeprefix:2;
 750   unsigned int vexsources:2;
 751   unsigned int sib:3;
 752   unsigned int sse2avx:1;
 753   unsigned int evex:3;
 754   unsigned int masking:2;
 755   unsigned int broadcast:3;
 756   unsigned int staticrounding:1;
 757   unsigned int sae:1;
 758   unsigned int disp8memshift:3;
 759   unsigned int nodefmask:1;
 760   unsigned int implicitquadgroup:1;
 761   unsigned int swapsources:1;
 762   unsigned int optimize:1;
 763   unsigned int attmnemonic:1;
 764   unsigned int attsyntax:1;
 765   unsigned int intelsyntax:1;
 766   unsigned int isa64:2;
 767 } i386_opcode_modifier;
 768
 769 /* Operand classes.  */
 770
 771 #define CLASS_WIDTH 4
 772 enum operand_class
 773 {
 774   ClassNone,
 775   Reg, /* GPRs and FP regs, distinguished by operand size */
 776   SReg, /* Segment register */
 777   RegCR, /* Control register */
 778   RegDR, /* Debug register */
 779   RegTR, /* Test register */
 780   RegMMX, /* MMX register */
 781   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 782   RegMask, /* Vector Mask register */
 783   RegBND, /* Bound register */
 784 };
 785
 786 /* Special operand instances.  */
 787
 788 #define INSTANCE_WIDTH 3
 789 enum operand_instance
 790 {
 791   InstanceNone,
 792   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 793   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 794   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 795   RegB,  /* %bl / %bx / %ebx / %rbx */
 796 };
 797
 798 /* Position of operand_type bits.  */
 799
 800 enum
 801 {
 802   /* Class and Instance */
 803   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 804   /* 1 bit immediate */
 805   Imm1,
 806   /* 8 bit immediate */
 807   Imm8,
 808   /* 8 bit immediate sign extended */
 809   Imm8S,
 810   /* 16 bit immediate */
 811   Imm16,
 812   /* 32 bit immediate */
 813   Imm32,
 814   /* 32 bit immediate sign extended */
 815   Imm32S,
 816   /* 64 bit immediate */
 817   Imm64,
 818   /* 8bit/16bit/32bit displacements are used in different ways,
 819      depending on the instruction.  For jumps, they specify the
 820      size of the PC relative displacement, for instructions with
 821      memory operand, they specify the size of the offset relative
 822      to the base register, and for instructions with memory offset
 823      such as `mov 1234,%al' they specify the size of the offset
 824      relative to the segment base.  */
 825   /* 8 bit displacement */
 826   Disp8,
 827   /* 16 bit displacement */
 828   Disp16,
 829   /* 32 bit displacement (64-bit: sign-extended) */
 830   Disp32,
 831   /* 64 bit displacement */
 832   Disp64,
 833   /* Register which can be used for base or index in memory operand.  */
 834   BaseIndex,
 835   /* BYTE size. */
 836   Byte,
 837   /* WORD size. 2 byte */
 838   Word,
 839   /* DWORD size. 4 byte */
 840   Dword,
 841   /* FWORD size. 6 byte */
 842   Fword,
 843   /* QWORD size. 8 byte */
 844   Qword,
 845   /* TBYTE size. 10 byte */
 846   Tbyte,
 847   /* XMMWORD size. */
 848   Xmmword,
 849   /* YMMWORD size. */
 850   Ymmword,
 851   /* ZMMWORD size.  */
 852   Zmmword,
 853   /* TMMWORD size.  */
 854   Tmmword,
 855   /* Unspecified memory size.  */
 856   Unspecified,
 857
 858   /* The number of bits in i386_operand_type.  */
 859   OTNum
 860 };
 861
 862 #define OTNumOfUints \
 863   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 864 #define OTNumOfBits \
 865   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 866
 867 /* If you get a compiler error for zero width of the unused field,
 868    comment it out.  */
 869 #define OTUnused                OTNum
 870
 871 typedef union i386_operand_type
 872 {
 873   struct
 874     {
 875       unsigned int class:CLASS_WIDTH;
 876       unsigned int instance:INSTANCE_WIDTH;
 877       unsigned int imm1:1;
 878       unsigned int imm8:1;
 879       unsigned int imm8s:1;
 880       unsigned int imm16:1;
 881       unsigned int imm32:1;
 882       unsigned int imm32s:1;
 883       unsigned int imm64:1;
 884       unsigned int disp8:1;
 885       unsigned int disp16:1;
 886       unsigned int disp32:1;
 887       unsigned int disp64:1;
 888       unsigned int baseindex:1;
 889       unsigned int byte:1;
 890       unsigned int word:1;
 891       unsigned int dword:1;
 892       unsigned int fword:1;
 893       unsigned int qword:1;
 894       unsigned int tbyte:1;
 895       unsigned int xmmword:1;
 896       unsigned int ymmword:1;
 897       unsigned int zmmword:1;
 898       unsigned int tmmword:1;
 899       unsigned int unspecified:1;
 900 #ifdef OTUnused
 901       unsigned int unused:(OTNumOfBits - OTUnused);
 902 #endif
 903     } bitfield;
 904   unsigned int array[OTNumOfUints];
 905 } i386_operand_type;
 906
 907 typedef struct insn_template
 908 {
 909   /* instruction name sans width suffix ("mov" for movl insns) */
 910   char *name;
 911
 912   /* Bitfield arrangement is such that individual fields can be easily
 913      extracted (in native builds at least) - either by at most a masking
 914      operation (base_opcode, operands), or by just a (signed) right shift
 915      (extension_opcode).  Please try to maintain this property.  */
 916
 917   /* base_opcode is the fundamental opcode byte without optional
 918      prefix(es).  */
 919   unsigned int base_opcode:16;
 920 #define Opcode_D        0x2 /* Direction bit:
 921                                set if Reg --> Regmem;
 922                                unset if Regmem --> Reg. */
 923 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 924 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 925 #define Opcode_ExtD     0x1 /* Direction bit for extended opcode space insns. */
 926 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 927 /* The next value is arbitrary, as long as it's non-zero and distinct
 928    from all other values above.  */
 929 #define Opcode_VexW     0xf /* Operand order controlled by VEX.W. */
 930
 931   /* how many operands */
 932   unsigned int operands:3;
 933
 934   /* spare bits */
 935   unsigned int :4;
 936
 937 /* (Fake) base opcode value for pseudo prefixes.  */
 938 #define PSEUDO_PREFIX 0
 939
 940   /* extension_opcode is the 3 bit extension for group <n> insns.
 941      This field is also used to store the 8-bit opcode suffix for the
 942      AMD 3DNow! instructions.
 943      If this template has no extension opcode (the usual case) use None
 944      Instructions */
 945   signed int extension_opcode:9;
 946 #define None (-1)               /* If no extension_opcode is possible.  */
 947
 948 /* Pseudo prefixes.  */
 949 #define Prefix_Disp8            0       /* {disp8} */
 950 #define Prefix_Disp16           1       /* {disp16} */
 951 #define Prefix_Disp32           2       /* {disp32} */
 952 #define Prefix_Load             3       /* {load} */
 953 #define Prefix_Store            4       /* {store} */
 954 #define Prefix_VEX              5       /* {vex} */
 955 #define Prefix_VEX3             6       /* {vex3} */
 956 #define Prefix_EVEX             7       /* {evex} */
 957 #define Prefix_REX              8       /* {rex} */
 958 #define Prefix_NoOptimize       9       /* {nooptimize} */
 959
 960   /* the bits in opcode_modifier are used to generate the final opcode from
 961      the base_opcode.  These bits also are used to detect alternate forms of
 962      the same instruction */
 963   i386_opcode_modifier opcode_modifier;
 964
 965   /* cpu feature flags */
 966   i386_cpu_flags cpu_flags;
 967
 968   /* operand_types[i] describes the type of operand i.  This is made
 969      by OR'ing together all of the possible type masks.  (e.g.
 970      'operand_types[i] = Reg|Imm' specifies that operand i can be
 971      either a register or an immediate operand.  */
 972   i386_operand_type operand_types[MAX_OPERANDS];
 973 }
 974 insn_template;
 975
 976 extern const insn_template i386_optab[];
 977
 978 /* these are for register name --> number & type hash lookup */
 979 typedef struct
 980 {
 981   const char *reg_name;
 982   i386_operand_type reg_type;
 983   unsigned char reg_flags;
 984 #define RegRex      0x1  /* Extended register.  */
 985 #define RegRex64    0x2  /* Extended 8 bit register.  */
 986 #define RegVRex     0x4  /* Extended vector register.  */
 987   unsigned char reg_num;
 988 #define RegIP   ((unsigned char ) ~0)
 989 /* EIZ and RIZ are fake index registers.  */
 990 #define RegIZ   (RegIP - 1)
 991 /* FLAT is a fake segment register (Intel mode).  */
 992 #define RegFlat     ((unsigned char) ~0)
 993   signed char dw2_regnum[2];
 994 #define Dw2Inval (-1)
 995 }
 996 reg_entry;
 997
 998 extern const reg_entry i386_regtab[];
 999 extern const unsigned int i386_regtab_size;
1000 extern const unsigned char i386_seg_prefixes[6];