opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2023 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #include <limits.h>
  23 #ifndef CHAR_BIT
  24 #define CHAR_BIT 8
  25 #endif
  26
  27 /* Position of cpu flags bitfiled.  */
  28
  29 enum
  30 {
  31   /* i186 or better required */
  32   Cpu186 = 0,
  33   /* i286 or better required */
  34   Cpu286,
  35   /* i386 or better required */
  36   Cpu386,
  37   /* i486 or better required */
  38   Cpu486,
  39   /* i585 or better required */
  40   Cpu586,
  41   /* i686 or better required */
  42   Cpu686,
  43   /* CMOV Instruction support required */
  44   CpuCMOV,
  45   /* FXSR Instruction support required */
  46   CpuFXSR,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* LZCNT support required */
  88   CpuLZCNT,
  89   /* POPCNT support required */
  90   CpuPOPCNT,
  91   /* SSE4.1 support required */
  92   CpuSSE4_1,
  93   /* SSE4.2 support required */
  94   CpuSSE4_2,
  95   /* AVX support required */
  96   CpuAVX,
  97   /* AVX2 support required */
  98   CpuAVX2,
  99   /* Intel AVX-512 Foundation Instructions support required */
 100   CpuAVX512F,
 101   /* Intel AVX-512 Conflict Detection Instructions support required */
 102   CpuAVX512CD,
 103   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 104      required */
 105   CpuAVX512ER,
 106   /* Intel AVX-512 Prefetch Instructions support required */
 107   CpuAVX512PF,
 108   /* Intel AVX-512 VL Instructions support required.  */
 109   CpuAVX512VL,
 110   /* Intel AVX-512 DQ Instructions support required.  */
 111   CpuAVX512DQ,
 112   /* Intel AVX-512 BW Instructions support required.  */
 113   CpuAVX512BW,
 114   /* Intel IAMCU support required */
 115   CpuIAMCU,
 116   /* Xsave/xrstor New Instructions support required */
 117   CpuXsave,
 118   /* Xsaveopt New Instructions support required */
 119   CpuXsaveopt,
 120   /* AES support required */
 121   CpuAES,
 122   /* PCLMUL support required */
 123   CpuPCLMUL,
 124   /* FMA support required */
 125   CpuFMA,
 126   /* FMA4 support required */
 127   CpuFMA4,
 128   /* XOP support required */
 129   CpuXOP,
 130   /* LWP support required */
 131   CpuLWP,
 132   /* BMI support required */
 133   CpuBMI,
 134   /* TBM support required */
 135   CpuTBM,
 136   /* MOVBE Instruction support required */
 137   CpuMovbe,
 138   /* CMPXCHG16B instruction support required.  */
 139   CpuCX16,
 140   /* EPT Instructions required */
 141   CpuEPT,
 142   /* RDTSCP Instruction support required */
 143   CpuRdtscp,
 144   /* FSGSBASE Instructions required */
 145   CpuFSGSBase,
 146   /* RDRND Instructions required */
 147   CpuRdRnd,
 148   /* F16C Instructions required */
 149   CpuF16C,
 150   /* Intel BMI2 support required */
 151   CpuBMI2,
 152   /* HLE support required */
 153   CpuHLE,
 154   /* RTM support required */
 155   CpuRTM,
 156   /* INVPCID Instructions required */
 157   CpuINVPCID,
 158   /* VMFUNC Instruction required */
 159   CpuVMFUNC,
 160   /* Intel MPX Instructions required  */
 161   CpuMPX,
 162   /* 64bit support available, used by -march= in assembler.  */
 163   CpuLM,
 164   /* RDRSEED instruction required.  */
 165   CpuRDSEED,
 166   /* Multi-presisionn add-carry instructions are required.  */
 167   CpuADX,
 168   /* Supports prefetchw and prefetch instructions.  */
 169   CpuPRFCHW,
 170   /* SMAP instructions required.  */
 171   CpuSMAP,
 172   /* SHA instructions required.  */
 173   CpuSHA,
 174   /* CLFLUSHOPT instruction required */
 175   CpuClflushOpt,
 176   /* XSAVES/XRSTORS instruction required */
 177   CpuXSAVES,
 178   /* XSAVEC instruction required */
 179   CpuXSAVEC,
 180   /* PREFETCHWT1 instruction required */
 181   CpuPREFETCHWT1,
 182   /* SE1 instruction required */
 183   CpuSE1,
 184   /* CLWB instruction required */
 185   CpuCLWB,
 186   /* Intel AVX-512 IFMA Instructions support required.  */
 187   CpuAVX512IFMA,
 188   /* Intel AVX-512 VBMI Instructions support required.  */
 189   CpuAVX512VBMI,
 190   /* Intel AVX-512 4FMAPS Instructions support required.  */
 191   CpuAVX512_4FMAPS,
 192   /* Intel AVX-512 4VNNIW Instructions support required.  */
 193   CpuAVX512_4VNNIW,
 194   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 195   CpuAVX512_VPOPCNTDQ,
 196   /* Intel AVX-512 VBMI2 Instructions support required.  */
 197   CpuAVX512_VBMI2,
 198   /* Intel AVX-512 VNNI Instructions support required.  */
 199   CpuAVX512_VNNI,
 200   /* Intel AVX-512 BITALG Instructions support required.  */
 201   CpuAVX512_BITALG,
 202   /* Intel AVX-512 BF16 Instructions support required.  */
 203   CpuAVX512_BF16,
 204   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 205   CpuAVX512_VP2INTERSECT,
 206   /* TDX Instructions support required.  */
 207   CpuTDX,
 208   /* Intel AVX VNNI Instructions support required.  */
 209   CpuAVX_VNNI,
 210   /* Intel AVX-512 FP16 Instructions support required.  */
 211   CpuAVX512_FP16,
 212   /* PREFETCHI instruction required */
 213   CpuPREFETCHI,
 214   /* Intel AVX IFMA Instructions support required.  */
 215   CpuAVX_IFMA,
 216   /* Intel AVX VNNI-INT8 Instructions support required.  */
 217   CpuAVX_VNNI_INT8,
 218   /* Intel CMPccXADD instructions support required.  */
 219   CpuCMPCCXADD,
 220   /* Intel WRMSRNS Instructions support required */
 221   CpuWRMSRNS,
 222   /* Intel MSRLIST Instructions support required.  */
 223   CpuMSRLIST,
 224   /* Intel AVX NE CONVERT Instructions support required.  */
 225   CpuAVX_NE_CONVERT,
 226   /* Intel RAO INT Instructions support required.  */
 227   CpuRAO_INT,
 228   /* mwaitx instruction required */
 229   CpuMWAITX,
 230   /* Clzero instruction required */
 231   CpuCLZERO,
 232   /* OSPKE instruction required */
 233   CpuOSPKE,
 234   /* RDPID instruction required */
 235   CpuRDPID,
 236   /* PTWRITE instruction required */
 237   CpuPTWRITE,
 238   /* CET instructions support required */
 239   CpuIBT,
 240   CpuSHSTK,
 241   /* AMX-INT8 instructions required */
 242   CpuAMX_INT8,
 243   /* AMX-BF16 instructions required */
 244   CpuAMX_BF16,
 245   /* AMX-FP16 instructions required */
 246   CpuAMX_FP16,
 247   /* AMX-TILE instructions required */
 248   CpuAMX_TILE,
 249   /* GFNI instructions required */
 250   CpuGFNI,
 251   /* VAES instructions required */
 252   CpuVAES,
 253   /* VPCLMULQDQ instructions required */
 254   CpuVPCLMULQDQ,
 255   /* WBNOINVD instructions required */
 256   CpuWBNOINVD,
 257   /* PCONFIG instructions required */
 258   CpuPCONFIG,
 259   /* WAITPKG instructions required */
 260   CpuWAITPKG,
 261   /* UINTR instructions required */
 262   CpuUINTR,
 263   /* CLDEMOTE instruction required */
 264   CpuCLDEMOTE,
 265   /* MOVDIRI instruction support required */
 266   CpuMOVDIRI,
 267   /* MOVDIRR64B instruction required */
 268   CpuMOVDIR64B,
 269   /* ENQCMD instruction required */
 270   CpuENQCMD,
 271   /* SERIALIZE instruction required */
 272   CpuSERIALIZE,
 273   /* RDPRU instruction required */
 274   CpuRDPRU,
 275   /* MCOMMIT instruction required */
 276   CpuMCOMMIT,
 277   /* SEV-ES instruction(s) required */
 278   CpuSEV_ES,
 279   /* TSXLDTRK instruction required */
 280   CpuTSXLDTRK,
 281   /* KL instruction support required */
 282   CpuKL,
 283   /* WideKL instruction support required */
 284   CpuWideKL,
 285   /* HRESET instruction required */
 286   CpuHRESET,
 287   /* INVLPGB instructions required */
 288   CpuINVLPGB,
 289   /* TLBSYNC instructions required */
 290   CpuTLBSYNC,
 291   /* SNP instructions required */
 292   CpuSNP,
 293   /* RMPQUERY instruction required */
 294   CpuRMPQUERY,
 295
 296   /* NOTE: These last three items need to remain last and in this order. */
 297
 298   /* 64bit support required  */
 299   Cpu64,
 300   /* Not supported in the 64bit mode  */
 301   CpuNo64,
 302   /* The last bitfield in i386_cpu_flags.  */
 303   CpuMax = CpuNo64
 304 };
 305
 306 #define CpuNumOfUints \
 307   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 308 #define CpuNumOfBits \
 309   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 310
 311 /* If you get a compiler error for zero width of the unused field,
 312    comment it out.  */
 313 #define CpuUnused       (CpuMax + 1)
 314
 315 /* We can check if an instruction is available with array instead
 316    of bitfield. */
 317 typedef union i386_cpu_flags
 318 {
 319   struct
 320     {
 321       unsigned int cpui186:1;
 322       unsigned int cpui286:1;
 323       unsigned int cpui386:1;
 324       unsigned int cpui486:1;
 325       unsigned int cpui586:1;
 326       unsigned int cpui686:1;
 327       unsigned int cpucmov:1;
 328       unsigned int cpufxsr:1;
 329       unsigned int cpuclflush:1;
 330       unsigned int cpunop:1;
 331       unsigned int cpusyscall:1;
 332       unsigned int cpu8087:1;
 333       unsigned int cpu287:1;
 334       unsigned int cpu387:1;
 335       unsigned int cpu687:1;
 336       unsigned int cpufisttp:1;
 337       unsigned int cpummx:1;
 338       unsigned int cpusse:1;
 339       unsigned int cpusse2:1;
 340       unsigned int cpua3dnow:1;
 341       unsigned int cpua3dnowa:1;
 342       unsigned int cpusse3:1;
 343       unsigned int cpupadlock:1;
 344       unsigned int cpusvme:1;
 345       unsigned int cpuvmx:1;
 346       unsigned int cpusmx:1;
 347       unsigned int cpussse3:1;
 348       unsigned int cpusse4a:1;
 349       unsigned int cpulzcnt:1;
 350       unsigned int cpupopcnt:1;
 351       unsigned int cpusse4_1:1;
 352       unsigned int cpusse4_2:1;
 353       unsigned int cpuavx:1;
 354       unsigned int cpuavx2:1;
 355       unsigned int cpuavx512f:1;
 356       unsigned int cpuavx512cd:1;
 357       unsigned int cpuavx512er:1;
 358       unsigned int cpuavx512pf:1;
 359       unsigned int cpuavx512vl:1;
 360       unsigned int cpuavx512dq:1;
 361       unsigned int cpuavx512bw:1;
 362       unsigned int cpuiamcu:1;
 363       unsigned int cpuxsave:1;
 364       unsigned int cpuxsaveopt:1;
 365       unsigned int cpuaes:1;
 366       unsigned int cpupclmul:1;
 367       unsigned int cpufma:1;
 368       unsigned int cpufma4:1;
 369       unsigned int cpuxop:1;
 370       unsigned int cpulwp:1;
 371       unsigned int cpubmi:1;
 372       unsigned int cputbm:1;
 373       unsigned int cpumovbe:1;
 374       unsigned int cpucx16:1;
 375       unsigned int cpuept:1;
 376       unsigned int cpurdtscp:1;
 377       unsigned int cpufsgsbase:1;
 378       unsigned int cpurdrnd:1;
 379       unsigned int cpuf16c:1;
 380       unsigned int cpubmi2:1;
 381       unsigned int cpuhle:1;
 382       unsigned int cpurtm:1;
 383       unsigned int cpuinvpcid:1;
 384       unsigned int cpuvmfunc:1;
 385       unsigned int cpumpx:1;
 386       unsigned int cpulm:1;
 387       unsigned int cpurdseed:1;
 388       unsigned int cpuadx:1;
 389       unsigned int cpuprfchw:1;
 390       unsigned int cpusmap:1;
 391       unsigned int cpusha:1;
 392       unsigned int cpuclflushopt:1;
 393       unsigned int cpuxsaves:1;
 394       unsigned int cpuxsavec:1;
 395       unsigned int cpuprefetchwt1:1;
 396       unsigned int cpuse1:1;
 397       unsigned int cpuclwb:1;
 398       unsigned int cpuavx512ifma:1;
 399       unsigned int cpuavx512vbmi:1;
 400       unsigned int cpuavx512_4fmaps:1;
 401       unsigned int cpuavx512_4vnniw:1;
 402       unsigned int cpuavx512_vpopcntdq:1;
 403       unsigned int cpuavx512_vbmi2:1;
 404       unsigned int cpuavx512_vnni:1;
 405       unsigned int cpuavx512_bitalg:1;
 406       unsigned int cpuavx512_bf16:1;
 407       unsigned int cpuavx512_vp2intersect:1;
 408       unsigned int cputdx:1;
 409       unsigned int cpuavx_vnni:1;
 410       unsigned int cpuavx512_fp16:1;
 411       unsigned int cpuprefetchi:1;
 412       unsigned int cpuavx_ifma:1;
 413       unsigned int cpuavx_vnni_int8:1;
 414       unsigned int cpucmpccxadd:1;
 415       unsigned int cpuwrmsrns:1;
 416       unsigned int cpumsrlist:1;
 417       unsigned int cpuavx_ne_convert:1;
 418       unsigned int cpurao_int:1;
 419       unsigned int cpumwaitx:1;
 420       unsigned int cpuclzero:1;
 421       unsigned int cpuospke:1;
 422       unsigned int cpurdpid:1;
 423       unsigned int cpuptwrite:1;
 424       unsigned int cpuibt:1;
 425       unsigned int cpushstk:1;
 426       unsigned int cpuamx_int8:1;
 427       unsigned int cpuamx_bf16:1;
 428       unsigned int cpuamx_fp16:1;
 429       unsigned int cpuamx_tile:1;
 430       unsigned int cpugfni:1;
 431       unsigned int cpuvaes:1;
 432       unsigned int cpuvpclmulqdq:1;
 433       unsigned int cpuwbnoinvd:1;
 434       unsigned int cpupconfig:1;
 435       unsigned int cpuwaitpkg:1;
 436       unsigned int cpuuintr:1;
 437       unsigned int cpucldemote:1;
 438       unsigned int cpumovdiri:1;
 439       unsigned int cpumovdir64b:1;
 440       unsigned int cpuenqcmd:1;
 441       unsigned int cpuserialize:1;
 442       unsigned int cpurdpru:1;
 443       unsigned int cpumcommit:1;
 444       unsigned int cpusev_es:1;
 445       unsigned int cputsxldtrk:1;
 446       unsigned int cpukl:1;
 447       unsigned int cpuwidekl:1;
 448       unsigned int cpuhreset:1;
 449       unsigned int cpuinvlpgb:1;
 450       unsigned int cputlbsync:1;
 451       unsigned int cpusnp:1;
 452       unsigned int cpurmpquery:1;
 453       /* NOTE: These last three fields need to remain last and in this order. */
 454       unsigned int cpu64:1;
 455       unsigned int cpuno64:1;
 456 #ifdef CpuUnused
 457       unsigned int unused:(CpuNumOfBits - CpuUnused);
 458 #endif
 459     } bitfield;
 460   unsigned int array[CpuNumOfUints];
 461 } i386_cpu_flags;
 462
 463 /* Position of opcode_modifier bits.  */
 464
 465 enum
 466 {
 467   /* has direction bit. */
 468   D = 0,
 469   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 470      canonical way; the base_opcode field should hold the encoding for byte
 471      operands  */
 472   W,
 473   /* load form instruction. Must be placed before store form.  */
 474   Load,
 475   /* insn has a modrm byte. */
 476   Modrm,
 477   /* special case for jump insns; value has to be 1 */
 478 #define JUMP 1
 479   /* call and jump */
 480 #define JUMP_DWORD 2
 481   /* loop and jecxz */
 482 #define JUMP_BYTE 3
 483   /* special case for intersegment leaps/calls */
 484 #define JUMP_INTERSEGMENT 4
 485   /* absolute address for jump */
 486 #define JUMP_ABSOLUTE 5
 487   Jump,
 488   /* FP insn memory format bit, sized by 0x4 */
 489   FloatMF,
 490   /* needs size prefix if in 32-bit mode */
 491 #define SIZE16 1
 492   /* needs size prefix if in 16-bit mode */
 493 #define SIZE32 2
 494   /* needs size prefix if in 64-bit mode */
 495 #define SIZE64 3
 496   Size,
 497   /* Check that operand sizes match.  */
 498   CheckOperandSize,
 499   /* any memory size */
 500 #define ANY_SIZE 1
 501   /* fake an extra reg operand for clr, imul and special register
 502      processing for some instructions.  */
 503 #define REG_KLUDGE 2
 504   /* deprecated fp insn, gets a warning */
 505 #define UGH 3
 506   /* An implicit xmm0 as the first operand */
 507 #define IMPLICIT_1ST_XMM0 4
 508   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 509      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 510    */
 511 #define IMPLICIT_QUAD_GROUP 5
 512   /* Two source operands are swapped.  */
 513 #define SWAP_SOURCES 6
 514   /* Default mask isn't allowed.  */
 515 #define NO_DEFAULT_MASK 7
 516   /* Address prefix changes register operand */
 517 #define ADDR_PREFIX_OP_REG 8
 518   /* Instrucion requires that destination must be distinct from source
 519      registers.  */
 520 #define DISTINCT_DEST 9
 521   OperandConstraint,
 522   /* instruction ignores operand size prefix and in Intel mode ignores
 523      mnemonic size suffix check.  */
 524 #define IGNORESIZE      1
 525   /* default insn size depends on mode */
 526 #define DEFAULTSIZE     2
 527   MnemonicSize,
 528   /* b suffix on instruction illegal */
 529   No_bSuf,
 530   /* w suffix on instruction illegal */
 531   No_wSuf,
 532   /* l suffix on instruction illegal */
 533   No_lSuf,
 534   /* s suffix on instruction illegal */
 535   No_sSuf,
 536   /* q suffix on instruction illegal */
 537   No_qSuf,
 538   /* instruction needs FWAIT */
 539   FWait,
 540   /* IsString provides for a quick test for string instructions, and
 541      its actual value also indicates which of the operands (if any)
 542      requires use of the %es segment.  */
 543 #define IS_STRING_ES_OP0 2
 544 #define IS_STRING_ES_OP1 3
 545   IsString,
 546   /* RegMem is for instructions with a modrm byte where the register
 547      destination operand should be encoded in the mod and regmem fields.
 548      Normally, it will be encoded in the reg field. We add a RegMem
 549      flag to indicate that it should be encoded in the regmem field.  */
 550   RegMem,
 551   /* quick test if branch instruction is MPX supported */
 552   BNDPrefixOk,
 553 #define PrefixNone              0
 554 #define PrefixRep               1
 555 #define PrefixHLERelease        2 /* Okay with an XRELEASE (0xf3) prefix. */
 556 #define PrefixNoTrack           3
 557   /* Prefixes implying "LOCK okay" must come after Lock. All others have
 558      to come before.  */
 559 #define PrefixLock              4
 560 #define PrefixHLELock           5 /* Okay with a LOCK prefix.  */
 561 #define PrefixHLEAny            6 /* Okay with or without a LOCK prefix.  */
 562   PrefixOk,
 563   /* opcode is a prefix */
 564   IsPrefix,
 565   /* instruction has extension in 8 bit imm */
 566   ImmExt,
 567   /* instruction don't need Rex64 prefix.  */
 568   NoRex64,
 569   /* insn has VEX prefix:
 570         1: 128bit VEX prefix (or operand dependent).
 571         2: 256bit VEX prefix.
 572         3: Scalar VEX prefix.
 573    */
 574 #define VEX128          1
 575 #define VEX256          2
 576 #define VEXScalar       3
 577   Vex,
 578   /* How to encode VEX.vvvv:
 579      0: VEX.vvvv must be 1111b.
 580      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 581         the content of source registers will be preserved.
 582         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 583         where the content of first source register will be overwritten
 584         by the result.
 585         VEX.NDD2.  The second destination register operand is encoded in
 586         VEX.vvvv for instructions with 2 destination register operands.
 587         For assembler, there are no difference between VEX.NDS, VEX.DDS
 588         and VEX.NDD2.
 589      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 590      instructions with 1 destination register operand.
 591      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 592         of the operands can access a memory location.
 593    */
 594 #define VEXXDS  1
 595 #define VEXNDD  2
 596 #define VEXLWP  3
 597   VexVVVV,
 598   /* How the VEX.W bit is used:
 599      0: Set by the REX.W bit.
 600      1: VEX.W0.  Should always be 0.
 601      2: VEX.W1.  Should always be 1.
 602      3: VEX.WIG. The VEX.W bit is ignored.
 603    */
 604 #define VEXW0   1
 605 #define VEXW1   2
 606 #define VEXWIG  3
 607   VexW,
 608   /* Opcode encoding space (values chosen to be usable directly in
 609      VEX/XOP mmmmm and EVEX mm fields):
 610      0: Base opcode space.
 611      1: 0F opcode prefix / space.
 612      2: 0F38 opcode prefix / space.
 613      3: 0F3A opcode prefix / space.
 614      5: EVEXMAP5 opcode prefix / space.
 615      6: EVEXMAP6 opcode prefix / space.
 616      8: XOP 08 opcode space.
 617      9: XOP 09 opcode space.
 618      A: XOP 0A opcode space.
 619    */
 620 #define SPACE_BASE      0
 621 #define SPACE_0F        1
 622 #define SPACE_0F38      2
 623 #define SPACE_0F3A      3
 624 #define SPACE_EVEXMAP5  5
 625 #define SPACE_EVEXMAP6  6
 626 #define SPACE_XOP08     8
 627 #define SPACE_XOP09     9
 628 #define SPACE_XOP0A     0xA
 629   OpcodeSpace,
 630   /* Opcode prefix (values chosen to be usable directly in
 631      VEX/XOP/EVEX pp fields):
 632      0: None
 633      1: Add 0x66 opcode prefix.
 634      2: Add 0xf3 opcode prefix.
 635      3: Add 0xf2 opcode prefix.
 636    */
 637 #define PREFIX_NONE     0
 638 #define PREFIX_0X66     1
 639 #define PREFIX_0XF3     2
 640 #define PREFIX_0XF2     3
 641   OpcodePrefix,
 642   /* number of VEX source operands:
 643      0: <= 2 source operands.
 644      1: 2 XOP source operands.
 645      2: 3 source operands.
 646    */
 647 #define XOP2SOURCES     1
 648 #define VEX3SOURCES     2
 649   VexSources,
 650   /* Instruction with a mandatory SIB byte:
 651         1: 128bit vector register.
 652         2: 256bit vector register.
 653         3: 512bit vector register.
 654    */
 655 #define VECSIB128       1
 656 #define VECSIB256       2
 657 #define VECSIB512       3
 658 #define SIBMEM          4
 659   SIB,
 660
 661   /* SSE to AVX support required */
 662   SSE2AVX,
 663
 664   /* insn has EVEX prefix:
 665         1: 512bit EVEX prefix.
 666         2: 128bit EVEX prefix.
 667         3: 256bit EVEX prefix.
 668         4: Length-ignored (LIG) EVEX prefix.
 669         5: Length determined from actual operands.
 670    */
 671 #define EVEX512                1
 672 #define EVEX128                2
 673 #define EVEX256                3
 674 #define EVEXLIG                4
 675 #define EVEXDYN                5
 676   EVex,
 677
 678   /* AVX512 masking support:
 679         1: Zeroing or merging masking depending on operands.
 680         2: Merging-masking.
 681         3: Both zeroing and merging masking.
 682    */
 683 #define DYNAMIC_MASKING 1
 684 #define MERGING_MASKING 2
 685 #define BOTH_MASKING    3
 686   Masking,
 687
 688   /* AVX512 broadcast support.  The number of bytes to broadcast is
 689      1 << (Broadcast - 1):
 690         1: Byte broadcast.
 691         2: Word broadcast.
 692         3: Dword broadcast.
 693         4: Qword broadcast.
 694    */
 695 #define BYTE_BROADCAST  1
 696 #define WORD_BROADCAST  2
 697 #define DWORD_BROADCAST 3
 698 #define QWORD_BROADCAST 4
 699   Broadcast,
 700
 701   /* Static rounding control is supported.  */
 702   StaticRounding,
 703
 704   /* Supress All Exceptions is supported.  */
 705   SAE,
 706
 707   /* Compressed Disp8*N attribute.  */
 708 #define DISP8_SHIFT_VL 7
 709   Disp8MemShift,
 710
 711   /* Support encoding optimization.  */
 712   Optimize,
 713
 714   /* AT&T mnemonic.  */
 715   ATTMnemonic,
 716   /* AT&T syntax.  */
 717   ATTSyntax,
 718   /* Intel syntax.  */
 719   IntelSyntax,
 720   /* ISA64: Don't change the order without other code adjustments.
 721         0: Common to AMD64 and Intel64.
 722         1: AMD64.
 723         2: Intel64.
 724         3: Only in Intel64.
 725    */
 726 #define AMD64           1
 727 #define INTEL64         2
 728 #define INTEL64ONLY     3
 729   ISA64,
 730   /* The last bitfield in i386_opcode_modifier.  */
 731   Opcode_Modifier_Num
 732 };
 733
 734 typedef struct i386_opcode_modifier
 735 {
 736   unsigned int d:1;
 737   unsigned int w:1;
 738   unsigned int load:1;
 739   unsigned int modrm:1;
 740   unsigned int jump:3;
 741   unsigned int floatmf:1;
 742   unsigned int size:2;
 743   unsigned int checkoperandsize:1;
 744   unsigned int operandconstraint:4;
 745   unsigned int mnemonicsize:2;
 746   unsigned int no_bsuf:1;
 747   unsigned int no_wsuf:1;
 748   unsigned int no_lsuf:1;
 749   unsigned int no_ssuf:1;
 750   unsigned int no_qsuf:1;
 751   unsigned int fwait:1;
 752   unsigned int isstring:2;
 753   unsigned int regmem:1;
 754   unsigned int bndprefixok:1;
 755   unsigned int prefixok:3;
 756   unsigned int isprefix:1;
 757   unsigned int immext:1;
 758   unsigned int norex64:1;
 759   unsigned int vex:2;
 760   unsigned int vexvvvv:2;
 761   unsigned int vexw:2;
 762   unsigned int opcodespace:4;
 763   unsigned int opcodeprefix:2;
 764   unsigned int vexsources:2;
 765   unsigned int sib:3;
 766   unsigned int sse2avx:1;
 767   unsigned int evex:3;
 768   unsigned int masking:2;
 769   unsigned int broadcast:3;
 770   unsigned int staticrounding:1;
 771   unsigned int sae:1;
 772   unsigned int disp8memshift:3;
 773   unsigned int optimize:1;
 774   unsigned int attmnemonic:1;
 775   unsigned int attsyntax:1;
 776   unsigned int intelsyntax:1;
 777   unsigned int isa64:2;
 778 } i386_opcode_modifier;
 779
 780 /* Operand classes.  */
 781
 782 #define CLASS_WIDTH 4
 783 enum operand_class
 784 {
 785   ClassNone,
 786   Reg, /* GPRs and FP regs, distinguished by operand size */
 787   SReg, /* Segment register */
 788   RegCR, /* Control register */
 789   RegDR, /* Debug register */
 790   RegTR, /* Test register */
 791   RegMMX, /* MMX register */
 792   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 793   RegMask, /* Vector Mask register */
 794   RegBND, /* Bound register */
 795 };
 796
 797 /* Special operand instances.  */
 798
 799 #define INSTANCE_WIDTH 3
 800 enum operand_instance
 801 {
 802   InstanceNone,
 803   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 804   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 805   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 806   RegB,  /* %bl / %bx / %ebx / %rbx */
 807 };
 808
 809 /* Position of operand_type bits.  */
 810
 811 enum
 812 {
 813   /* Class and Instance */
 814   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 815   /* 1 bit immediate */
 816   Imm1,
 817   /* 8 bit immediate */
 818   Imm8,
 819   /* 8 bit immediate sign extended */
 820   Imm8S,
 821   /* 16 bit immediate */
 822   Imm16,
 823   /* 32 bit immediate */
 824   Imm32,
 825   /* 32 bit immediate sign extended */
 826   Imm32S,
 827   /* 64 bit immediate */
 828   Imm64,
 829   /* 8bit/16bit/32bit displacements are used in different ways,
 830      depending on the instruction.  For jumps, they specify the
 831      size of the PC relative displacement, for instructions with
 832      memory operand, they specify the size of the offset relative
 833      to the base register, and for instructions with memory offset
 834      such as `mov 1234,%al' they specify the size of the offset
 835      relative to the segment base.  */
 836   /* 8 bit displacement */
 837   Disp8,
 838   /* 16 bit displacement */
 839   Disp16,
 840   /* 32 bit displacement (64-bit: sign-extended) */
 841   Disp32,
 842   /* 64 bit displacement */
 843   Disp64,
 844   /* Register which can be used for base or index in memory operand.  */
 845   BaseIndex,
 846   /* BYTE size. */
 847   Byte,
 848   /* WORD size. 2 byte */
 849   Word,
 850   /* DWORD size. 4 byte */
 851   Dword,
 852   /* FWORD size. 6 byte */
 853   Fword,
 854   /* QWORD size. 8 byte */
 855   Qword,
 856   /* TBYTE size. 10 byte */
 857   Tbyte,
 858   /* XMMWORD size. */
 859   Xmmword,
 860   /* YMMWORD size. */
 861   Ymmword,
 862   /* ZMMWORD size.  */
 863   Zmmword,
 864   /* TMMWORD size.  */
 865   Tmmword,
 866   /* Unspecified memory size.  */
 867   Unspecified,
 868
 869   /* The number of bits in i386_operand_type.  */
 870   OTNum
 871 };
 872
 873 #define OTNumOfUints \
 874   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 875 #define OTNumOfBits \
 876   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 877
 878 /* If you get a compiler error for zero width of the unused field,
 879    comment it out.  */
 880 #define OTUnused                OTNum
 881
 882 typedef union i386_operand_type
 883 {
 884   struct
 885     {
 886       unsigned int class:CLASS_WIDTH;
 887       unsigned int instance:INSTANCE_WIDTH;
 888       unsigned int imm1:1;
 889       unsigned int imm8:1;
 890       unsigned int imm8s:1;
 891       unsigned int imm16:1;
 892       unsigned int imm32:1;
 893       unsigned int imm32s:1;
 894       unsigned int imm64:1;
 895       unsigned int disp8:1;
 896       unsigned int disp16:1;
 897       unsigned int disp32:1;
 898       unsigned int disp64:1;
 899       unsigned int baseindex:1;
 900       unsigned int byte:1;
 901       unsigned int word:1;
 902       unsigned int dword:1;
 903       unsigned int fword:1;
 904       unsigned int qword:1;
 905       unsigned int tbyte:1;
 906       unsigned int xmmword:1;
 907       unsigned int ymmword:1;
 908       unsigned int zmmword:1;
 909       unsigned int tmmword:1;
 910       unsigned int unspecified:1;
 911 #ifdef OTUnused
 912       unsigned int unused:(OTNumOfBits - OTUnused);
 913 #endif
 914     } bitfield;
 915   unsigned int array[OTNumOfUints];
 916 } i386_operand_type;
 917
 918 typedef struct insn_template
 919 {
 920   /* instruction name sans width suffix ("mov" for movl insns) */
 921   unsigned int mnem_off;
 922
 923   /* Bitfield arrangement is such that individual fields can be easily
 924      extracted (in native builds at least) - either by at most a masking
 925      operation (base_opcode, operands), or by just a (signed) right shift
 926      (extension_opcode).  Please try to maintain this property.  */
 927
 928   /* base_opcode is the fundamental opcode byte without optional
 929      prefix(es).  */
 930   unsigned int base_opcode:16;
 931 #define Opcode_D        0x2 /* Direction bit:
 932                                set if Reg --> Regmem;
 933                                unset if Regmem --> Reg. */
 934 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 935 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 936 #define Opcode_ExtD     0x1 /* Direction bit for extended opcode space insns. */
 937 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 938 /* The next value is arbitrary, as long as it's non-zero and distinct
 939    from all other values above.  */
 940 #define Opcode_VexW     0xf /* Operand order controlled by VEX.W. */
 941
 942   /* how many operands */
 943   unsigned int operands:3;
 944
 945   /* spare bits */
 946   unsigned int :4;
 947
 948 /* (Fake) base opcode value for pseudo prefixes.  */
 949 #define PSEUDO_PREFIX 0
 950
 951   /* extension_opcode is the 3 bit extension for group <n> insns.
 952      This field is also used to store the 8-bit opcode suffix for the
 953      AMD 3DNow! instructions.
 954      If this template has no extension opcode (the usual case) use None
 955      Instructions */
 956   signed int extension_opcode:9;
 957 #define None (-1)               /* If no extension_opcode is possible.  */
 958
 959 /* Pseudo prefixes.  */
 960 #define Prefix_Disp8            0       /* {disp8} */
 961 #define Prefix_Disp16           1       /* {disp16} */
 962 #define Prefix_Disp32           2       /* {disp32} */
 963 #define Prefix_Load             3       /* {load} */
 964 #define Prefix_Store            4       /* {store} */
 965 #define Prefix_VEX              5       /* {vex} */
 966 #define Prefix_VEX3             6       /* {vex3} */
 967 #define Prefix_EVEX             7       /* {evex} */
 968 #define Prefix_REX              8       /* {rex} */
 969 #define Prefix_NoOptimize       9       /* {nooptimize} */
 970
 971   /* the bits in opcode_modifier are used to generate the final opcode from
 972      the base_opcode.  These bits also are used to detect alternate forms of
 973      the same instruction */
 974   i386_opcode_modifier opcode_modifier;
 975
 976   /* cpu feature flags */
 977   i386_cpu_flags cpu_flags;
 978
 979   /* operand_types[i] describes the type of operand i.  This is made
 980      by OR'ing together all of the possible type masks.  (e.g.
 981      'operand_types[i] = Reg|Imm' specifies that operand i can be
 982      either a register or an immediate operand.  */
 983   i386_operand_type operand_types[MAX_OPERANDS];
 984 }
 985 insn_template;
 986
 987 /* these are for register name --> number & type hash lookup */
 988 typedef struct
 989 {
 990   const char *reg_name;
 991   i386_operand_type reg_type;
 992   unsigned char reg_flags;
 993 #define RegRex      0x1  /* Extended register.  */
 994 #define RegRex64    0x2  /* Extended 8 bit register.  */
 995 #define RegVRex     0x4  /* Extended vector register.  */
 996   unsigned char reg_num;
 997 #define RegIP   ((unsigned char ) ~0)
 998 /* EIZ and RIZ are fake index registers.  */
 999 #define RegIZ   (RegIP - 1)
1000 /* FLAT is a fake segment register (Intel mode).  */
1001 #define RegFlat     ((unsigned char) ~0)
1002   signed char dw2_regnum[2];
1003 #define Dw2Inval (-1)
1004 }
1005 reg_entry;