opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CMOV Instruction support required */
  47   CpuCMOV,
  48   /* FXSR Instruction support required */
  49   CpuFXSR,
  50   /* CLFLUSH Instruction support required */
  51   CpuClflush,
  52   /* NOP Instruction support required */
  53   CpuNop,
  54   /* SYSCALL Instructions support required */
  55   CpuSYSCALL,
  56   /* Floating point support required */
  57   Cpu8087,
  58   /* i287 support required */
  59   Cpu287,
  60   /* i387 support required */
  61   Cpu387,
  62   /* i686 and floating point support required */
  63   Cpu687,
  64   /* SSE3 and floating point support required */
  65   CpuFISTTP,
  66   /* MMX support required */
  67   CpuMMX,
  68   /* SSE support required */
  69   CpuSSE,
  70   /* SSE2 support required */
  71   CpuSSE2,
  72   /* 3dnow! support required */
  73   Cpu3dnow,
  74   /* 3dnow! Extensions support required */
  75   Cpu3dnowA,
  76   /* SSE3 support required */
  77   CpuSSE3,
  78   /* VIA PadLock required */
  79   CpuPadLock,
  80   /* AMD Secure Virtual Machine Ext-s required */
  81   CpuSVME,
  82   /* VMX Instructions required */
  83   CpuVMX,
  84   /* SMX Instructions required */
  85   CpuSMX,
  86   /* SSSE3 support required */
  87   CpuSSSE3,
  88   /* SSE4a support required */
  89   CpuSSE4a,
  90   /* LZCNT support required */
  91   CpuLZCNT,
  92   /* POPCNT support required */
  93   CpuPOPCNT,
  94   /* SSE4.1 support required */
  95   CpuSSE4_1,
  96   /* SSE4.2 support required */
  97   CpuSSE4_2,
  98   /* AVX support required */
  99   CpuAVX,
 100   /* AVX2 support required */
 101   CpuAVX2,
 102   /* Intel AVX-512 Foundation Instructions support required */
 103   CpuAVX512F,
 104   /* Intel AVX-512 Conflict Detection Instructions support required */
 105   CpuAVX512CD,
 106   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 107      required */
 108   CpuAVX512ER,
 109   /* Intel AVX-512 Prefetch Instructions support required */
 110   CpuAVX512PF,
 111   /* Intel AVX-512 VL Instructions support required.  */
 112   CpuAVX512VL,
 113   /* Intel AVX-512 DQ Instructions support required.  */
 114   CpuAVX512DQ,
 115   /* Intel AVX-512 BW Instructions support required.  */
 116   CpuAVX512BW,
 117   /* Intel L1OM support required */
 118   CpuL1OM,
 119   /* Intel K1OM support required */
 120   CpuK1OM,
 121   /* Intel IAMCU support required */
 122   CpuIAMCU,
 123   /* Xsave/xrstor New Instructions support required */
 124   CpuXsave,
 125   /* Xsaveopt New Instructions support required */
 126   CpuXsaveopt,
 127   /* AES support required */
 128   CpuAES,
 129   /* PCLMUL support required */
 130   CpuPCLMUL,
 131   /* FMA support required */
 132   CpuFMA,
 133   /* FMA4 support required */
 134   CpuFMA4,
 135   /* XOP support required */
 136   CpuXOP,
 137   /* LWP support required */
 138   CpuLWP,
 139   /* BMI support required */
 140   CpuBMI,
 141   /* TBM support required */
 142   CpuTBM,
 143   /* MOVBE Instruction support required */
 144   CpuMovbe,
 145   /* CMPXCHG16B instruction support required.  */
 146   CpuCX16,
 147   /* EPT Instructions required */
 148   CpuEPT,
 149   /* RDTSCP Instruction support required */
 150   CpuRdtscp,
 151   /* FSGSBASE Instructions required */
 152   CpuFSGSBase,
 153   /* RDRND Instructions required */
 154   CpuRdRnd,
 155   /* F16C Instructions required */
 156   CpuF16C,
 157   /* Intel BMI2 support required */
 158   CpuBMI2,
 159   /* HLE support required */
 160   CpuHLE,
 161   /* RTM support required */
 162   CpuRTM,
 163   /* INVPCID Instructions required */
 164   CpuINVPCID,
 165   /* VMFUNC Instruction required */
 166   CpuVMFUNC,
 167   /* Intel MPX Instructions required  */
 168   CpuMPX,
 169   /* 64bit support available, used by -march= in assembler.  */
 170   CpuLM,
 171   /* RDRSEED instruction required.  */
 172   CpuRDSEED,
 173   /* Multi-presisionn add-carry instructions are required.  */
 174   CpuADX,
 175   /* Supports prefetchw and prefetch instructions.  */
 176   CpuPRFCHW,
 177   /* SMAP instructions required.  */
 178   CpuSMAP,
 179   /* SHA instructions required.  */
 180   CpuSHA,
 181   /* CLFLUSHOPT instruction required */
 182   CpuClflushOpt,
 183   /* XSAVES/XRSTORS instruction required */
 184   CpuXSAVES,
 185   /* XSAVEC instruction required */
 186   CpuXSAVEC,
 187   /* PREFETCHWT1 instruction required */
 188   CpuPREFETCHWT1,
 189   /* SE1 instruction required */
 190   CpuSE1,
 191   /* CLWB instruction required */
 192   CpuCLWB,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* Intel AVX-512 4FMAPS Instructions support required.  */
 198   CpuAVX512_4FMAPS,
 199   /* Intel AVX-512 4VNNIW Instructions support required.  */
 200   CpuAVX512_4VNNIW,
 201   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 202   CpuAVX512_VPOPCNTDQ,
 203   /* Intel AVX-512 VBMI2 Instructions support required.  */
 204   CpuAVX512_VBMI2,
 205   /* Intel AVX-512 VNNI Instructions support required.  */
 206   CpuAVX512_VNNI,
 207   /* Intel AVX-512 BITALG Instructions support required.  */
 208   CpuAVX512_BITALG,
 209   /* Intel AVX-512 BF16 Instructions support required.  */
 210   CpuAVX512_BF16,
 211   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 212   CpuAVX512_VP2INTERSECT,
 213   /* TDX Instructions support required.  */
 214   CpuTDX,
 215   /* Intel AVX VNNI Instructions support required.  */
 216   CpuAVX_VNNI,
 217   /* mwaitx instruction required */
 218   CpuMWAITX,
 219   /* Clzero instruction required */
 220   CpuCLZERO,
 221   /* OSPKE instruction required */
 222   CpuOSPKE,
 223   /* RDPID instruction required */
 224   CpuRDPID,
 225   /* PTWRITE instruction required */
 226   CpuPTWRITE,
 227   /* CET instructions support required */
 228   CpuIBT,
 229   CpuSHSTK,
 230   /* AMX-INT8 instructions required */
 231   CpuAMX_INT8,
 232   /* AMX-BF16 instructions required */
 233   CpuAMX_BF16,
 234   /* AMX-TILE instructions required */
 235   CpuAMX_TILE,
 236   /* GFNI instructions required */
 237   CpuGFNI,
 238   /* VAES instructions required */
 239   CpuVAES,
 240   /* VPCLMULQDQ instructions required */
 241   CpuVPCLMULQDQ,
 242   /* WBNOINVD instructions required */
 243   CpuWBNOINVD,
 244   /* PCONFIG instructions required */
 245   CpuPCONFIG,
 246   /* WAITPKG instructions required */
 247   CpuWAITPKG,
 248   /* UINTR instructions required */
 249   CpuUINTR,
 250   /* CLDEMOTE instruction required */
 251   CpuCLDEMOTE,
 252   /* MOVDIRI instruction support required */
 253   CpuMOVDIRI,
 254   /* MOVDIRR64B instruction required */
 255   CpuMOVDIR64B,
 256   /* ENQCMD instruction required */
 257   CpuENQCMD,
 258   /* SERIALIZE instruction required */
 259   CpuSERIALIZE,
 260   /* RDPRU instruction required */
 261   CpuRDPRU,
 262   /* MCOMMIT instruction required */
 263   CpuMCOMMIT,
 264   /* SEV-ES instruction(s) required */
 265   CpuSEV_ES,
 266   /* TSXLDTRK instruction required */
 267   CpuTSXLDTRK,
 268   /* KL instruction support required */
 269   CpuKL,
 270   /* WideKL instruction support required */
 271   CpuWideKL,
 272   /* HRESET instruction required */
 273   CpuHRESET,
 274   /* INVLPGB instructions required */
 275   CpuINVLPGB,
 276   /* TLBSYNC instructions required */
 277   CpuTLBSYNC,
 278   /* SNP instructions required */
 279   CpuSNP,
 280   /* 64bit support required  */
 281   Cpu64,
 282   /* Not supported in the 64bit mode  */
 283   CpuNo64,
 284   /* The last bitfield in i386_cpu_flags.  */
 285   CpuMax = CpuNo64
 286 };
 287
 288 #define CpuNumOfUints \
 289   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 290 #define CpuNumOfBits \
 291   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 292
 293 /* If you get a compiler error for zero width of the unused field,
 294    comment it out.  */
 295 #define CpuUnused       (CpuMax + 1)
 296
 297 /* We can check if an instruction is available with array instead
 298    of bitfield. */
 299 typedef union i386_cpu_flags
 300 {
 301   struct
 302     {
 303       unsigned int cpui186:1;
 304       unsigned int cpui286:1;
 305       unsigned int cpui386:1;
 306       unsigned int cpui486:1;
 307       unsigned int cpui586:1;
 308       unsigned int cpui686:1;
 309       unsigned int cpucmov:1;
 310       unsigned int cpufxsr:1;
 311       unsigned int cpuclflush:1;
 312       unsigned int cpunop:1;
 313       unsigned int cpusyscall:1;
 314       unsigned int cpu8087:1;
 315       unsigned int cpu287:1;
 316       unsigned int cpu387:1;
 317       unsigned int cpu687:1;
 318       unsigned int cpufisttp:1;
 319       unsigned int cpummx:1;
 320       unsigned int cpusse:1;
 321       unsigned int cpusse2:1;
 322       unsigned int cpua3dnow:1;
 323       unsigned int cpua3dnowa:1;
 324       unsigned int cpusse3:1;
 325       unsigned int cpupadlock:1;
 326       unsigned int cpusvme:1;
 327       unsigned int cpuvmx:1;
 328       unsigned int cpusmx:1;
 329       unsigned int cpussse3:1;
 330       unsigned int cpusse4a:1;
 331       unsigned int cpulzcnt:1;
 332       unsigned int cpupopcnt:1;
 333       unsigned int cpusse4_1:1;
 334       unsigned int cpusse4_2:1;
 335       unsigned int cpuavx:1;
 336       unsigned int cpuavx2:1;
 337       unsigned int cpuavx512f:1;
 338       unsigned int cpuavx512cd:1;
 339       unsigned int cpuavx512er:1;
 340       unsigned int cpuavx512pf:1;
 341       unsigned int cpuavx512vl:1;
 342       unsigned int cpuavx512dq:1;
 343       unsigned int cpuavx512bw:1;
 344       unsigned int cpul1om:1;
 345       unsigned int cpuk1om:1;
 346       unsigned int cpuiamcu:1;
 347       unsigned int cpuxsave:1;
 348       unsigned int cpuxsaveopt:1;
 349       unsigned int cpuaes:1;
 350       unsigned int cpupclmul:1;
 351       unsigned int cpufma:1;
 352       unsigned int cpufma4:1;
 353       unsigned int cpuxop:1;
 354       unsigned int cpulwp:1;
 355       unsigned int cpubmi:1;
 356       unsigned int cputbm:1;
 357       unsigned int cpumovbe:1;
 358       unsigned int cpucx16:1;
 359       unsigned int cpuept:1;
 360       unsigned int cpurdtscp:1;
 361       unsigned int cpufsgsbase:1;
 362       unsigned int cpurdrnd:1;
 363       unsigned int cpuf16c:1;
 364       unsigned int cpubmi2:1;
 365       unsigned int cpuhle:1;
 366       unsigned int cpurtm:1;
 367       unsigned int cpuinvpcid:1;
 368       unsigned int cpuvmfunc:1;
 369       unsigned int cpumpx:1;
 370       unsigned int cpulm:1;
 371       unsigned int cpurdseed:1;
 372       unsigned int cpuadx:1;
 373       unsigned int cpuprfchw:1;
 374       unsigned int cpusmap:1;
 375       unsigned int cpusha:1;
 376       unsigned int cpuclflushopt:1;
 377       unsigned int cpuxsaves:1;
 378       unsigned int cpuxsavec:1;
 379       unsigned int cpuprefetchwt1:1;
 380       unsigned int cpuse1:1;
 381       unsigned int cpuclwb:1;
 382       unsigned int cpuavx512ifma:1;
 383       unsigned int cpuavx512vbmi:1;
 384       unsigned int cpuavx512_4fmaps:1;
 385       unsigned int cpuavx512_4vnniw:1;
 386       unsigned int cpuavx512_vpopcntdq:1;
 387       unsigned int cpuavx512_vbmi2:1;
 388       unsigned int cpuavx512_vnni:1;
 389       unsigned int cpuavx512_bitalg:1;
 390       unsigned int cpuavx512_bf16:1;
 391       unsigned int cpuavx512_vp2intersect:1;
 392       unsigned int cputdx:1;
 393       unsigned int cpuavx_vnni:1;
 394       unsigned int cpumwaitx:1;
 395       unsigned int cpuclzero:1;
 396       unsigned int cpuospke:1;
 397       unsigned int cpurdpid:1;
 398       unsigned int cpuptwrite:1;
 399       unsigned int cpuibt:1;
 400       unsigned int cpushstk:1;
 401       unsigned int cpuamx_int8:1;
 402       unsigned int cpuamx_bf16:1;
 403       unsigned int cpuamx_tile:1;
 404       unsigned int cpugfni:1;
 405       unsigned int cpuvaes:1;
 406       unsigned int cpuvpclmulqdq:1;
 407       unsigned int cpuwbnoinvd:1;
 408       unsigned int cpupconfig:1;
 409       unsigned int cpuwaitpkg:1;
 410       unsigned int cpuuintr:1;
 411       unsigned int cpucldemote:1;
 412       unsigned int cpumovdiri:1;
 413       unsigned int cpumovdir64b:1;
 414       unsigned int cpuenqcmd:1;
 415       unsigned int cpuserialize:1;
 416       unsigned int cpurdpru:1;
 417       unsigned int cpumcommit:1;
 418       unsigned int cpusev_es:1;
 419       unsigned int cputsxldtrk:1;
 420       unsigned int cpukl:1;
 421       unsigned int cpuwidekl:1;
 422       unsigned int cpuhreset:1;
 423       unsigned int cpuinvlpgb:1;
 424       unsigned int cputlbsync:1;
 425       unsigned int cpusnp:1;
 426       unsigned int cpu64:1;
 427       unsigned int cpuno64:1;
 428 #ifdef CpuUnused
 429       unsigned int unused:(CpuNumOfBits - CpuUnused);
 430 #endif
 431     } bitfield;
 432   unsigned int array[CpuNumOfUints];
 433 } i386_cpu_flags;
 434
 435 /* Position of opcode_modifier bits.  */
 436
 437 enum
 438 {
 439   /* has direction bit. */
 440   D = 0,
 441   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 442      canonical way; the base_opcode field should hold the encoding for byte
 443      operands  */
 444   W,
 445   /* load form instruction. Must be placed before store form.  */
 446   Load,
 447   /* insn has a modrm byte. */
 448   Modrm,
 449   /* special case for jump insns; value has to be 1 */
 450 #define JUMP 1
 451   /* call and jump */
 452 #define JUMP_DWORD 2
 453   /* loop and jecxz */
 454 #define JUMP_BYTE 3
 455   /* special case for intersegment leaps/calls */
 456 #define JUMP_INTERSEGMENT 4
 457   /* absolute address for jump */
 458 #define JUMP_ABSOLUTE 5
 459   Jump,
 460   /* FP insn memory format bit, sized by 0x4 */
 461   FloatMF,
 462   /* src/dest swap for floats. */
 463   FloatR,
 464   /* needs size prefix if in 32-bit mode */
 465 #define SIZE16 1
 466   /* needs size prefix if in 16-bit mode */
 467 #define SIZE32 2
 468   /* needs size prefix if in 64-bit mode */
 469 #define SIZE64 3
 470   Size,
 471   /* check register size.  */
 472   CheckRegSize,
 473   /* instruction ignores operand size prefix and in Intel mode ignores
 474      mnemonic size suffix check.  */
 475 #define IGNORESIZE      1
 476   /* default insn size depends on mode */
 477 #define DEFAULTSIZE     2
 478   MnemonicSize,
 479   /* any memory size */
 480   Anysize,
 481   /* b suffix on instruction illegal */
 482   No_bSuf,
 483   /* w suffix on instruction illegal */
 484   No_wSuf,
 485   /* l suffix on instruction illegal */
 486   No_lSuf,
 487   /* s suffix on instruction illegal */
 488   No_sSuf,
 489   /* q suffix on instruction illegal */
 490   No_qSuf,
 491   /* long double suffix on instruction illegal */
 492   No_ldSuf,
 493   /* instruction needs FWAIT */
 494   FWait,
 495   /* IsString provides for a quick test for string instructions, and
 496      its actual value also indicates which of the operands (if any)
 497      requires use of the %es segment.  */
 498 #define IS_STRING_ES_OP0 2
 499 #define IS_STRING_ES_OP1 3
 500   IsString,
 501   /* RegMem is for instructions with a modrm byte where the register
 502      destination operand should be encoded in the mod and regmem fields.
 503      Normally, it will be encoded in the reg field. We add a RegMem
 504      flag to indicate that it should be encoded in the regmem field.  */
 505   RegMem,
 506   /* quick test if branch instruction is MPX supported */
 507   BNDPrefixOk,
 508   /* quick test if NOTRACK prefix is supported */
 509   NoTrackPrefixOk,
 510   /* quick test for lockable instructions */
 511   IsLockable,
 512   /* fake an extra reg operand for clr, imul and special register
 513      processing for some instructions.  */
 514   RegKludge,
 515   /* An implicit xmm0 as the first operand */
 516   Implicit1stXmm0,
 517   /* The HLE prefix is OK:
 518      1. With a LOCK prefix.
 519      2. With or without a LOCK prefix.
 520      3. With a RELEASE (0xf3) prefix.
 521    */
 522 #define HLEPrefixNone           0
 523 #define HLEPrefixLock           1
 524 #define HLEPrefixAny            2
 525 #define HLEPrefixRelease        3
 526   HLEPrefixOk,
 527   /* An instruction on which a "rep" prefix is acceptable.  */
 528   RepPrefixOk,
 529   /* Convert to DWORD */
 530   ToDword,
 531   /* Convert to QWORD */
 532   ToQword,
 533   /* Address prefix changes register operand */
 534   AddrPrefixOpReg,
 535   /* opcode is a prefix */
 536   IsPrefix,
 537   /* instruction has extension in 8 bit imm */
 538   ImmExt,
 539   /* instruction don't need Rex64 prefix.  */
 540   NoRex64,
 541   /* deprecated fp insn, gets a warning */
 542   Ugh,
 543   /* Intel AVX Instructions support via {vex} prefix */
 544   PseudoVexPrefix,
 545   /* insn has VEX prefix:
 546         1: 128bit VEX prefix (or operand dependent).
 547         2: 256bit VEX prefix.
 548         3: Scalar VEX prefix.
 549    */
 550 #define VEX128          1
 551 #define VEX256          2
 552 #define VEXScalar       3
 553   Vex,
 554   /* How to encode VEX.vvvv:
 555      0: VEX.vvvv must be 1111b.
 556      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 557         the content of source registers will be preserved.
 558         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 559         where the content of first source register will be overwritten
 560         by the result.
 561         VEX.NDD2.  The second destination register operand is encoded in
 562         VEX.vvvv for instructions with 2 destination register operands.
 563         For assembler, there are no difference between VEX.NDS, VEX.DDS
 564         and VEX.NDD2.
 565      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 566      instructions with 1 destination register operand.
 567      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 568         of the operands can access a memory location.
 569    */
 570 #define VEXXDS  1
 571 #define VEXNDD  2
 572 #define VEXLWP  3
 573   VexVVVV,
 574   /* How the VEX.W bit is used:
 575      0: Set by the REX.W bit.
 576      1: VEX.W0.  Should always be 0.
 577      2: VEX.W1.  Should always be 1.
 578      3: VEX.WIG. The VEX.W bit is ignored.
 579    */
 580 #define VEXW0   1
 581 #define VEXW1   2
 582 #define VEXWIG  3
 583   VexW,
 584   /* Regular opcode prefix:
 585      0: None
 586      1: Add 0x66 opcode prefix.
 587      2: Add 0xf2 opcode prefix.
 588      3: Add 0xf3 opcode prefix.
 589    */
 590 #define PREFIX_NONE     0
 591 #define PREFIX_0X66     1
 592 #define PREFIX_0XF2     2
 593 #define PREFIX_0XF3     3
 594   /* VEX opcode prefix:
 595      0: VEX 0x0F opcode prefix.
 596      1: VEX 0x0F38 opcode prefix.
 597      2: VEX 0x0F3A opcode prefix
 598      3: XOP 0x08 opcode prefix.
 599      4: XOP 0x09 opcode prefix
 600      5: XOP 0x0A opcode prefix.
 601    */
 602 #define VEX0F           0
 603 #define VEX0F38         1
 604 #define VEX0F3A         2
 605 #define XOP08           3
 606 #define XOP09           4
 607 #define XOP0A           5
 608   OpcodePrefix,
 609   /* number of VEX source operands:
 610      0: <= 2 source operands.
 611      1: 2 XOP source operands.
 612      2: 3 source operands.
 613    */
 614 #define XOP2SOURCES     1
 615 #define VEX3SOURCES     2
 616   VexSources,
 617   /* Instruction with a mandatory SIB byte:
 618         1: 128bit vector register.
 619         2: 256bit vector register.
 620         3: 512bit vector register.
 621    */
 622 #define VECSIB128       1
 623 #define VECSIB256       2
 624 #define VECSIB512       3
 625 #define SIBMEM          4
 626   SIB,
 627
 628   /* SSE to AVX support required */
 629   SSE2AVX,
 630   /* No AVX equivalent */
 631   NoAVX,
 632
 633   /* insn has EVEX prefix:
 634         1: 512bit EVEX prefix.
 635         2: 128bit EVEX prefix.
 636         3: 256bit EVEX prefix.
 637         4: Length-ignored (LIG) EVEX prefix.
 638         5: Length determined from actual operands.
 639    */
 640 #define EVEX512                1
 641 #define EVEX128                2
 642 #define EVEX256                3
 643 #define EVEXLIG                4
 644 #define EVEXDYN                5
 645   EVex,
 646
 647   /* AVX512 masking support:
 648         1: Zeroing or merging masking depending on operands.
 649         2: Merging-masking.
 650         3: Both zeroing and merging masking.
 651    */
 652 #define DYNAMIC_MASKING 1
 653 #define MERGING_MASKING 2
 654 #define BOTH_MASKING    3
 655   Masking,
 656
 657   /* AVX512 broadcast support.  The number of bytes to broadcast is
 658      1 << (Broadcast - 1):
 659         1: Byte broadcast.
 660         2: Word broadcast.
 661         3: Dword broadcast.
 662         4: Qword broadcast.
 663    */
 664 #define BYTE_BROADCAST  1
 665 #define WORD_BROADCAST  2
 666 #define DWORD_BROADCAST 3
 667 #define QWORD_BROADCAST 4
 668   Broadcast,
 669
 670   /* Static rounding control is supported.  */
 671   StaticRounding,
 672
 673   /* Supress All Exceptions is supported.  */
 674   SAE,
 675
 676   /* Compressed Disp8*N attribute.  */
 677 #define DISP8_SHIFT_VL 7
 678   Disp8MemShift,
 679
 680   /* Default mask isn't allowed.  */
 681   NoDefMask,
 682
 683   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 684      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 685    */
 686   ImplicitQuadGroup,
 687
 688   /* Two source operands are swapped.  */
 689   SwapSources,
 690
 691   /* Support encoding optimization.  */
 692   Optimize,
 693
 694   /* AT&T mnemonic.  */
 695   ATTMnemonic,
 696   /* AT&T syntax.  */
 697   ATTSyntax,
 698   /* Intel syntax.  */
 699   IntelSyntax,
 700   /* ISA64: Don't change the order without other code adjustments.
 701         0: Common to AMD64 and Intel64.
 702         1: AMD64.
 703         2: Intel64.
 704         3: Only in Intel64.
 705    */
 706 #define AMD64           1
 707 #define INTEL64         2
 708 #define INTEL64ONLY     3
 709   ISA64,
 710   /* The last bitfield in i386_opcode_modifier.  */
 711   Opcode_Modifier_Num
 712 };
 713
 714 typedef struct i386_opcode_modifier
 715 {
 716   unsigned int d:1;
 717   unsigned int w:1;
 718   unsigned int load:1;
 719   unsigned int modrm:1;
 720   unsigned int jump:3;
 721   unsigned int floatmf:1;
 722   unsigned int floatr:1;
 723   unsigned int size:2;
 724   unsigned int checkregsize:1;
 725   unsigned int mnemonicsize:2;
 726   unsigned int anysize:1;
 727   unsigned int no_bsuf:1;
 728   unsigned int no_wsuf:1;
 729   unsigned int no_lsuf:1;
 730   unsigned int no_ssuf:1;
 731   unsigned int no_qsuf:1;
 732   unsigned int no_ldsuf:1;
 733   unsigned int fwait:1;
 734   unsigned int isstring:2;
 735   unsigned int regmem:1;
 736   unsigned int bndprefixok:1;
 737   unsigned int notrackprefixok:1;
 738   unsigned int islockable:1;
 739   unsigned int regkludge:1;
 740   unsigned int implicit1stxmm0:1;
 741   unsigned int hleprefixok:2;
 742   unsigned int repprefixok:1;
 743   unsigned int todword:1;
 744   unsigned int toqword:1;
 745   unsigned int addrprefixopreg:1;
 746   unsigned int isprefix:1;
 747   unsigned int immext:1;
 748   unsigned int norex64:1;
 749   unsigned int ugh:1;
 750   unsigned int pseudovexprefix:1;
 751   unsigned int vex:2;
 752   unsigned int vexvvvv:2;
 753   unsigned int vexw:2;
 754   unsigned int opcodeprefix:3;
 755   unsigned int vexsources:2;
 756   unsigned int sib:3;
 757   unsigned int sse2avx:1;
 758   unsigned int noavx:1;
 759   unsigned int evex:3;
 760   unsigned int masking:2;
 761   unsigned int broadcast:3;
 762   unsigned int staticrounding:1;
 763   unsigned int sae:1;
 764   unsigned int disp8memshift:3;
 765   unsigned int nodefmask:1;
 766   unsigned int implicitquadgroup:1;
 767   unsigned int swapsources:1;
 768   unsigned int optimize:1;
 769   unsigned int attmnemonic:1;
 770   unsigned int attsyntax:1;
 771   unsigned int intelsyntax:1;
 772   unsigned int isa64:2;
 773 } i386_opcode_modifier;
 774
 775 /* Operand classes.  */
 776
 777 #define CLASS_WIDTH 4
 778 enum operand_class
 779 {
 780   ClassNone,
 781   Reg, /* GPRs and FP regs, distinguished by operand size */
 782   SReg, /* Segment register */
 783   RegCR, /* Control register */
 784   RegDR, /* Debug register */
 785   RegTR, /* Test register */
 786   RegMMX, /* MMX register */
 787   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 788   RegMask, /* Vector Mask register */
 789   RegBND, /* Bound register */
 790 };
 791
 792 /* Special operand instances.  */
 793
 794 #define INSTANCE_WIDTH 3
 795 enum operand_instance
 796 {
 797   InstanceNone,
 798   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 799   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 800   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 801   RegB,  /* %bl / %bx / %ebx / %rbx */
 802 };
 803
 804 /* Position of operand_type bits.  */
 805
 806 enum
 807 {
 808   /* Class and Instance */
 809   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 810   /* 1 bit immediate */
 811   Imm1,
 812   /* 8 bit immediate */
 813   Imm8,
 814   /* 8 bit immediate sign extended */
 815   Imm8S,
 816   /* 16 bit immediate */
 817   Imm16,
 818   /* 32 bit immediate */
 819   Imm32,
 820   /* 32 bit immediate sign extended */
 821   Imm32S,
 822   /* 64 bit immediate */
 823   Imm64,
 824   /* 8bit/16bit/32bit displacements are used in different ways,
 825      depending on the instruction.  For jumps, they specify the
 826      size of the PC relative displacement, for instructions with
 827      memory operand, they specify the size of the offset relative
 828      to the base register, and for instructions with memory offset
 829      such as `mov 1234,%al' they specify the size of the offset
 830      relative to the segment base.  */
 831   /* 8 bit displacement */
 832   Disp8,
 833   /* 16 bit displacement */
 834   Disp16,
 835   /* 32 bit displacement */
 836   Disp32,
 837   /* 32 bit signed displacement */
 838   Disp32S,
 839   /* 64 bit displacement */
 840   Disp64,
 841   /* Register which can be used for base or index in memory operand.  */
 842   BaseIndex,
 843   /* BYTE size. */
 844   Byte,
 845   /* WORD size. 2 byte */
 846   Word,
 847   /* DWORD size. 4 byte */
 848   Dword,
 849   /* FWORD size. 6 byte */
 850   Fword,
 851   /* QWORD size. 8 byte */
 852   Qword,
 853   /* TBYTE size. 10 byte */
 854   Tbyte,
 855   /* XMMWORD size. */
 856   Xmmword,
 857   /* YMMWORD size. */
 858   Ymmword,
 859   /* ZMMWORD size.  */
 860   Zmmword,
 861   /* TMMWORD size.  */
 862   Tmmword,
 863   /* Unspecified memory size.  */
 864   Unspecified,
 865
 866   /* The number of bits in i386_operand_type.  */
 867   OTNum
 868 };
 869
 870 #define OTNumOfUints \
 871   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 872 #define OTNumOfBits \
 873   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 874
 875 /* If you get a compiler error for zero width of the unused field,
 876    comment it out.  */
 877 #define OTUnused                OTNum
 878
 879 typedef union i386_operand_type
 880 {
 881   struct
 882     {
 883       unsigned int class:CLASS_WIDTH;
 884       unsigned int instance:INSTANCE_WIDTH;
 885       unsigned int imm1:1;
 886       unsigned int imm8:1;
 887       unsigned int imm8s:1;
 888       unsigned int imm16:1;
 889       unsigned int imm32:1;
 890       unsigned int imm32s:1;
 891       unsigned int imm64:1;
 892       unsigned int disp8:1;
 893       unsigned int disp16:1;
 894       unsigned int disp32:1;
 895       unsigned int disp32s:1;
 896       unsigned int disp64:1;
 897       unsigned int baseindex:1;
 898       unsigned int byte:1;
 899       unsigned int word:1;
 900       unsigned int dword:1;
 901       unsigned int fword:1;
 902       unsigned int qword:1;
 903       unsigned int tbyte:1;
 904       unsigned int xmmword:1;
 905       unsigned int ymmword:1;
 906       unsigned int zmmword:1;
 907       unsigned int tmmword:1;
 908       unsigned int unspecified:1;
 909 #ifdef OTUnused
 910       unsigned int unused:(OTNumOfBits - OTUnused);
 911 #endif
 912     } bitfield;
 913   unsigned int array[OTNumOfUints];
 914 } i386_operand_type;
 915
 916 typedef struct insn_template
 917 {
 918   /* instruction name sans width suffix ("mov" for movl insns) */
 919   char *name;
 920
 921   /* base_opcode is the fundamental opcode byte without optional
 922      prefix(es).  */
 923   unsigned int base_opcode;
 924 #define Opcode_D        0x2 /* Direction bit:
 925                                set if Reg --> Regmem;
 926                                unset if Regmem --> Reg. */
 927 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 928 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 929 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 930 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 931
 932 /* Pseudo prefixes.  */
 933 #define Prefix_Disp8            0       /* {disp8} */
 934 #define Prefix_Disp16           1       /* {disp16} */
 935 #define Prefix_Disp32           2       /* {disp32} */
 936 #define Prefix_Load             3       /* {load} */
 937 #define Prefix_Store            4       /* {store} */
 938 #define Prefix_VEX              5       /* {vex} */
 939 #define Prefix_VEX3             6       /* {vex3} */
 940 #define Prefix_EVEX             7       /* {evex} */
 941 #define Prefix_REX              8       /* {rex} */
 942 #define Prefix_NoOptimize       9       /* {nooptimize} */
 943
 944   /* extension_opcode is the 3 bit extension for group <n> insns.
 945      This field is also used to store the 8-bit opcode suffix for the
 946      AMD 3DNow! instructions.
 947      If this template has no extension opcode (the usual case) use None
 948      Instructions */
 949   unsigned short extension_opcode;
 950 #define None 0xffff             /* If no extension_opcode is possible.  */
 951
 952   /* Opcode length.  */
 953   unsigned char opcode_length;
 954
 955   /* how many operands */
 956   unsigned char operands;
 957
 958   /* cpu feature flags */
 959   i386_cpu_flags cpu_flags;
 960
 961   /* the bits in opcode_modifier are used to generate the final opcode from
 962      the base_opcode.  These bits also are used to detect alternate forms of
 963      the same instruction */
 964   i386_opcode_modifier opcode_modifier;
 965
 966   /* operand_types[i] describes the type of operand i.  This is made
 967      by OR'ing together all of the possible type masks.  (e.g.
 968      'operand_types[i] = Reg|Imm' specifies that operand i can be
 969      either a register or an immediate operand.  */
 970   i386_operand_type operand_types[MAX_OPERANDS];
 971 }
 972 insn_template;
 973
 974 extern const insn_template i386_optab[];
 975
 976 /* these are for register name --> number & type hash lookup */
 977 typedef struct
 978 {
 979   const char *reg_name;
 980   i386_operand_type reg_type;
 981   unsigned char reg_flags;
 982 #define RegRex      0x1  /* Extended register.  */
 983 #define RegRex64    0x2  /* Extended 8 bit register.  */
 984 #define RegVRex     0x4  /* Extended vector register.  */
 985   unsigned char reg_num;
 986 #define RegIP   ((unsigned char ) ~0)
 987 /* EIZ and RIZ are fake index registers.  */
 988 #define RegIZ   (RegIP - 1)
 989 /* FLAT is a fake segment register (Intel mode).  */
 990 #define RegFlat     ((unsigned char) ~0)
 991   signed char dw2_regnum[2];
 992 #define Dw2Inval (-1)
 993 }
 994 reg_entry;
 995
 996 /* Entries in i386_regtab.  */
 997 #define REGNAM_AL 1
 998 #define REGNAM_AX 25
 999 #define REGNAM_EAX 41
1000
1001 extern const reg_entry i386_regtab[];
1002 extern const unsigned int i386_regtab_size;
1003
1004 typedef struct
1005 {
1006   char *seg_name;
1007   unsigned int seg_prefix;
1008 }
1009 seg_entry;
1010
1011 extern const seg_entry cs;
1012 extern const seg_entry ds;
1013 extern const seg_entry ss;
1014 extern const seg_entry es;
1015 extern const seg_entry fs;
1016 extern const seg_entry gs;