opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CMOV Instruction support required */
  47   CpuCMOV,
  48   /* FXSR Instruction support required */
  49   CpuFXSR,
  50   /* CLFLUSH Instruction support required */
  51   CpuClflush,
  52   /* NOP Instruction support required */
  53   CpuNop,
  54   /* SYSCALL Instructions support required */
  55   CpuSYSCALL,
  56   /* Floating point support required */
  57   Cpu8087,
  58   /* i287 support required */
  59   Cpu287,
  60   /* i387 support required */
  61   Cpu387,
  62   /* i686 and floating point support required */
  63   Cpu687,
  64   /* SSE3 and floating point support required */
  65   CpuFISTTP,
  66   /* MMX support required */
  67   CpuMMX,
  68   /* SSE support required */
  69   CpuSSE,
  70   /* SSE2 support required */
  71   CpuSSE2,
  72   /* 3dnow! support required */
  73   Cpu3dnow,
  74   /* 3dnow! Extensions support required */
  75   Cpu3dnowA,
  76   /* SSE3 support required */
  77   CpuSSE3,
  78   /* VIA PadLock required */
  79   CpuPadLock,
  80   /* AMD Secure Virtual Machine Ext-s required */
  81   CpuSVME,
  82   /* VMX Instructions required */
  83   CpuVMX,
  84   /* SMX Instructions required */
  85   CpuSMX,
  86   /* SSSE3 support required */
  87   CpuSSSE3,
  88   /* SSE4a support required */
  89   CpuSSE4a,
  90   /* LZCNT support required */
  91   CpuLZCNT,
  92   /* POPCNT support required */
  93   CpuPOPCNT,
  94   /* SSE4.1 support required */
  95   CpuSSE4_1,
  96   /* SSE4.2 support required */
  97   CpuSSE4_2,
  98   /* AVX support required */
  99   CpuAVX,
 100   /* AVX2 support required */
 101   CpuAVX2,
 102   /* Intel AVX-512 Foundation Instructions support required */
 103   CpuAVX512F,
 104   /* Intel AVX-512 Conflict Detection Instructions support required */
 105   CpuAVX512CD,
 106   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 107      required */
 108   CpuAVX512ER,
 109   /* Intel AVX-512 Prefetch Instructions support required */
 110   CpuAVX512PF,
 111   /* Intel AVX-512 VL Instructions support required.  */
 112   CpuAVX512VL,
 113   /* Intel AVX-512 DQ Instructions support required.  */
 114   CpuAVX512DQ,
 115   /* Intel AVX-512 BW Instructions support required.  */
 116   CpuAVX512BW,
 117   /* Intel L1OM support required */
 118   CpuL1OM,
 119   /* Intel K1OM support required */
 120   CpuK1OM,
 121   /* Intel IAMCU support required */
 122   CpuIAMCU,
 123   /* Xsave/xrstor New Instructions support required */
 124   CpuXsave,
 125   /* Xsaveopt New Instructions support required */
 126   CpuXsaveopt,
 127   /* AES support required */
 128   CpuAES,
 129   /* PCLMUL support required */
 130   CpuPCLMUL,
 131   /* FMA support required */
 132   CpuFMA,
 133   /* FMA4 support required */
 134   CpuFMA4,
 135   /* XOP support required */
 136   CpuXOP,
 137   /* LWP support required */
 138   CpuLWP,
 139   /* BMI support required */
 140   CpuBMI,
 141   /* TBM support required */
 142   CpuTBM,
 143   /* MOVBE Instruction support required */
 144   CpuMovbe,
 145   /* CMPXCHG16B instruction support required.  */
 146   CpuCX16,
 147   /* EPT Instructions required */
 148   CpuEPT,
 149   /* RDTSCP Instruction support required */
 150   CpuRdtscp,
 151   /* FSGSBASE Instructions required */
 152   CpuFSGSBase,
 153   /* RDRND Instructions required */
 154   CpuRdRnd,
 155   /* F16C Instructions required */
 156   CpuF16C,
 157   /* Intel BMI2 support required */
 158   CpuBMI2,
 159   /* HLE support required */
 160   CpuHLE,
 161   /* RTM support required */
 162   CpuRTM,
 163   /* INVPCID Instructions required */
 164   CpuINVPCID,
 165   /* VMFUNC Instruction required */
 166   CpuVMFUNC,
 167   /* Intel MPX Instructions required  */
 168   CpuMPX,
 169   /* 64bit support available, used by -march= in assembler.  */
 170   CpuLM,
 171   /* RDRSEED instruction required.  */
 172   CpuRDSEED,
 173   /* Multi-presisionn add-carry instructions are required.  */
 174   CpuADX,
 175   /* Supports prefetchw and prefetch instructions.  */
 176   CpuPRFCHW,
 177   /* SMAP instructions required.  */
 178   CpuSMAP,
 179   /* SHA instructions required.  */
 180   CpuSHA,
 181   /* CLFLUSHOPT instruction required */
 182   CpuClflushOpt,
 183   /* XSAVES/XRSTORS instruction required */
 184   CpuXSAVES,
 185   /* XSAVEC instruction required */
 186   CpuXSAVEC,
 187   /* PREFETCHWT1 instruction required */
 188   CpuPREFETCHWT1,
 189   /* SE1 instruction required */
 190   CpuSE1,
 191   /* CLWB instruction required */
 192   CpuCLWB,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* Intel AVX-512 4FMAPS Instructions support required.  */
 198   CpuAVX512_4FMAPS,
 199   /* Intel AVX-512 4VNNIW Instructions support required.  */
 200   CpuAVX512_4VNNIW,
 201   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 202   CpuAVX512_VPOPCNTDQ,
 203   /* Intel AVX-512 VBMI2 Instructions support required.  */
 204   CpuAVX512_VBMI2,
 205   /* Intel AVX-512 VNNI Instructions support required.  */
 206   CpuAVX512_VNNI,
 207   /* Intel AVX-512 BITALG Instructions support required.  */
 208   CpuAVX512_BITALG,
 209   /* Intel AVX-512 BF16 Instructions support required.  */
 210   CpuAVX512_BF16,
 211   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 212   CpuAVX512_VP2INTERSECT,
 213   /* mwaitx instruction required */
 214   CpuMWAITX,
 215   /* Clzero instruction required */
 216   CpuCLZERO,
 217   /* OSPKE instruction required */
 218   CpuOSPKE,
 219   /* RDPID instruction required */
 220   CpuRDPID,
 221   /* PTWRITE instruction required */
 222   CpuPTWRITE,
 223   /* CET instructions support required */
 224   CpuIBT,
 225   CpuSHSTK,
 226   /* GFNI instructions required */
 227   CpuGFNI,
 228   /* VAES instructions required */
 229   CpuVAES,
 230   /* VPCLMULQDQ instructions required */
 231   CpuVPCLMULQDQ,
 232   /* WBNOINVD instructions required */
 233   CpuWBNOINVD,
 234   /* PCONFIG instructions required */
 235   CpuPCONFIG,
 236   /* WAITPKG instructions required */
 237   CpuWAITPKG,
 238   /* CLDEMOTE instruction required */
 239   CpuCLDEMOTE,
 240   /* MOVDIRI instruction support required */
 241   CpuMOVDIRI,
 242   /* MOVDIRR64B instruction required */
 243   CpuMOVDIR64B,
 244   /* ENQCMD instruction required */
 245   CpuENQCMD,
 246   /* SERIALIZE instruction required */
 247   CpuSERIALIZE,
 248   /* RDPRU instruction required */
 249   CpuRDPRU,
 250   /* MCOMMIT instruction required */
 251   CpuMCOMMIT,
 252   /* SEV-ES instruction(s) required */
 253   CpuSEV_ES,
 254   /* TSXLDTRK instruction required */
 255   CpuTSXLDTRK,
 256   /* 64bit support required  */
 257   Cpu64,
 258   /* Not supported in the 64bit mode  */
 259   CpuNo64,
 260   /* The last bitfield in i386_cpu_flags.  */
 261   CpuMax = CpuNo64
 262 };
 263
 264 #define CpuNumOfUints \
 265   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 266 #define CpuNumOfBits \
 267   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 268
 269 /* If you get a compiler error for zero width of the unused field,
 270    comment it out.  */
 271 #define CpuUnused       (CpuMax + 1)
 272
 273 /* We can check if an instruction is available with array instead
 274    of bitfield. */
 275 typedef union i386_cpu_flags
 276 {
 277   struct
 278     {
 279       unsigned int cpui186:1;
 280       unsigned int cpui286:1;
 281       unsigned int cpui386:1;
 282       unsigned int cpui486:1;
 283       unsigned int cpui586:1;
 284       unsigned int cpui686:1;
 285       unsigned int cpucmov:1;
 286       unsigned int cpufxsr:1;
 287       unsigned int cpuclflush:1;
 288       unsigned int cpunop:1;
 289       unsigned int cpusyscall:1;
 290       unsigned int cpu8087:1;
 291       unsigned int cpu287:1;
 292       unsigned int cpu387:1;
 293       unsigned int cpu687:1;
 294       unsigned int cpufisttp:1;
 295       unsigned int cpummx:1;
 296       unsigned int cpusse:1;
 297       unsigned int cpusse2:1;
 298       unsigned int cpua3dnow:1;
 299       unsigned int cpua3dnowa:1;
 300       unsigned int cpusse3:1;
 301       unsigned int cpupadlock:1;
 302       unsigned int cpusvme:1;
 303       unsigned int cpuvmx:1;
 304       unsigned int cpusmx:1;
 305       unsigned int cpussse3:1;
 306       unsigned int cpusse4a:1;
 307       unsigned int cpulzcnt:1;
 308       unsigned int cpupopcnt:1;
 309       unsigned int cpusse4_1:1;
 310       unsigned int cpusse4_2:1;
 311       unsigned int cpuavx:1;
 312       unsigned int cpuavx2:1;
 313       unsigned int cpuavx512f:1;
 314       unsigned int cpuavx512cd:1;
 315       unsigned int cpuavx512er:1;
 316       unsigned int cpuavx512pf:1;
 317       unsigned int cpuavx512vl:1;
 318       unsigned int cpuavx512dq:1;
 319       unsigned int cpuavx512bw:1;
 320       unsigned int cpul1om:1;
 321       unsigned int cpuk1om:1;
 322       unsigned int cpuiamcu:1;
 323       unsigned int cpuxsave:1;
 324       unsigned int cpuxsaveopt:1;
 325       unsigned int cpuaes:1;
 326       unsigned int cpupclmul:1;
 327       unsigned int cpufma:1;
 328       unsigned int cpufma4:1;
 329       unsigned int cpuxop:1;
 330       unsigned int cpulwp:1;
 331       unsigned int cpubmi:1;
 332       unsigned int cputbm:1;
 333       unsigned int cpumovbe:1;
 334       unsigned int cpucx16:1;
 335       unsigned int cpuept:1;
 336       unsigned int cpurdtscp:1;
 337       unsigned int cpufsgsbase:1;
 338       unsigned int cpurdrnd:1;
 339       unsigned int cpuf16c:1;
 340       unsigned int cpubmi2:1;
 341       unsigned int cpuhle:1;
 342       unsigned int cpurtm:1;
 343       unsigned int cpuinvpcid:1;
 344       unsigned int cpuvmfunc:1;
 345       unsigned int cpumpx:1;
 346       unsigned int cpulm:1;
 347       unsigned int cpurdseed:1;
 348       unsigned int cpuadx:1;
 349       unsigned int cpuprfchw:1;
 350       unsigned int cpusmap:1;
 351       unsigned int cpusha:1;
 352       unsigned int cpuclflushopt:1;
 353       unsigned int cpuxsaves:1;
 354       unsigned int cpuxsavec:1;
 355       unsigned int cpuprefetchwt1:1;
 356       unsigned int cpuse1:1;
 357       unsigned int cpuclwb:1;
 358       unsigned int cpuavx512ifma:1;
 359       unsigned int cpuavx512vbmi:1;
 360       unsigned int cpuavx512_4fmaps:1;
 361       unsigned int cpuavx512_4vnniw:1;
 362       unsigned int cpuavx512_vpopcntdq:1;
 363       unsigned int cpuavx512_vbmi2:1;
 364       unsigned int cpuavx512_vnni:1;
 365       unsigned int cpuavx512_bitalg:1;
 366       unsigned int cpuavx512_bf16:1;
 367       unsigned int cpuavx512_vp2intersect:1;
 368       unsigned int cpumwaitx:1;
 369       unsigned int cpuclzero:1;
 370       unsigned int cpuospke:1;
 371       unsigned int cpurdpid:1;
 372       unsigned int cpuptwrite:1;
 373       unsigned int cpuibt:1;
 374       unsigned int cpushstk:1;
 375       unsigned int cpugfni:1;
 376       unsigned int cpuvaes:1;
 377       unsigned int cpuvpclmulqdq:1;
 378       unsigned int cpuwbnoinvd:1;
 379       unsigned int cpupconfig:1;
 380       unsigned int cpuwaitpkg:1;
 381       unsigned int cpucldemote:1;
 382       unsigned int cpumovdiri:1;
 383       unsigned int cpumovdir64b:1;
 384       unsigned int cpuenqcmd:1;
 385       unsigned int cpuserialize:1;
 386       unsigned int cpurdpru:1;
 387       unsigned int cpumcommit:1;
 388       unsigned int cpusev_es:1;
 389       unsigned int cputsxldtrk:1;
 390       unsigned int cpu64:1;
 391       unsigned int cpuno64:1;
 392 #ifdef CpuUnused
 393       unsigned int unused:(CpuNumOfBits - CpuUnused);
 394 #endif
 395     } bitfield;
 396   unsigned int array[CpuNumOfUints];
 397 } i386_cpu_flags;
 398
 399 /* Position of opcode_modifier bits.  */
 400
 401 enum
 402 {
 403   /* has direction bit. */
 404   D = 0,
 405   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 406      canonical way; the base_opcode field should hold the encoding for byte
 407      operands  */
 408   W,
 409   /* load form instruction. Must be placed before store form.  */
 410   Load,
 411   /* insn has a modrm byte. */
 412   Modrm,
 413   /* special case for jump insns; value has to be 1 */
 414 #define JUMP 1
 415   /* call and jump */
 416 #define JUMP_DWORD 2
 417   /* loop and jecxz */
 418 #define JUMP_BYTE 3
 419   /* special case for intersegment leaps/calls */
 420 #define JUMP_INTERSEGMENT 4
 421   /* absolute address for jump */
 422 #define JUMP_ABSOLUTE 5
 423   Jump,
 424   /* FP insn memory format bit, sized by 0x4 */
 425   FloatMF,
 426   /* src/dest swap for floats. */
 427   FloatR,
 428   /* needs size prefix if in 32-bit mode */
 429 #define SIZE16 1
 430   /* needs size prefix if in 16-bit mode */
 431 #define SIZE32 2
 432   /* needs size prefix if in 64-bit mode */
 433 #define SIZE64 3
 434   Size,
 435   /* check register size.  */
 436   CheckRegSize,
 437   /* instruction ignores operand size prefix and in Intel mode ignores
 438      mnemonic size suffix check.  */
 439 #define IGNORESIZE      1
 440   /* default insn size depends on mode */
 441 #define DEFAULTSIZE     2
 442   MnemonicSize,
 443   /* any memory size */
 444   Anysize,
 445   /* b suffix on instruction illegal */
 446   No_bSuf,
 447   /* w suffix on instruction illegal */
 448   No_wSuf,
 449   /* l suffix on instruction illegal */
 450   No_lSuf,
 451   /* s suffix on instruction illegal */
 452   No_sSuf,
 453   /* q suffix on instruction illegal */
 454   No_qSuf,
 455   /* long double suffix on instruction illegal */
 456   No_ldSuf,
 457   /* instruction needs FWAIT */
 458   FWait,
 459   /* IsString provides for a quick test for string instructions, and
 460      its actual value also indicates which of the operands (if any)
 461      requires use of the %es segment.  */
 462 #define IS_STRING_ES_OP0 2
 463 #define IS_STRING_ES_OP1 3
 464   IsString,
 465   /* RegMem is for instructions with a modrm byte where the register
 466      destination operand should be encoded in the mod and regmem fields.
 467      Normally, it will be encoded in the reg field. We add a RegMem
 468      flag to indicate that it should be encoded in the regmem field.  */
 469   RegMem,
 470   /* quick test if branch instruction is MPX supported */
 471   BNDPrefixOk,
 472   /* quick test if NOTRACK prefix is supported */
 473   NoTrackPrefixOk,
 474   /* quick test for lockable instructions */
 475   IsLockable,
 476   /* fake an extra reg operand for clr, imul and special register
 477      processing for some instructions.  */
 478   RegKludge,
 479   /* An implicit xmm0 as the first operand */
 480   Implicit1stXmm0,
 481   /* The HLE prefix is OK:
 482      1. With a LOCK prefix.
 483      2. With or without a LOCK prefix.
 484      3. With a RELEASE (0xf3) prefix.
 485    */
 486 #define HLEPrefixNone           0
 487 #define HLEPrefixLock           1
 488 #define HLEPrefixAny            2
 489 #define HLEPrefixRelease        3
 490   HLEPrefixOk,
 491   /* An instruction on which a "rep" prefix is acceptable.  */
 492   RepPrefixOk,
 493   /* Convert to DWORD */
 494   ToDword,
 495   /* Convert to QWORD */
 496   ToQword,
 497   /* Address prefix changes register operand */
 498   AddrPrefixOpReg,
 499   /* opcode is a prefix */
 500   IsPrefix,
 501   /* instruction has extension in 8 bit imm */
 502   ImmExt,
 503   /* instruction don't need Rex64 prefix.  */
 504   NoRex64,
 505   /* deprecated fp insn, gets a warning */
 506   Ugh,
 507   /* insn has VEX prefix:
 508         1: 128bit VEX prefix (or operand dependent).
 509         2: 256bit VEX prefix.
 510         3: Scalar VEX prefix.
 511    */
 512 #define VEX128          1
 513 #define VEX256          2
 514 #define VEXScalar       3
 515   Vex,
 516   /* How to encode VEX.vvvv:
 517      0: VEX.vvvv must be 1111b.
 518      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 519         the content of source registers will be preserved.
 520         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 521         where the content of first source register will be overwritten
 522         by the result.
 523         VEX.NDD2.  The second destination register operand is encoded in
 524         VEX.vvvv for instructions with 2 destination register operands.
 525         For assembler, there are no difference between VEX.NDS, VEX.DDS
 526         and VEX.NDD2.
 527      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 528      instructions with 1 destination register operand.
 529      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 530         of the operands can access a memory location.
 531    */
 532 #define VEXXDS  1
 533 #define VEXNDD  2
 534 #define VEXLWP  3
 535   VexVVVV,
 536   /* How the VEX.W bit is used:
 537      0: Set by the REX.W bit.
 538      1: VEX.W0.  Should always be 0.
 539      2: VEX.W1.  Should always be 1.
 540      3: VEX.WIG. The VEX.W bit is ignored.
 541    */
 542 #define VEXW0   1
 543 #define VEXW1   2
 544 #define VEXWIG  3
 545   VexW,
 546   /* VEX opcode prefix:
 547      0: VEX 0x0F opcode prefix.
 548      1: VEX 0x0F38 opcode prefix.
 549      2: VEX 0x0F3A opcode prefix
 550      3: XOP 0x08 opcode prefix.
 551      4: XOP 0x09 opcode prefix
 552      5: XOP 0x0A opcode prefix.
 553    */
 554 #define VEX0F           0
 555 #define VEX0F38         1
 556 #define VEX0F3A         2
 557 #define XOP08           3
 558 #define XOP09           4
 559 #define XOP0A           5
 560   VexOpcode,
 561   /* number of VEX source operands:
 562      0: <= 2 source operands.
 563      1: 2 XOP source operands.
 564      2: 3 source operands.
 565    */
 566 #define XOP2SOURCES     1
 567 #define VEX3SOURCES     2
 568   VexSources,
 569   /* Instruction with a mandatory SIB byte:
 570         1: 128bit vector register.
 571         2: 256bit vector register.
 572         3: 512bit vector register.
 573    */
 574 #define VECSIB128       1
 575 #define VECSIB256       2
 576 #define VECSIB512       3
 577   SIB,
 578   /* SSE to AVX support required */
 579   SSE2AVX,
 580   /* No AVX equivalent */
 581   NoAVX,
 582
 583   /* insn has EVEX prefix:
 584         1: 512bit EVEX prefix.
 585         2: 128bit EVEX prefix.
 586         3: 256bit EVEX prefix.
 587         4: Length-ignored (LIG) EVEX prefix.
 588         5: Length determined from actual operands.
 589    */
 590 #define EVEX512                1
 591 #define EVEX128                2
 592 #define EVEX256                3
 593 #define EVEXLIG                4
 594 #define EVEXDYN                5
 595   EVex,
 596
 597   /* AVX512 masking support:
 598         1: Zeroing or merging masking depending on operands.
 599         2: Merging-masking.
 600         3: Both zeroing and merging masking.
 601    */
 602 #define DYNAMIC_MASKING 1
 603 #define MERGING_MASKING 2
 604 #define BOTH_MASKING    3
 605   Masking,
 606
 607   /* AVX512 broadcast support.  The number of bytes to broadcast is
 608      1 << (Broadcast - 1):
 609         1: Byte broadcast.
 610         2: Word broadcast.
 611         3: Dword broadcast.
 612         4: Qword broadcast.
 613    */
 614 #define BYTE_BROADCAST  1
 615 #define WORD_BROADCAST  2
 616 #define DWORD_BROADCAST 3
 617 #define QWORD_BROADCAST 4
 618   Broadcast,
 619
 620   /* Static rounding control is supported.  */
 621   StaticRounding,
 622
 623   /* Supress All Exceptions is supported.  */
 624   SAE,
 625
 626   /* Compressed Disp8*N attribute.  */
 627 #define DISP8_SHIFT_VL 7
 628   Disp8MemShift,
 629
 630   /* Default mask isn't allowed.  */
 631   NoDefMask,
 632
 633   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 634      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 635    */
 636   ImplicitQuadGroup,
 637
 638   /* Two source operands are swapped.  */
 639   SwapSources,
 640
 641   /* Support encoding optimization.  */
 642   Optimize,
 643
 644   /* AT&T mnemonic.  */
 645   ATTMnemonic,
 646   /* AT&T syntax.  */
 647   ATTSyntax,
 648   /* Intel syntax.  */
 649   IntelSyntax,
 650   /* ISA64: Don't change the order without other code adjustments.
 651         0: Common to AMD64 and Intel64.
 652         1: AMD64.
 653         2: Intel64.
 654         3: Only in Intel64.
 655    */
 656 #define AMD64           1
 657 #define INTEL64         2
 658 #define INTEL64ONLY     3
 659   ISA64,
 660   /* The last bitfield in i386_opcode_modifier.  */
 661   Opcode_Modifier_Num
 662 };
 663
 664 typedef struct i386_opcode_modifier
 665 {
 666   unsigned int d:1;
 667   unsigned int w:1;
 668   unsigned int load:1;
 669   unsigned int modrm:1;
 670   unsigned int jump:3;
 671   unsigned int floatmf:1;
 672   unsigned int floatr:1;
 673   unsigned int size:2;
 674   unsigned int checkregsize:1;
 675   unsigned int mnemonicsize:2;
 676   unsigned int anysize:1;
 677   unsigned int no_bsuf:1;
 678   unsigned int no_wsuf:1;
 679   unsigned int no_lsuf:1;
 680   unsigned int no_ssuf:1;
 681   unsigned int no_qsuf:1;
 682   unsigned int no_ldsuf:1;
 683   unsigned int fwait:1;
 684   unsigned int isstring:2;
 685   unsigned int regmem:1;
 686   unsigned int bndprefixok:1;
 687   unsigned int notrackprefixok:1;
 688   unsigned int islockable:1;
 689   unsigned int regkludge:1;
 690   unsigned int implicit1stxmm0:1;
 691   unsigned int hleprefixok:2;
 692   unsigned int repprefixok:1;
 693   unsigned int todword:1;
 694   unsigned int toqword:1;
 695   unsigned int addrprefixopreg:1;
 696   unsigned int isprefix:1;
 697   unsigned int immext:1;
 698   unsigned int norex64:1;
 699   unsigned int ugh:1;
 700   unsigned int vex:2;
 701   unsigned int vexvvvv:2;
 702   unsigned int vexw:2;
 703   unsigned int vexopcode:3;
 704   unsigned int vexsources:2;
 705   unsigned int sib:2;
 706   unsigned int sse2avx:1;
 707   unsigned int noavx:1;
 708   unsigned int evex:3;
 709   unsigned int masking:2;
 710   unsigned int broadcast:3;
 711   unsigned int staticrounding:1;
 712   unsigned int sae:1;
 713   unsigned int disp8memshift:3;
 714   unsigned int nodefmask:1;
 715   unsigned int implicitquadgroup:1;
 716   unsigned int swapsources:1;
 717   unsigned int optimize:1;
 718   unsigned int attmnemonic:1;
 719   unsigned int attsyntax:1;
 720   unsigned int intelsyntax:1;
 721   unsigned int isa64:2;
 722 } i386_opcode_modifier;
 723
 724 /* Operand classes.  */
 725
 726 #define CLASS_WIDTH 4
 727 enum operand_class
 728 {
 729   ClassNone,
 730   Reg, /* GPRs and FP regs, distinguished by operand size */
 731   SReg, /* Segment register */
 732   RegCR, /* Control register */
 733   RegDR, /* Debug register */
 734   RegTR, /* Test register */
 735   RegMMX, /* MMX register */
 736   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 737   RegMask, /* Vector Mask register */
 738   RegBND, /* Bound register */
 739 };
 740
 741 /* Special operand instances.  */
 742
 743 #define INSTANCE_WIDTH 3
 744 enum operand_instance
 745 {
 746   InstanceNone,
 747   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 748   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 749   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 750   RegB,  /* %bl / %bx / %ebx / %rbx */
 751 };
 752
 753 /* Position of operand_type bits.  */
 754
 755 enum
 756 {
 757   /* Class and Instance */
 758   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 759   /* 1 bit immediate */
 760   Imm1,
 761   /* 8 bit immediate */
 762   Imm8,
 763   /* 8 bit immediate sign extended */
 764   Imm8S,
 765   /* 16 bit immediate */
 766   Imm16,
 767   /* 32 bit immediate */
 768   Imm32,
 769   /* 32 bit immediate sign extended */
 770   Imm32S,
 771   /* 64 bit immediate */
 772   Imm64,
 773   /* 8bit/16bit/32bit displacements are used in different ways,
 774      depending on the instruction.  For jumps, they specify the
 775      size of the PC relative displacement, for instructions with
 776      memory operand, they specify the size of the offset relative
 777      to the base register, and for instructions with memory offset
 778      such as `mov 1234,%al' they specify the size of the offset
 779      relative to the segment base.  */
 780   /* 8 bit displacement */
 781   Disp8,
 782   /* 16 bit displacement */
 783   Disp16,
 784   /* 32 bit displacement */
 785   Disp32,
 786   /* 32 bit signed displacement */
 787   Disp32S,
 788   /* 64 bit displacement */
 789   Disp64,
 790   /* Register which can be used for base or index in memory operand.  */
 791   BaseIndex,
 792   /* BYTE size. */
 793   Byte,
 794   /* WORD size. 2 byte */
 795   Word,
 796   /* DWORD size. 4 byte */
 797   Dword,
 798   /* FWORD size. 6 byte */
 799   Fword,
 800   /* QWORD size. 8 byte */
 801   Qword,
 802   /* TBYTE size. 10 byte */
 803   Tbyte,
 804   /* XMMWORD size. */
 805   Xmmword,
 806   /* YMMWORD size. */
 807   Ymmword,
 808   /* ZMMWORD size.  */
 809   Zmmword,
 810   /* Unspecified memory size.  */
 811   Unspecified,
 812
 813   /* The number of bits in i386_operand_type.  */
 814   OTNum
 815 };
 816
 817 #define OTNumOfUints \
 818   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 819 #define OTNumOfBits \
 820   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 821
 822 /* If you get a compiler error for zero width of the unused field,
 823    comment it out.  */
 824 #define OTUnused                OTNum
 825
 826 typedef union i386_operand_type
 827 {
 828   struct
 829     {
 830       unsigned int class:CLASS_WIDTH;
 831       unsigned int instance:INSTANCE_WIDTH;
 832       unsigned int imm1:1;
 833       unsigned int imm8:1;
 834       unsigned int imm8s:1;
 835       unsigned int imm16:1;
 836       unsigned int imm32:1;
 837       unsigned int imm32s:1;
 838       unsigned int imm64:1;
 839       unsigned int disp8:1;
 840       unsigned int disp16:1;
 841       unsigned int disp32:1;
 842       unsigned int disp32s:1;
 843       unsigned int disp64:1;
 844       unsigned int baseindex:1;
 845       unsigned int byte:1;
 846       unsigned int word:1;
 847       unsigned int dword:1;
 848       unsigned int fword:1;
 849       unsigned int qword:1;
 850       unsigned int tbyte:1;
 851       unsigned int xmmword:1;
 852       unsigned int ymmword:1;
 853       unsigned int zmmword:1;
 854       unsigned int unspecified:1;
 855 #ifdef OTUnused
 856       unsigned int unused:(OTNumOfBits - OTUnused);
 857 #endif
 858     } bitfield;
 859   unsigned int array[OTNumOfUints];
 860 } i386_operand_type;
 861
 862 typedef struct insn_template
 863 {
 864   /* instruction name sans width suffix ("mov" for movl insns) */
 865   char *name;
 866
 867   /* base_opcode is the fundamental opcode byte without optional
 868      prefix(es).  */
 869   unsigned int base_opcode;
 870 #define Opcode_D        0x2 /* Direction bit:
 871                                set if Reg --> Regmem;
 872                                unset if Regmem --> Reg. */
 873 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 874 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 875 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 876 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 877
 878   /* extension_opcode is the 3 bit extension for group <n> insns.
 879      This field is also used to store the 8-bit opcode suffix for the
 880      AMD 3DNow! instructions.
 881      If this template has no extension opcode (the usual case) use None
 882      Instructions */
 883   unsigned short extension_opcode;
 884 #define None 0xffff             /* If no extension_opcode is possible.  */
 885
 886   /* Opcode length.  */
 887   unsigned char opcode_length;
 888
 889   /* how many operands */
 890   unsigned char operands;
 891
 892   /* cpu feature flags */
 893   i386_cpu_flags cpu_flags;
 894
 895   /* the bits in opcode_modifier are used to generate the final opcode from
 896      the base_opcode.  These bits also are used to detect alternate forms of
 897      the same instruction */
 898   i386_opcode_modifier opcode_modifier;
 899
 900   /* operand_types[i] describes the type of operand i.  This is made
 901      by OR'ing together all of the possible type masks.  (e.g.
 902      'operand_types[i] = Reg|Imm' specifies that operand i can be
 903      either a register or an immediate operand.  */
 904   i386_operand_type operand_types[MAX_OPERANDS];
 905 }
 906 insn_template;
 907
 908 extern const insn_template i386_optab[];
 909
 910 /* these are for register name --> number & type hash lookup */
 911 typedef struct
 912 {
 913   const char *reg_name;
 914   i386_operand_type reg_type;
 915   unsigned char reg_flags;
 916 #define RegRex      0x1  /* Extended register.  */
 917 #define RegRex64    0x2  /* Extended 8 bit register.  */
 918 #define RegVRex     0x4  /* Extended vector register.  */
 919   unsigned char reg_num;
 920 #define RegIP   ((unsigned char ) ~0)
 921 /* EIZ and RIZ are fake index registers.  */
 922 #define RegIZ   (RegIP - 1)
 923 /* FLAT is a fake segment register (Intel mode).  */
 924 #define RegFlat     ((unsigned char) ~0)
 925   signed char dw2_regnum[2];
 926 #define Dw2Inval (-1)
 927 }
 928 reg_entry;
 929
 930 /* Entries in i386_regtab.  */
 931 #define REGNAM_AL 1
 932 #define REGNAM_AX 25
 933 #define REGNAM_EAX 41
 934
 935 extern const reg_entry i386_regtab[];
 936 extern const unsigned int i386_regtab_size;
 937
 938 typedef struct
 939 {
 940   char *seg_name;
 941   unsigned int seg_prefix;
 942 }
 943 seg_entry;
 944
 945 extern const seg_entry cs;
 946 extern const seg_entry ds;
 947 extern const seg_entry ss;
 948 extern const seg_entry es;
 949 extern const seg_entry fs;
 950 extern const seg_entry gs;