1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Intel IAMCU support required */
117 /* Xsave/xrstor New Instructions support required */
119 /* Xsaveopt New Instructions support required */
121 /* AES support required */
123 /* PCLMUL support required */
125 /* FMA support required */
127 /* FMA4 support required */
129 /* XOP support required */
131 /* LWP support required */
133 /* BMI support required */
135 /* TBM support required */
137 /* MOVBE Instruction support required */
139 /* CMPXCHG16B instruction support required. */
141 /* EPT Instructions required */
143 /* RDTSCP Instruction support required */
145 /* FSGSBASE Instructions required */
147 /* RDRND Instructions required */
149 /* F16C Instructions required */
151 /* Intel BMI2 support required */
153 /* LZCNT support required */
155 /* HLE support required */
157 /* RTM support required */
159 /* INVPCID Instructions required */
161 /* VMFUNC Instruction required */
163 /* Intel MPX Instructions required */
165 /* 64bit support available, used by -march= in assembler. */
167 /* RDRSEED instruction required. */
169 /* Multi-presisionn add-carry instructions are required. */
171 /* Supports prefetchw and prefetch instructions. */
173 /* SMAP instructions required. */
175 /* SHA instructions required. */
177 /* VREX support required */
179 /* CLFLUSHOPT instruction required */
181 /* XSAVES/XRSTORS instruction required */
183 /* XSAVEC instruction required */
185 /* PREFETCHWT1 instruction required */
187 /* SE1 instruction required */
189 /* CLWB instruction required */
191 /* Intel AVX-512 IFMA Instructions support required. */
193 /* Intel AVX-512 VBMI Instructions support required. */
195 /* Intel AVX-512 4FMAPS Instructions support required. */
197 /* Intel AVX-512 4VNNIW Instructions support required. */
199 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
201 /* Intel AVX-512 VBMI2 Instructions support required. */
203 /* Intel AVX-512 VNNI Instructions support required. */
205 /* Intel AVX-512 BITALG Instructions support required. */
207 /* mwaitx instruction required */
209 /* Clzero instruction required */
211 /* OSPKE instruction required */
213 /* RDPID instruction required */
215 /* PTWRITE instruction required */
217 /* CET instructions support required */
220 /* GFNI instructions required */
222 /* VAES instructions required */
224 /* VPCLMULQDQ instructions required */
226 /* WBNOINVD instructions required */
228 /* PCONFIG instructions required */
230 /* MMX register support required */
232 /* XMM register support required */
234 /* YMM register support required */
236 /* ZMM register support required */
238 /* Mask register support required */
240 /* 64bit support required */
242 /* Not supported in the 64bit mode */
244 /* The last bitfield in i386_cpu_flags. */
248 #define CpuNumOfUints \
249 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
250 #define CpuNumOfBits \
251 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
253 /* If you get a compiler error for zero width of the unused field,
255 #define CpuUnused (CpuMax + 1)
257 /* We can check if an instruction is available with array instead
259 typedef union i386_cpu_flags
263 unsigned int cpui186
:1;
264 unsigned int cpui286
:1;
265 unsigned int cpui386
:1;
266 unsigned int cpui486
:1;
267 unsigned int cpui586
:1;
268 unsigned int cpui686
:1;
269 unsigned int cpuclflush
:1;
270 unsigned int cpunop
:1;
271 unsigned int cpusyscall
:1;
272 unsigned int cpu8087
:1;
273 unsigned int cpu287
:1;
274 unsigned int cpu387
:1;
275 unsigned int cpu687
:1;
276 unsigned int cpufisttp
:1;
277 unsigned int cpummx
:1;
278 unsigned int cpusse
:1;
279 unsigned int cpusse2
:1;
280 unsigned int cpua3dnow
:1;
281 unsigned int cpua3dnowa
:1;
282 unsigned int cpusse3
:1;
283 unsigned int cpupadlock
:1;
284 unsigned int cpusvme
:1;
285 unsigned int cpuvmx
:1;
286 unsigned int cpusmx
:1;
287 unsigned int cpussse3
:1;
288 unsigned int cpusse4a
:1;
289 unsigned int cpuabm
:1;
290 unsigned int cpusse4_1
:1;
291 unsigned int cpusse4_2
:1;
292 unsigned int cpuavx
:1;
293 unsigned int cpuavx2
:1;
294 unsigned int cpuavx512f
:1;
295 unsigned int cpuavx512cd
:1;
296 unsigned int cpuavx512er
:1;
297 unsigned int cpuavx512pf
:1;
298 unsigned int cpuavx512vl
:1;
299 unsigned int cpuavx512dq
:1;
300 unsigned int cpuavx512bw
:1;
301 unsigned int cpul1om
:1;
302 unsigned int cpuk1om
:1;
303 unsigned int cpuiamcu
:1;
304 unsigned int cpuxsave
:1;
305 unsigned int cpuxsaveopt
:1;
306 unsigned int cpuaes
:1;
307 unsigned int cpupclmul
:1;
308 unsigned int cpufma
:1;
309 unsigned int cpufma4
:1;
310 unsigned int cpuxop
:1;
311 unsigned int cpulwp
:1;
312 unsigned int cpubmi
:1;
313 unsigned int cputbm
:1;
314 unsigned int cpumovbe
:1;
315 unsigned int cpucx16
:1;
316 unsigned int cpuept
:1;
317 unsigned int cpurdtscp
:1;
318 unsigned int cpufsgsbase
:1;
319 unsigned int cpurdrnd
:1;
320 unsigned int cpuf16c
:1;
321 unsigned int cpubmi2
:1;
322 unsigned int cpulzcnt
:1;
323 unsigned int cpuhle
:1;
324 unsigned int cpurtm
:1;
325 unsigned int cpuinvpcid
:1;
326 unsigned int cpuvmfunc
:1;
327 unsigned int cpumpx
:1;
328 unsigned int cpulm
:1;
329 unsigned int cpurdseed
:1;
330 unsigned int cpuadx
:1;
331 unsigned int cpuprfchw
:1;
332 unsigned int cpusmap
:1;
333 unsigned int cpusha
:1;
334 unsigned int cpuvrex
:1;
335 unsigned int cpuclflushopt
:1;
336 unsigned int cpuxsaves
:1;
337 unsigned int cpuxsavec
:1;
338 unsigned int cpuprefetchwt1
:1;
339 unsigned int cpuse1
:1;
340 unsigned int cpuclwb
:1;
341 unsigned int cpuavx512ifma
:1;
342 unsigned int cpuavx512vbmi
:1;
343 unsigned int cpuavx512_4fmaps
:1;
344 unsigned int cpuavx512_4vnniw
:1;
345 unsigned int cpuavx512_vpopcntdq
:1;
346 unsigned int cpuavx512_vbmi2
:1;
347 unsigned int cpuavx512_vnni
:1;
348 unsigned int cpuavx512_bitalg
:1;
349 unsigned int cpumwaitx
:1;
350 unsigned int cpuclzero
:1;
351 unsigned int cpuospke
:1;
352 unsigned int cpurdpid
:1;
353 unsigned int cpuptwrite
:1;
354 unsigned int cpuibt
:1;
355 unsigned int cpushstk
:1;
356 unsigned int cpugfni
:1;
357 unsigned int cpuvaes
:1;
358 unsigned int cpuvpclmulqdq
:1;
359 unsigned int cpuwbnoinvd
:1;
360 unsigned int cpupconfig
:1;
361 unsigned int cpuregmmx
:1;
362 unsigned int cpuregxmm
:1;
363 unsigned int cpuregymm
:1;
364 unsigned int cpuregzmm
:1;
365 unsigned int cpuregmask
:1;
366 unsigned int cpu64
:1;
367 unsigned int cpuno64
:1;
369 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
372 unsigned int array
[CpuNumOfUints
];
375 /* Position of opcode_modifier bits. */
379 /* has direction bit. */
381 /* set if operands can be words or dwords encoded the canonical way */
383 /* load form instruction. Must be placed before store form. */
385 /* insn has a modrm byte. */
387 /* register is in low 3 bits of opcode */
389 /* special case for jump insns. */
395 /* special case for intersegment leaps/calls */
397 /* FP insn memory format bit, sized by 0x4 */
399 /* src/dest swap for floats. */
401 /* needs size prefix if in 32-bit mode */
403 /* needs size prefix if in 16-bit mode */
405 /* needs size prefix if in 64-bit mode */
407 /* check register size. */
409 /* instruction ignores operand size prefix and in Intel mode ignores
410 mnemonic size suffix check. */
412 /* default insn size depends on mode */
414 /* b suffix on instruction illegal */
416 /* w suffix on instruction illegal */
418 /* l suffix on instruction illegal */
420 /* s suffix on instruction illegal */
422 /* q suffix on instruction illegal */
424 /* long double suffix on instruction illegal */
426 /* instruction needs FWAIT */
428 /* quick test for string instructions */
430 /* quick test if branch instruction is MPX supported */
432 /* quick test if NOTRACK prefix is supported */
434 /* quick test for lockable instructions */
436 /* fake an extra reg operand for clr, imul and special register
437 processing for some instructions. */
439 /* An implicit xmm0 as the first operand */
441 /* The HLE prefix is OK:
442 1. With a LOCK prefix.
443 2. With or without a LOCK prefix.
444 3. With a RELEASE (0xf3) prefix.
446 #define HLEPrefixNone 0
447 #define HLEPrefixLock 1
448 #define HLEPrefixAny 2
449 #define HLEPrefixRelease 3
451 /* An instruction on which a "rep" prefix is acceptable. */
453 /* Convert to DWORD */
455 /* Convert to QWORD */
457 /* Address prefix changes operand 0 */
459 /* opcode is a prefix */
461 /* instruction has extension in 8 bit imm */
463 /* instruction don't need Rex64 prefix. */
465 /* instruction require Rex64 prefix. */
467 /* deprecated fp insn, gets a warning */
469 /* insn has VEX prefix:
470 1: 128bit VEX prefix (or operand dependent).
471 2: 256bit VEX prefix.
472 3: Scalar VEX prefix.
478 /* How to encode VEX.vvvv:
479 0: VEX.vvvv must be 1111b.
480 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
481 the content of source registers will be preserved.
482 VEX.DDS. The second register operand is encoded in VEX.vvvv
483 where the content of first source register will be overwritten
485 VEX.NDD2. The second destination register operand is encoded in
486 VEX.vvvv for instructions with 2 destination register operands.
487 For assembler, there are no difference between VEX.NDS, VEX.DDS
489 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
490 instructions with 1 destination register operand.
491 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
492 of the operands can access a memory location.
498 /* How the VEX.W bit is used:
499 0: Set by the REX.W bit.
500 1: VEX.W0. Should always be 0.
501 2: VEX.W1. Should always be 1.
506 /* VEX opcode prefix:
507 0: VEX 0x0F opcode prefix.
508 1: VEX 0x0F38 opcode prefix.
509 2: VEX 0x0F3A opcode prefix
510 3: XOP 0x08 opcode prefix.
511 4: XOP 0x09 opcode prefix
512 5: XOP 0x0A opcode prefix.
521 /* number of VEX source operands:
522 0: <= 2 source operands.
523 1: 2 XOP source operands.
524 2: 3 source operands.
526 #define XOP2SOURCES 1
527 #define VEX3SOURCES 2
529 /* instruction has VEX 8 bit imm */
531 /* Instruction with vector SIB byte:
532 1: 128bit vector register.
533 2: 256bit vector register.
534 3: 512bit vector register.
540 /* SSE to AVX support required */
542 /* No AVX equivalent */
545 /* insn has EVEX prefix:
546 1: 512bit EVEX prefix.
547 2: 128bit EVEX prefix.
548 3: 256bit EVEX prefix.
549 4: Length-ignored (LIG) EVEX prefix.
550 5: Length determined from actual operands.
559 /* AVX512 masking support:
562 3: Both zeroing and merging masking.
564 #define ZEROING_MASKING 1
565 #define MERGING_MASKING 2
566 #define BOTH_MASKING 3
569 /* Input element size of vector insn:
580 #define NO_BROADCAST 0
581 #define BROADCAST_1TO16 1
582 #define BROADCAST_1TO8 2
583 #define BROADCAST_1TO4 3
584 #define BROADCAST_1TO2 4
587 /* Static rounding control is supported. */
590 /* Supress All Exceptions is supported. */
593 /* Copressed Disp8*N attribute. */
596 /* Default mask isn't allowed. */
599 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
600 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
604 /* Support encoding optimization. */
607 /* Compatible with old (<= 2.8.1) versions of gcc */
619 /* The last bitfield in i386_opcode_modifier. */
623 typedef struct i386_opcode_modifier
628 unsigned int modrm
:1;
629 unsigned int shortform
:1;
631 unsigned int jumpdword
:1;
632 unsigned int jumpbyte
:1;
633 unsigned int jumpintersegment
:1;
634 unsigned int floatmf
:1;
635 unsigned int floatr
:1;
636 unsigned int size16
:1;
637 unsigned int size32
:1;
638 unsigned int size64
:1;
639 unsigned int checkregsize
:1;
640 unsigned int ignoresize
:1;
641 unsigned int defaultsize
:1;
642 unsigned int no_bsuf
:1;
643 unsigned int no_wsuf
:1;
644 unsigned int no_lsuf
:1;
645 unsigned int no_ssuf
:1;
646 unsigned int no_qsuf
:1;
647 unsigned int no_ldsuf
:1;
648 unsigned int fwait
:1;
649 unsigned int isstring
:1;
650 unsigned int bndprefixok
:1;
651 unsigned int notrackprefixok
:1;
652 unsigned int islockable
:1;
653 unsigned int regkludge
:1;
654 unsigned int implicit1stxmm0
:1;
655 unsigned int hleprefixok
:2;
656 unsigned int repprefixok
:1;
657 unsigned int todword
:1;
658 unsigned int toqword
:1;
659 unsigned int addrprefixop0
:1;
660 unsigned int isprefix
:1;
661 unsigned int immext
:1;
662 unsigned int norex64
:1;
663 unsigned int rex64
:1;
666 unsigned int vexvvvv
:2;
668 unsigned int vexopcode
:3;
669 unsigned int vexsources
:2;
670 unsigned int veximmext
:1;
671 unsigned int vecsib
:2;
672 unsigned int sse2avx
:1;
673 unsigned int noavx
:1;
675 unsigned int masking
:2;
676 unsigned int vecesize
:1;
677 unsigned int broadcast
:3;
678 unsigned int staticrounding
:1;
680 unsigned int disp8memshift
:3;
681 unsigned int nodefmask
:1;
682 unsigned int implicitquadgroup
:1;
683 unsigned int optimize
:1;
684 unsigned int oldgcc
:1;
685 unsigned int attmnemonic
:1;
686 unsigned int attsyntax
:1;
687 unsigned int intelsyntax
:1;
688 unsigned int amd64
:1;
689 unsigned int intel64
:1;
690 } i386_opcode_modifier
;
692 /* Position of operand_type bits. */
696 /* Register (qualified by Byte, Word, etc) */
700 /* Vector registers */
702 /* Vector Mask registers */
704 /* Control register */
710 /* 2 bit segment register */
712 /* 3 bit segment register */
714 /* 1 bit immediate */
716 /* 8 bit immediate */
718 /* 8 bit immediate sign extended */
720 /* 16 bit immediate */
722 /* 32 bit immediate */
724 /* 32 bit immediate sign extended */
726 /* 64 bit immediate */
728 /* 8bit/16bit/32bit displacements are used in different ways,
729 depending on the instruction. For jumps, they specify the
730 size of the PC relative displacement, for instructions with
731 memory operand, they specify the size of the offset relative
732 to the base register, and for instructions with memory offset
733 such as `mov 1234,%al' they specify the size of the offset
734 relative to the segment base. */
735 /* 8 bit displacement */
737 /* 16 bit displacement */
739 /* 32 bit displacement */
741 /* 32 bit signed displacement */
743 /* 64 bit displacement */
745 /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
747 /* Register which can be used for base or index in memory operand. */
749 /* Register to hold in/out port addr = dx */
751 /* Register to hold shift count = cl */
753 /* Absolute address for jump. */
755 /* String insn operand with fixed es segment */
757 /* RegMem is for instructions with a modrm byte where the register
758 destination operand should be encoded in the mod and regmem fields.
759 Normally, it will be encoded in the reg field. We add a RegMem
760 flag to the destination register operand to indicate that it should
761 be encoded in the regmem field. */
767 /* WORD memory. 2 byte */
769 /* DWORD memory. 4 byte */
771 /* FWORD memory. 6 byte */
773 /* QWORD memory. 8 byte */
775 /* TBYTE memory. 10 byte */
777 /* XMMWORD memory. */
779 /* YMMWORD memory. */
781 /* ZMMWORD memory. */
783 /* Unspecified memory size. */
785 /* Any memory size. */
788 /* Vector 4 bit immediate. */
791 /* Bound register. */
794 /* The last bitfield in i386_operand_type. */
798 #define OTNumOfUints \
799 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
800 #define OTNumOfBits \
801 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
803 /* If you get a compiler error for zero width of the unused field,
805 #define OTUnused (OTMax + 1)
807 typedef union i386_operand_type
812 unsigned int regmmx
:1;
813 unsigned int regsimd
:1;
814 unsigned int regmask
:1;
815 unsigned int control
:1;
816 unsigned int debug
:1;
818 unsigned int sreg2
:1;
819 unsigned int sreg3
:1;
822 unsigned int imm8s
:1;
823 unsigned int imm16
:1;
824 unsigned int imm32
:1;
825 unsigned int imm32s
:1;
826 unsigned int imm64
:1;
827 unsigned int disp8
:1;
828 unsigned int disp16
:1;
829 unsigned int disp32
:1;
830 unsigned int disp32s
:1;
831 unsigned int disp64
:1;
833 unsigned int baseindex
:1;
834 unsigned int inoutportreg
:1;
835 unsigned int shiftcount
:1;
836 unsigned int jumpabsolute
:1;
837 unsigned int esseg
:1;
838 unsigned int regmem
:1;
842 unsigned int dword
:1;
843 unsigned int fword
:1;
844 unsigned int qword
:1;
845 unsigned int tbyte
:1;
846 unsigned int xmmword
:1;
847 unsigned int ymmword
:1;
848 unsigned int zmmword
:1;
849 unsigned int unspecified
:1;
850 unsigned int anysize
:1;
851 unsigned int vec_imm4
:1;
852 unsigned int regbnd
:1;
854 unsigned int unused
:(OTNumOfBits
- OTUnused
);
857 unsigned int array
[OTNumOfUints
];
860 typedef struct insn_template
862 /* instruction name sans width suffix ("mov" for movl insns) */
865 /* how many operands */
866 unsigned int operands
;
868 /* base_opcode is the fundamental opcode byte without optional
870 unsigned int base_opcode
;
871 #define Opcode_D 0x2 /* Direction bit:
872 set if Reg --> Regmem;
873 unset if Regmem --> Reg. */
874 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
875 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
877 /* extension_opcode is the 3 bit extension for group <n> insns.
878 This field is also used to store the 8-bit opcode suffix for the
879 AMD 3DNow! instructions.
880 If this template has no extension opcode (the usual case) use None
882 unsigned int extension_opcode
;
883 #define None 0xffff /* If no extension_opcode is possible. */
886 unsigned char opcode_length
;
888 /* cpu feature flags */
889 i386_cpu_flags cpu_flags
;
891 /* the bits in opcode_modifier are used to generate the final opcode from
892 the base_opcode. These bits also are used to detect alternate forms of
893 the same instruction */
894 i386_opcode_modifier opcode_modifier
;
896 /* operand_types[i] describes the type of operand i. This is made
897 by OR'ing together all of the possible type masks. (e.g.
898 'operand_types[i] = Reg|Imm' specifies that operand i can be
899 either a register or an immediate operand. */
900 i386_operand_type operand_types
[MAX_OPERANDS
];
904 extern const insn_template i386_optab
[];
906 /* these are for register name --> number & type hash lookup */
910 i386_operand_type reg_type
;
911 unsigned char reg_flags
;
912 #define RegRex 0x1 /* Extended register. */
913 #define RegRex64 0x2 /* Extended 8 bit register. */
914 #define RegVRex 0x4 /* Extended vector register. */
915 unsigned char reg_num
;
916 #define RegRip ((unsigned char ) ~0)
917 #define RegEip (RegRip - 1)
918 /* EIZ and RIZ are fake index registers. */
919 #define RegEiz (RegEip - 1)
920 #define RegRiz (RegEiz - 1)
921 /* FLAT is a fake segment register (Intel mode). */
922 #define RegFlat ((unsigned char) ~0)
923 signed char dw2_regnum
[2];
924 #define Dw2Inval (-1)
928 /* Entries in i386_regtab. */
931 #define REGNAM_EAX 41
933 extern const reg_entry i386_regtab
[];
934 extern const unsigned int i386_regtab_size
;
939 unsigned int seg_prefix
;
943 extern const seg_entry cs
;
944 extern const seg_entry ds
;
945 extern const seg_entry ss
;
946 extern const seg_entry es
;
947 extern const seg_entry fs
;
948 extern const seg_entry gs
;