opcodes/m32r-opc.h

   1 /* Instruction description for m32r.
   2
   3 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   4
   5 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20
  21 */
  22
  23 #ifndef m32r_OPC_H
  24 #define m32r_OPC_H
  25
  26 #define CGEN_ARCH m32r
  27 /* Given symbol S, return m32r_cgen_<s>.  */
  28 #define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)
  29
  30 #define CGEN_WORD_BITSIZE 32
  31 #define CGEN_DEFAULT_INSN_BITSIZE 32
  32 #define CGEN_BASE_INSN_BITSIZE 32
  33 #define CGEN_MAX_INSN_BITSIZE 32
  34 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
  35 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
  36 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
  37 #define CGEN_INT_INSN
  38
  39 /* +1 because the first entry is reserved (null) */
  40 #define CGEN_NUM_INSNS (127 + 1)
  41 #define CGEN_NUM_OPERANDS (21)
  42
  43 /* Number of non-boolean attributes. */
  44 #define CGEN_MAX_INSN_ATTRS 0
  45 #define CGEN_MAX_OPERAND_ATTRS 0
  46
  47 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  48
  49 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  50    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  51    we can't hash on everything up to the space.  */
  52 #define CGEN_MNEMONIC_OPERANDS
  53
  54 /* Number of architecture variants.  */
  55 #define MAX_MACHS 1
  56
  57 /* Enums.  */
  58
  59 /* Enum declaration for insn format enums.  */
  60 typedef enum insn_op1 {
  61   OP1_0 = 0, OP1_1 = 1, OP1_2 = 2, OP1_3 = 3,
  62   OP1_4 = 4, OP1_5 = 5, OP1_6 = 6, OP1_7 = 7,
  63   OP1_8 = 8, OP1_9 = 9, OP1_10 = 10, OP1_11 = 11,
  64   OP1_12 = 12, OP1_13 = 13, OP1_14 = 14, OP1_15 = 15
  65 } INSN_OP1;
  66
  67 /* Enum declaration for op2 enums.  */
  68 typedef enum insn_op2 {
  69   OP2_0 = 0, OP2_1 = 1, OP2_2 = 2, OP2_3 = 3,
  70   OP2_4 = 4, OP2_5 = 5, OP2_6 = 6, OP2_7 = 7,
  71   OP2_8 = 8, OP2_9 = 9, OP2_10 = 10, OP2_11 = 11,
  72   OP2_12 = 12, OP2_13 = 13, OP2_14 = 14, OP2_15 = 15
  73 } INSN_OP2;
  74
  75 /* Enum declaration for m32r operand types.  */
  76 typedef enum cgen_operand_type {
  77   M32R_OPERAND_PC = 0, M32R_OPERAND_SR = 1, M32R_OPERAND_DR = 2, M32R_OPERAND_SRC1 = 3,
  78   M32R_OPERAND_SRC2 = 4, M32R_OPERAND_SCR = 5, M32R_OPERAND_DCR = 6, M32R_OPERAND_SIMM8 = 7,
  79   M32R_OPERAND_SIMM16 = 8, M32R_OPERAND_UIMM4 = 9, M32R_OPERAND_UIMM5 = 10, M32R_OPERAND_UIMM16 = 11,
  80   M32R_OPERAND_HI16 = 12, M32R_OPERAND_SLO16 = 13, M32R_OPERAND_ULO16 = 14, M32R_OPERAND_UIMM24 = 15,
  81   M32R_OPERAND_DISP8 = 16, M32R_OPERAND_DISP16 = 17, M32R_OPERAND_DISP24 = 18, M32R_OPERAND_CONDBIT = 19,
  82   M32R_OPERAND_ACCUM = 20
  83 } CGEN_OPERAND_TYPE;
  84
  85 /* Non-boolean attributes.  */
  86
  87 /* Enum declaration for machine type selection.  */
  88 typedef enum mach_attr {
  89   MACH_M32R = 0
  90 } MACH_ATTR;
  91
  92 /* Operand and instruction attribute indices.  */
  93
  94 /* Enum declaration for cgen_operand attrs.  */
  95 typedef enum cgen_operand_attr {
  96   CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC,
  97   CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT,
  98   CGEN_OPERAND_UNSIGNED
  99 } CGEN_OPERAND_ATTR;
 100
 101 /* Enum declaration for cgen_insn attrs.  */
 102 typedef enum cgen_insn_attr {
 103   CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_RELAX,
 104   CGEN_INSN_RELAX_BC, CGEN_INSN_RELAX_BL, CGEN_INSN_RELAX_BNC, CGEN_INSN_RELAX_BRA,
 105   CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
 106 } CGEN_INSN_ATTR;
 107
 108 /* Insn types are used by the simulator.  */
 109 /* Enum declaration for m32r instruction types.  */
 110 typedef enum cgen_insn_type {
 111   M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND,
 112   M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR,
 113   M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3,
 114   M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC8_S, M32R_INSN_BC24,
 115   M32R_INSN_BC24_L, M32R_INSN_BEQ, M32R_INSN_BEQZ, M32R_INSN_BGEZ,
 116   M32R_INSN_BGTZ, M32R_INSN_BLEZ, M32R_INSN_BLTZ, M32R_INSN_BNEZ,
 117   M32R_INSN_BL8, M32R_INSN_BL8_S, M32R_INSN_BL24, M32R_INSN_BL24_L,
 118   M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L,
 119   M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24,
 120   M32R_INSN_BRA24_L, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU,
 121   M32R_INSN_CMPUI, M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM,
 122   M32R_INSN_REMU, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD,
 123   M32R_INSN_LD_2, M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB,
 124   M32R_INSN_LDB_2, M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH,
 125   M32R_INSN_LDH_2, M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB,
 126   M32R_INSN_LDUB_2, M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH,
 127   M32R_INSN_LDUH_2, M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS,
 128   M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI8A, M32R_INSN_LDI16,
 129   M32R_INSN_LDI16A, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACLO,
 130   M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI,
 131   M32R_INSN_MULLO, M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV,
 132   M32R_INSN_MVFACHI, M32R_INSN_MVFACLO, M32R_INSN_MVFACMI, M32R_INSN_MVFC,
 133   M32R_INSN_MVTACHI, M32R_INSN_MVTACLO, M32R_INSN_MVTC, M32R_INSN_NEG,
 134   M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC, M32R_INSN_RACH,
 135   M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3,
 136   M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI,
 137   M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST,
 138   M32R_INSN_ST_2, M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB,
 139   M32R_INSN_STB_2, M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH,
 140   M32R_INSN_STH_2, M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS,
 141   M32R_INSN_ST_MINUS, M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX,
 142   M32R_INSN_TRAP, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP,
 143   M32R_INSN_MAX
 144 } CGEN_INSN_TYPE;
 145
 146 /* Index of `illegal' insn place holder.  */
 147 #define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
 148 /* Total number of insns in table.  */
 149 #define CGEN_MAX_INSNS ((int) M32R_INSN_MAX)
 150
 151 /* cgen.h uses things we just defined.  */
 152 #include "opcode/cgen.h"
 153
 154 /* This struct records data prior to insertion or after extraction.  */
 155 typedef struct cgen_fields
 156 {
 157   long f_nil;
 158   long f_op1;
 159   long f_op2;
 160   long f_cond;
 161   long f_r1;
 162   long f_r2;
 163   long f_simm8;
 164   long f_simm16;
 165   long f_shift_op2;
 166   long f_uimm4;
 167   long f_uimm5;
 168   long f_uimm16;
 169   long f_uimm24;
 170   long f_hi16;
 171   long f_disp8;
 172   long f_disp16;
 173   long f_disp24;
 174   int length;
 175 } CGEN_FIELDS;
 176
 177 /* Attributes.  */
 178 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
 179 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 180
 181 extern CGEN_KEYWORD m32r_cgen_opval_mach;
 182 extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
 183 extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
 184
 185 #define CGEN_INIT_PARSE() \
 186 {\
 187 }
 188 #define CGEN_INIT_INSERT() \
 189 {\
 190 }
 191 #define CGEN_INIT_EXTRACT() \
 192 {\
 193 }
 194 #define CGEN_INIT_PRINT() \
 195 {\
 196 }
 197
 198 /* -- opc.h */
 199
 200 #undef CGEN_DIS_HASH_SIZE
 201 #define CGEN_DIS_HASH_SIZE 256
 202 #undef CGEN_DIS_HASH
 203 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
 204 #define CGEN_DIS_HASH(buffer, insn) \
 205 (X (buffer) | \
 206  (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
 207   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
 208   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
 209
 210 /* -- */
 211
 212
 213 #endif /* m32r_OPC_H */