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Remove ppc860, ppc750cl, ppc7450 insns from common ppc.
[thirdparty/binutils-gdb.git] / opcodes / ppc-dis.c
1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "dis-asm.h"
25 #include "elf-bfd.h"
26 #include "elf/ppc.h"
27 #include "opintl.h"
28 #include "opcode/ppc.h"
29
30 /* This file provides several disassembler functions, all of which use
31 the disassembler interface defined in dis-asm.h. Several functions
32 are provided because this file handles disassembly for the PowerPC
33 in both big and little endian mode and also for the POWER (RS/6000)
34 chip. */
35 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
36 ppc_cpu_t);
37
38 struct dis_private
39 {
40 /* Stash the result of parsing disassembler_options here. */
41 ppc_cpu_t dialect;
42 } private;
43
44 #define POWERPC_DIALECT(INFO) \
45 (((struct dis_private *) ((INFO)->private_data))->dialect)
46
47 struct ppc_mopt {
48 const char *opt;
49 ppc_cpu_t cpu;
50 ppc_cpu_t sticky;
51 };
52
53 struct ppc_mopt ppc_opts[] = {
54 { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403),
55 0 },
56 { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
57 0 },
58 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
59 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
60 0 },
61 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
62 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
63 0 },
64 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
65 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
66 0 },
67 { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601),
68 0 },
69 { "603", (PPC_OPCODE_PPC),
70 0 },
71 { "604", (PPC_OPCODE_PPC),
72 0 },
73 { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64),
74 0 },
75 { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
76 0 },
77 { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
78 0 },
79 { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC),
80 0 },
81 { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
82 0 },
83 { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS)
84 , 0 },
85 { "821", (PPC_OPCODE_PPC | PPC_OPCODE_860),
86 0 },
87 { "850", (PPC_OPCODE_PPC | PPC_OPCODE_860),
88 0 },
89 { "860", (PPC_OPCODE_PPC | PPC_OPCODE_860),
90 0 },
91 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
92 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
93 | PPC_OPCODE_A2),
94 0 },
95 { "altivec", (PPC_OPCODE_PPC),
96 PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
97 { "any", 0,
98 PPC_OPCODE_ANY },
99 { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
100 0 },
101 { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
102 0 },
103 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
104 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
105 0 },
106 { "com", (PPC_OPCODE_COMMON),
107 0 },
108 { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300),
109 0 },
110 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
111 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
112 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
113 | PPC_OPCODE_E500),
114 0 },
115 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
116 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
117 | PPC_OPCODE_E500MC),
118 0 },
119 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
120 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
121 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
122 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
123 0 },
124 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
125 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
126 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
127 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
128 | PPC_OPCODE_POWER7),
129 0 },
130 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
131 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
132 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
133 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
134 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
135 0 },
136 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
137 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
138 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
139 | PPC_OPCODE_E500),
140 0 },
141 { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
142 0 },
143 { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
144 0 },
145 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
146 | PPC_OPCODE_POWER5),
147 0 },
148 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
149 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
150 0 },
151 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
152 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
153 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
154 0 },
155 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
156 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
157 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
158 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
159 0 },
160 { "ppc", (PPC_OPCODE_PPC),
161 0 },
162 { "ppc32", (PPC_OPCODE_PPC),
163 0 },
164 { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64),
165 0 },
166 { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
167 0 },
168 { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
169 0 },
170 { "pwr", (PPC_OPCODE_POWER),
171 0 },
172 { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
173 0 },
174 { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
175 0 },
176 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
177 | PPC_OPCODE_POWER5),
178 0 },
179 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
180 | PPC_OPCODE_POWER5),
181 0 },
182 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
183 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
184 0 },
185 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
186 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
187 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
188 0 },
189 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
190 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
191 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
192 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
193 0 },
194 { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
195 0 },
196 { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
197 PPC_OPCODE_SPE },
198 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
199 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
200 0 },
201 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
202 PPC_OPCODE_VLE },
203 { "vsx", (PPC_OPCODE_PPC),
204 PPC_OPCODE_VSX },
205 { "htm", (PPC_OPCODE_PPC),
206 PPC_OPCODE_HTM },
207 };
208
209 /* Switch between Booke and VLE dialects for interlinked dumps. */
210 static ppc_cpu_t
211 get_powerpc_dialect (struct disassemble_info *info)
212 {
213 ppc_cpu_t dialect = 0;
214
215 dialect = POWERPC_DIALECT (info);
216
217 /* Disassemble according to the section headers flags for VLE-mode. */
218 if (dialect & PPC_OPCODE_VLE
219 && info->section->owner != NULL
220 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
221 && elf_object_id (info->section->owner) == PPC32_ELF_DATA
222 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
223 return dialect;
224 else
225 return dialect & ~ PPC_OPCODE_VLE;
226 }
227
228 /* Handle -m and -M options that set cpu type, and .machine arg. */
229
230 ppc_cpu_t
231 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
232 {
233 unsigned int i;
234
235 for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
236 if (strcmp (ppc_opts[i].opt, arg) == 0)
237 {
238 if (ppc_opts[i].sticky)
239 {
240 *sticky |= ppc_opts[i].sticky;
241 if ((ppc_cpu & ~*sticky) != 0)
242 break;
243 }
244 ppc_cpu = ppc_opts[i].cpu;
245 break;
246 }
247 if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
248 return 0;
249
250 ppc_cpu |= *sticky;
251 return ppc_cpu;
252 }
253
254 /* Determine which set of machines to disassemble for. */
255
256 static void
257 powerpc_init_dialect (struct disassemble_info *info)
258 {
259 ppc_cpu_t dialect = 0;
260 ppc_cpu_t sticky = 0;
261 char *arg;
262 struct dis_private *priv = calloc (sizeof (*priv), 1);
263
264 if (priv == NULL)
265 priv = &private;
266
267 switch (info->mach)
268 {
269 case bfd_mach_ppc_403:
270 case bfd_mach_ppc_403gc:
271 dialect = ppc_parse_cpu (dialect, &sticky, "403");
272 break;
273 case bfd_mach_ppc_405:
274 dialect = ppc_parse_cpu (dialect, &sticky, "405");
275 break;
276 case bfd_mach_ppc_601:
277 dialect = ppc_parse_cpu (dialect, &sticky, "601");
278 break;
279 case bfd_mach_ppc_a35:
280 case bfd_mach_ppc_rs64ii:
281 case bfd_mach_ppc_rs64iii:
282 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
283 break;
284 case bfd_mach_ppc_e500:
285 dialect = ppc_parse_cpu (dialect, &sticky, "e500");
286 break;
287 case bfd_mach_ppc_e500mc:
288 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
289 break;
290 case bfd_mach_ppc_e500mc64:
291 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
292 break;
293 case bfd_mach_ppc_e5500:
294 dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
295 break;
296 case bfd_mach_ppc_e6500:
297 dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
298 break;
299 case bfd_mach_ppc_titan:
300 dialect = ppc_parse_cpu (dialect, &sticky, "titan");
301 break;
302 case bfd_mach_ppc_vle:
303 dialect = ppc_parse_cpu (dialect, &sticky, "vle");
304 break;
305 default:
306 dialect = ppc_parse_cpu (dialect, &sticky, "power8") | PPC_OPCODE_ANY;
307 }
308
309 arg = info->disassembler_options;
310 while (arg != NULL)
311 {
312 ppc_cpu_t new_cpu = 0;
313 char *end = strchr (arg, ',');
314
315 if (end != NULL)
316 *end = 0;
317
318 if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
319 dialect = new_cpu;
320 else if (strcmp (arg, "32") == 0)
321 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
322 else if (strcmp (arg, "64") == 0)
323 dialect |= PPC_OPCODE_64;
324 else
325 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
326
327 if (end != NULL)
328 *end++ = ',';
329 arg = end;
330 }
331
332 info->private_data = priv;
333 POWERPC_DIALECT(info) = dialect;
334 }
335
336 #define PPC_OPCD_SEGS 64
337 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
338 #define VLE_OPCD_SEGS 32
339 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
340
341 /* Calculate opcode table indices to speed up disassembly,
342 and init dialect. */
343
344 void
345 disassemble_init_powerpc (struct disassemble_info *info)
346 {
347 int i;
348 unsigned short last;
349
350 if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
351 {
352
353 i = powerpc_num_opcodes;
354 while (--i >= 0)
355 {
356 unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
357
358 powerpc_opcd_indices[op] = i;
359 }
360
361 last = powerpc_num_opcodes;
362 for (i = PPC_OPCD_SEGS; i > 0; --i)
363 {
364 if (powerpc_opcd_indices[i] == 0)
365 powerpc_opcd_indices[i] = last;
366 last = powerpc_opcd_indices[i];
367 }
368
369 i = vle_num_opcodes;
370 while (--i >= 0)
371 {
372 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
373 unsigned seg = VLE_OP_TO_SEG (op);
374
375 vle_opcd_indices[seg] = i;
376 }
377
378 last = vle_num_opcodes;
379 for (i = VLE_OPCD_SEGS; i > 0; --i)
380 {
381 if (vle_opcd_indices[i] == 0)
382 vle_opcd_indices[i] = last;
383 last = vle_opcd_indices[i];
384 }
385 }
386
387 if (info->arch == bfd_arch_powerpc)
388 powerpc_init_dialect (info);
389 }
390
391 /* Print a big endian PowerPC instruction. */
392
393 int
394 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
395 {
396 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
397 }
398
399 /* Print a little endian PowerPC instruction. */
400
401 int
402 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
403 {
404 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
405 }
406
407 /* Print a POWER (RS/6000) instruction. */
408
409 int
410 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
411 {
412 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
413 }
414
415 /* Extract the operand value from the PowerPC or POWER instruction. */
416
417 static long
418 operand_value_powerpc (const struct powerpc_operand *operand,
419 unsigned long insn, ppc_cpu_t dialect)
420 {
421 long value;
422 int invalid;
423 /* Extract the value from the instruction. */
424 if (operand->extract)
425 value = (*operand->extract) (insn, dialect, &invalid);
426 else
427 {
428 if (operand->shift >= 0)
429 value = (insn >> operand->shift) & operand->bitm;
430 else
431 value = (insn << -operand->shift) & operand->bitm;
432 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
433 {
434 /* BITM is always some number of zeros followed by some
435 number of ones, followed by some number of zeros. */
436 unsigned long top = operand->bitm;
437 /* top & -top gives the rightmost 1 bit, so this
438 fills in any trailing zeros. */
439 top |= (top & -top) - 1;
440 top &= ~(top >> 1);
441 value = (value ^ top) - top;
442 }
443 }
444
445 return value;
446 }
447
448 /* Determine whether the optional operand(s) should be printed. */
449
450 static int
451 skip_optional_operands (const unsigned char *opindex,
452 unsigned long insn, ppc_cpu_t dialect)
453 {
454 const struct powerpc_operand *operand;
455
456 for (; *opindex != 0; opindex++)
457 {
458 operand = &powerpc_operands[*opindex];
459 if ((operand->flags & PPC_OPERAND_NEXT) != 0
460 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
461 && operand_value_powerpc (operand, insn, dialect) !=
462 ppc_optional_operand_value (operand)))
463 return 0;
464 }
465
466 return 1;
467 }
468
469 /* Find a match for INSN in the opcode table, given machine DIALECT.
470 A DIALECT of -1 is special, matching all machine opcode variations. */
471
472 static const struct powerpc_opcode *
473 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
474 {
475 const struct powerpc_opcode *opcode;
476 const struct powerpc_opcode *opcode_end;
477 unsigned long op;
478
479 /* Get the major opcode of the instruction. */
480 op = PPC_OP (insn);
481
482 /* Find the first match in the opcode table for this major opcode. */
483 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
484 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
485 opcode < opcode_end;
486 ++opcode)
487 {
488 const unsigned char *opindex;
489 const struct powerpc_operand *operand;
490 int invalid;
491
492 if ((insn & opcode->mask) != opcode->opcode
493 || (dialect != (ppc_cpu_t) -1
494 && ((opcode->flags & dialect) == 0
495 || (opcode->deprecated & dialect) != 0)))
496 continue;
497
498 /* Check validity of operands. */
499 invalid = 0;
500 for (opindex = opcode->operands; *opindex != 0; opindex++)
501 {
502 operand = powerpc_operands + *opindex;
503 if (operand->extract)
504 (*operand->extract) (insn, dialect, &invalid);
505 }
506 if (invalid)
507 continue;
508
509 return opcode;
510 }
511
512 return NULL;
513 }
514
515 /* Find a match for INSN in the VLE opcode table. */
516
517 static const struct powerpc_opcode *
518 lookup_vle (unsigned long insn)
519 {
520 const struct powerpc_opcode *opcode;
521 const struct powerpc_opcode *opcode_end;
522 unsigned op, seg;
523
524 op = PPC_OP (insn);
525 if (op >= 0x20 && op <= 0x37)
526 {
527 /* This insn has a 4-bit opcode. */
528 op &= 0x3c;
529 }
530 seg = VLE_OP_TO_SEG (op);
531
532 /* Find the first match in the opcode table for this major opcode. */
533 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
534 for (opcode = vle_opcodes + vle_opcd_indices[seg];
535 opcode < opcode_end;
536 ++opcode)
537 {
538 unsigned long table_opcd = opcode->opcode;
539 unsigned long table_mask = opcode->mask;
540 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
541 unsigned long insn2;
542 const unsigned char *opindex;
543 const struct powerpc_operand *operand;
544 int invalid;
545
546 insn2 = insn;
547 if (table_op_is_short)
548 insn2 >>= 16;
549 if ((insn2 & table_mask) != table_opcd)
550 continue;
551
552 /* Check validity of operands. */
553 invalid = 0;
554 for (opindex = opcode->operands; *opindex != 0; ++opindex)
555 {
556 operand = powerpc_operands + *opindex;
557 if (operand->extract)
558 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
559 }
560 if (invalid)
561 continue;
562
563 return opcode;
564 }
565
566 return NULL;
567 }
568
569 /* Print a PowerPC or POWER instruction. */
570
571 static int
572 print_insn_powerpc (bfd_vma memaddr,
573 struct disassemble_info *info,
574 int bigendian,
575 ppc_cpu_t dialect)
576 {
577 bfd_byte buffer[4];
578 int status;
579 unsigned long insn;
580 const struct powerpc_opcode *opcode;
581 bfd_boolean insn_is_short;
582
583 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
584 if (status != 0)
585 {
586 /* The final instruction may be a 2-byte VLE insn. */
587 if ((dialect & PPC_OPCODE_VLE) != 0)
588 {
589 /* Clear buffer so unused bytes will not have garbage in them. */
590 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
591 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
592 if (status != 0)
593 {
594 (*info->memory_error_func) (status, memaddr, info);
595 return -1;
596 }
597 }
598 else
599 {
600 (*info->memory_error_func) (status, memaddr, info);
601 return -1;
602 }
603 }
604
605 if (bigendian)
606 insn = bfd_getb32 (buffer);
607 else
608 insn = bfd_getl32 (buffer);
609
610 /* Get the major opcode of the insn. */
611 opcode = NULL;
612 insn_is_short = FALSE;
613 if ((dialect & PPC_OPCODE_VLE) != 0)
614 {
615 opcode = lookup_vle (insn);
616 if (opcode != NULL)
617 insn_is_short = PPC_OP_SE_VLE(opcode->mask);
618 }
619 if (opcode == NULL)
620 opcode = lookup_powerpc (insn, dialect);
621 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
622 opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
623
624 if (opcode != NULL)
625 {
626 const unsigned char *opindex;
627 const struct powerpc_operand *operand;
628 int need_comma;
629 int need_paren;
630 int skip_optional;
631
632 if (opcode->operands[0] != 0)
633 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
634 else
635 (*info->fprintf_func) (info->stream, "%s", opcode->name);
636
637 if (insn_is_short)
638 /* The operands will be fetched out of the 16-bit instruction. */
639 insn >>= 16;
640
641 /* Now extract and print the operands. */
642 need_comma = 0;
643 need_paren = 0;
644 skip_optional = -1;
645 for (opindex = opcode->operands; *opindex != 0; opindex++)
646 {
647 long value;
648
649 operand = powerpc_operands + *opindex;
650
651 /* Operands that are marked FAKE are simply ignored. We
652 already made sure that the extract function considered
653 the instruction to be valid. */
654 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
655 continue;
656
657 /* If all of the optional operands have the value zero,
658 then don't print any of them. */
659 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
660 {
661 if (skip_optional < 0)
662 skip_optional = skip_optional_operands (opindex, insn,
663 dialect);
664 if (skip_optional)
665 continue;
666 }
667
668 value = operand_value_powerpc (operand, insn, dialect);
669
670 if (need_comma)
671 {
672 (*info->fprintf_func) (info->stream, ",");
673 need_comma = 0;
674 }
675
676 /* Print the operand as directed by the flags. */
677 if ((operand->flags & PPC_OPERAND_GPR) != 0
678 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
679 (*info->fprintf_func) (info->stream, "r%ld", value);
680 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
681 (*info->fprintf_func) (info->stream, "f%ld", value);
682 else if ((operand->flags & PPC_OPERAND_VR) != 0)
683 (*info->fprintf_func) (info->stream, "v%ld", value);
684 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
685 (*info->fprintf_func) (info->stream, "vs%ld", value);
686 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
687 (*info->print_address_func) (memaddr + value, info);
688 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
689 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
690 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
691 (*info->fprintf_func) (info->stream, "fsl%ld", value);
692 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
693 (*info->fprintf_func) (info->stream, "fcr%ld", value);
694 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
695 (*info->fprintf_func) (info->stream, "%ld", value);
696 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
697 && (((dialect & PPC_OPCODE_PPC) != 0)
698 || ((dialect & PPC_OPCODE_VLE) != 0)))
699 (*info->fprintf_func) (info->stream, "cr%ld", value);
700 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
701 && (((dialect & PPC_OPCODE_PPC) != 0)
702 || ((dialect & PPC_OPCODE_VLE) != 0)))
703 {
704 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
705 int cr;
706 int cc;
707
708 cr = value >> 2;
709 if (cr != 0)
710 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
711 cc = value & 3;
712 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
713 }
714 else
715 (*info->fprintf_func) (info->stream, "%d", (int) value);
716
717 if (need_paren)
718 {
719 (*info->fprintf_func) (info->stream, ")");
720 need_paren = 0;
721 }
722
723 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
724 need_comma = 1;
725 else
726 {
727 (*info->fprintf_func) (info->stream, "(");
728 need_paren = 1;
729 }
730 }
731
732 /* We have found and printed an instruction.
733 If it was a short VLE instruction we have more to do. */
734 if (insn_is_short)
735 {
736 memaddr += 2;
737 return 2;
738 }
739 else
740 /* Otherwise, return. */
741 return 4;
742 }
743
744 /* We could not find a match. */
745 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
746
747 return 4;
748 }
749
750 void
751 print_ppc_disassembler_options (FILE *stream)
752 {
753 unsigned int i, col;
754
755 fprintf (stream, _("\n\
756 The following PPC specific disassembler options are supported for use with\n\
757 the -M switch:\n"));
758
759 for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
760 {
761 col += fprintf (stream, " %s,", ppc_opts[i].opt);
762 if (col > 66)
763 {
764 fprintf (stream, "\n");
765 col = 0;
766 }
767 }
768 fprintf (stream, " 32, 64\n");
769 }
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