opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2020 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "disassemble.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29 #include "libiberty.h"
  30
  31 /* This file provides several disassembler functions, all of which use
  32    the disassembler interface defined in dis-asm.h.  Several functions
  33    are provided because this file handles disassembly for the PowerPC
  34    in both big and little endian mode and also for the POWER (RS/6000)
  35    chip.  */
  36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  37                                ppc_cpu_t);
  38
  39 struct dis_private
  40 {
  41   /* Stash the result of parsing disassembler_options here.  */
  42   ppc_cpu_t dialect;
  43 };
  44
  45 #define POWERPC_DIALECT(INFO) \
  46   (((struct dis_private *) ((INFO)->private_data))->dialect)
  47
  48 struct ppc_mopt {
  49   /* Option string, without -m or -M prefix.  */
  50   const char *opt;
  51   /* CPU option flags.  */
  52   ppc_cpu_t cpu;
  53   /* Flags that should stay on, even when combined with another cpu
  54      option.  This should only be used for generic options like
  55      "-many" or "-maltivec" where it is reasonable to add some
  56      capability to another cpu selection.  The added flags are sticky
  57      so that, for example, "-many -me500" and "-me500 -many" result in
  58      the same assembler or disassembler behaviour.  Do not use
  59      "sticky" for specific cpus, as this will prevent that cpu's flags
  60      from overriding the defaults set in powerpc_init_dialect or a
  61      prior -m option.  */
  62   ppc_cpu_t sticky;
  63 };
  64
  65 struct ppc_mopt ppc_opts[] = {
  66   { "403",     PPC_OPCODE_PPC | PPC_OPCODE_403,
  67     0 },
  68   { "405",     PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
  69     0 },
  70   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  71                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  72     0 },
  73   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  74                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  75     0 },
  76   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
  77                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  78     0 },
  79   { "601",     PPC_OPCODE_PPC | PPC_OPCODE_601,
  80     0 },
  81   { "603",     PPC_OPCODE_PPC,
  82     0 },
  83   { "604",     PPC_OPCODE_PPC,
  84     0 },
  85   { "620",     PPC_OPCODE_PPC | PPC_OPCODE_64,
  86     0 },
  87   { "7400",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  88     0 },
  89   { "7410",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  90     0 },
  91   { "7450",    PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
  92     0 },
  93   { "7455",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  94     0 },
  95   { "750cl",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  96     , 0 },
  97   { "gekko",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  98     , 0 },
  99   { "broadway", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
 100     , 0 },
 101   { "821",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 102     0 },
 103   { "850",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 104     0 },
 105   { "860",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 106     0 },
 107   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
 108                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
 109                 | PPC_OPCODE_A2),
 110     0 },
 111   { "altivec", PPC_OPCODE_PPC,
 112     PPC_OPCODE_ALTIVEC },
 113   { "any",     PPC_OPCODE_PPC,
 114     PPC_OPCODE_ANY },
 115   { "booke",   PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 116     0 },
 117   { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 118     0 },
 119   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 120                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 121     0 },
 122   { "com",     PPC_OPCODE_COMMON,
 123     0 },
 124   { "e200z4",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 125                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 126                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 127                 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
 128                 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
 129     0 },
 130   { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
 131     0 },
 132   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 133                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 134                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 135                 | PPC_OPCODE_E500),
 136     0 },
 137   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 138                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 139                 | PPC_OPCODE_E500MC),
 140     0 },
 141   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 142                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 143                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 144                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 145     0 },
 146   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 147                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 148                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 149                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 150     0 },
 151   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 152                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 153                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 154                 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
 155                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 156     0 },
 157   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 158                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 159                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 160                 | PPC_OPCODE_E500),
 161     0 },
 162   { "efs",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 163     0 },
 164   { "efs2",    PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
 165     0 },
 166   { "power4",  PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 167     0 },
 168   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 169                 | PPC_OPCODE_POWER5),
 170     0 },
 171   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 172                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 173     0 },
 174   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 175                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 176                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 177     0 },
 178   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 179                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 180                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 181                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 182     0 },
 183   { "power9",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 184                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 185                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 186                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 187     0 },
 188   { "power10", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 189                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 190                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 191                 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 192     0 },
 193   { "future",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 194                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 195                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 196                 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 197     0 },
 198   { "ppc",     PPC_OPCODE_PPC,
 199     0 },
 200   { "ppc32",   PPC_OPCODE_PPC,
 201     0 },
 202   { "32",      PPC_OPCODE_PPC,
 203     0 },
 204   { "ppc64",   PPC_OPCODE_PPC | PPC_OPCODE_64,
 205     0 },
 206   { "64",      PPC_OPCODE_PPC | PPC_OPCODE_64,
 207     0 },
 208   { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
 209     0 },
 210   { "ppcps",   PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
 211     0 },
 212   { "pwr",     PPC_OPCODE_POWER,
 213     0 },
 214   { "pwr2",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 215     0 },
 216   { "pwr4",    PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 217     0 },
 218   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 219                 | PPC_OPCODE_POWER5),
 220     0 },
 221   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 222                 | PPC_OPCODE_POWER5),
 223     0 },
 224   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 225                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 226     0 },
 227   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 228                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 229                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 230     0 },
 231   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 232                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 233                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 234                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 235     0 },
 236   { "pwr9",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 237                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 238                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 239                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 240     0 },
 241   { "pwr10",   (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 242                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 243                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 244                 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 245     0 },
 246   { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 247     0 },
 248   { "raw",     PPC_OPCODE_PPC,
 249     PPC_OPCODE_RAW },
 250   { "spe",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 251     PPC_OPCODE_SPE },
 252   { "spe2",     PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
 253     PPC_OPCODE_SPE2 },
 254   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 255                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 256     0 },
 257   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 258                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 259                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 260                 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
 261     PPC_OPCODE_VLE },
 262   { "vsx",     PPC_OPCODE_PPC,
 263     PPC_OPCODE_VSX },
 264 };
 265
 266 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 267 static ppc_cpu_t
 268 get_powerpc_dialect (struct disassemble_info *info)
 269 {
 270   ppc_cpu_t dialect = 0;
 271
 272   if (info->private_data)
 273     dialect = POWERPC_DIALECT (info);
 274
 275   /* Disassemble according to the section headers flags for VLE-mode.  */
 276   if (dialect & PPC_OPCODE_VLE
 277       && info->section != NULL && info->section->owner != NULL
 278       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 279       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 280       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 281     return dialect;
 282   else
 283     return dialect & ~ PPC_OPCODE_VLE;
 284 }
 285
 286 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 287
 288 ppc_cpu_t
 289 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 290 {
 291   unsigned int i;
 292
 293   for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 294     if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
 295       {
 296         if (ppc_opts[i].sticky)
 297           {
 298             *sticky |= ppc_opts[i].sticky;
 299             if ((ppc_cpu & ~*sticky) != 0)
 300               break;
 301           }
 302         ppc_cpu = ppc_opts[i].cpu;
 303         break;
 304       }
 305   if (i >= ARRAY_SIZE (ppc_opts))
 306     return 0;
 307
 308   ppc_cpu |= *sticky;
 309   return ppc_cpu;
 310 }
 311
 312 /* Determine which set of machines to disassemble for.  */
 313
 314 static void
 315 powerpc_init_dialect (struct disassemble_info *info)
 316 {
 317   ppc_cpu_t dialect = 0;
 318   ppc_cpu_t sticky = 0;
 319   struct dis_private *priv = calloc (sizeof (*priv), 1);
 320
 321   if (priv == NULL)
 322     return;
 323
 324   switch (info->mach)
 325     {
 326     case bfd_mach_ppc_403:
 327     case bfd_mach_ppc_403gc:
 328       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 329       break;
 330     case bfd_mach_ppc_405:
 331       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 332       break;
 333     case bfd_mach_ppc_601:
 334       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 335       break;
 336     case bfd_mach_ppc_750:
 337       dialect = ppc_parse_cpu (dialect, &sticky, "750cl");
 338       break;
 339     case bfd_mach_ppc_a35:
 340     case bfd_mach_ppc_rs64ii:
 341     case bfd_mach_ppc_rs64iii:
 342       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 343       break;
 344     case bfd_mach_ppc_e500:
 345       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 346       break;
 347     case bfd_mach_ppc_e500mc:
 348       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 349       break;
 350     case bfd_mach_ppc_e500mc64:
 351       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 352       break;
 353     case bfd_mach_ppc_e5500:
 354       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 355       break;
 356     case bfd_mach_ppc_e6500:
 357       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 358       break;
 359     case bfd_mach_ppc_titan:
 360       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 361       break;
 362     case bfd_mach_ppc_vle:
 363       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 364       break;
 365     default:
 366       if (info->arch == bfd_arch_powerpc)
 367         dialect = ppc_parse_cpu (dialect, &sticky, "power10") | PPC_OPCODE_ANY;
 368       else
 369         dialect = ppc_parse_cpu (dialect, &sticky, "pwr");
 370       break;
 371     }
 372
 373   const char *opt;
 374   FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
 375     {
 376       ppc_cpu_t new_cpu = 0;
 377
 378       if (disassembler_options_cmp (opt, "32") == 0)
 379         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 380       else if (disassembler_options_cmp (opt, "64") == 0)
 381         dialect |= PPC_OPCODE_64;
 382       else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
 383         dialect = new_cpu;
 384       else
 385         /* xgettext: c-format */
 386         opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt);
 387     }
 388
 389   info->private_data = priv;
 390   POWERPC_DIALECT(info) = dialect;
 391 }
 392
 393 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
 394 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
 395 #define PREFIX_OPCD_SEGS (1 + PPC_PREFIX_SEG (-1))
 396 static unsigned short prefix_opcd_indices[PREFIX_OPCD_SEGS + 1];
 397 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
 398 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
 399 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
 400 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
 401
 402 /* Calculate opcode table indices to speed up disassembly,
 403    and init dialect.  */
 404
 405 void
 406 disassemble_init_powerpc (struct disassemble_info *info)
 407 {
 408   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 409     {
 410       unsigned seg, idx, op;
 411
 412       /* PPC opcodes */
 413       for (seg = 0, idx = 0; seg <= PPC_OPCD_SEGS; seg++)
 414         {
 415           powerpc_opcd_indices[seg] = idx;
 416           for (; idx < powerpc_num_opcodes; idx++)
 417             if (seg < PPC_OP (powerpc_opcodes[idx].opcode))
 418               break;
 419         }
 420
 421       /* 64-bit prefix opcodes */
 422       for (seg = 0, idx = 0; seg <= PREFIX_OPCD_SEGS; seg++)
 423         {
 424           prefix_opcd_indices[seg] = idx;
 425           for (; idx < prefix_num_opcodes; idx++)
 426             if (seg < PPC_PREFIX_SEG (prefix_opcodes[idx].opcode))
 427               break;
 428         }
 429
 430       /* VLE opcodes */
 431       for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++)
 432         {
 433           vle_opcd_indices[seg] = idx;
 434           for (; idx < vle_num_opcodes; idx++)
 435             {
 436               op = VLE_OP (vle_opcodes[idx].opcode, vle_opcodes[idx].mask);
 437               if (seg < VLE_OP_TO_SEG (op))
 438                 break;
 439             }
 440         }
 441
 442       /* SPE2 opcodes */
 443       for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)
 444         {
 445           spe2_opcd_indices[seg] = idx;
 446           for (; idx < spe2_num_opcodes; idx++)
 447             {
 448               op = SPE2_XOP (spe2_opcodes[idx].opcode);
 449               if (seg < SPE2_XOP_TO_SEG (op))
 450                 break;
 451             }
 452         }
 453     }
 454
 455   powerpc_init_dialect (info);
 456 }
 457
 458 /* Print a big endian PowerPC instruction.  */
 459
 460 int
 461 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 462 {
 463   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 464 }
 465
 466 /* Print a little endian PowerPC instruction.  */
 467
 468 int
 469 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 470 {
 471   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 472 }
 473
 474 /* Extract the operand value from the PowerPC or POWER instruction.  */
 475
 476 static int64_t
 477 operand_value_powerpc (const struct powerpc_operand *operand,
 478                        uint64_t insn, ppc_cpu_t dialect)
 479 {
 480   int64_t value;
 481   int invalid = 0;
 482   /* Extract the value from the instruction.  */
 483   if (operand->extract)
 484     value = (*operand->extract) (insn, dialect, &invalid);
 485   else
 486     {
 487       if (operand->shift >= 0)
 488         value = (insn >> operand->shift) & operand->bitm;
 489       else
 490         value = (insn << -operand->shift) & operand->bitm;
 491       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 492         {
 493           /* BITM is always some number of zeros followed by some
 494              number of ones, followed by some number of zeros.  */
 495           uint64_t top = operand->bitm;
 496           /* top & -top gives the rightmost 1 bit, so this
 497              fills in any trailing zeros.  */
 498           top |= (top & -top) - 1;
 499           top &= ~(top >> 1);
 500           value = (value ^ top) - top;
 501         }
 502     }
 503
 504   return value;
 505 }
 506
 507 /* Determine whether the optional operand(s) should be printed.  */
 508
 509 static bfd_boolean
 510 skip_optional_operands (const unsigned char *opindex,
 511                         uint64_t insn, ppc_cpu_t dialect)
 512 {
 513   const struct powerpc_operand *operand;
 514   int num_optional;
 515
 516   for (num_optional = 0; *opindex != 0; opindex++)
 517     {
 518       operand = &powerpc_operands[*opindex];
 519       if ((operand->flags & PPC_OPERAND_NEXT) != 0)
 520         return FALSE;
 521       if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 522         {
 523           /* Negative count is used as a flag to extract function.  */
 524           --num_optional;
 525           if (operand_value_powerpc (operand, insn, dialect)
 526               != ppc_optional_operand_value (operand, insn, dialect,
 527                                              num_optional))
 528             return FALSE;
 529         }
 530     }
 531
 532   return TRUE;
 533 }
 534
 535 /* Find a match for INSN in the opcode table, given machine DIALECT.  */
 536
 537 static const struct powerpc_opcode *
 538 lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
 539 {
 540   const struct powerpc_opcode *opcode, *opcode_end, *last;
 541   unsigned long op;
 542
 543   /* Get the major opcode of the instruction.  */
 544   op = PPC_OP (insn);
 545
 546   /* Find the first match in the opcode table for this major opcode.  */
 547   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 548   last = NULL;
 549   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 550        opcode < opcode_end;
 551        ++opcode)
 552     {
 553       const unsigned char *opindex;
 554       const struct powerpc_operand *operand;
 555       int invalid;
 556
 557       if ((insn & opcode->mask) != opcode->opcode
 558           || ((dialect & PPC_OPCODE_ANY) == 0
 559               && ((opcode->flags & dialect) == 0
 560                   || (opcode->deprecated & dialect) != 0)))
 561         continue;
 562
 563       /* Check validity of operands.  */
 564       invalid = 0;
 565       for (opindex = opcode->operands; *opindex != 0; opindex++)
 566         {
 567           operand = powerpc_operands + *opindex;
 568           if (operand->extract)
 569             (*operand->extract) (insn, dialect, &invalid);
 570         }
 571       if (invalid)
 572         continue;
 573
 574       if ((dialect & PPC_OPCODE_RAW) == 0)
 575         return opcode;
 576
 577       /* The raw machine insn is one that is not a specialization.  */
 578       if (last == NULL
 579           || (last->mask & ~opcode->mask) != 0)
 580         last = opcode;
 581     }
 582
 583   return last;
 584 }
 585
 586 /* Find a match for INSN in the PREFIX opcode table.  */
 587
 588 static const struct powerpc_opcode *
 589 lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
 590 {
 591   const struct powerpc_opcode *opcode, *opcode_end, *last;
 592   unsigned long seg;
 593
 594   /* Get the opcode segment of the instruction.  */
 595   seg = PPC_PREFIX_SEG (insn);
 596
 597   /* Find the first match in the opcode table for this major opcode.  */
 598   opcode_end = prefix_opcodes + prefix_opcd_indices[seg + 1];
 599   last = NULL;
 600   for (opcode = prefix_opcodes + prefix_opcd_indices[seg];
 601        opcode < opcode_end;
 602        ++opcode)
 603     {
 604       const unsigned char *opindex;
 605       const struct powerpc_operand *operand;
 606       int invalid;
 607
 608       if ((insn & opcode->mask) != opcode->opcode
 609           || ((dialect & PPC_OPCODE_ANY) == 0
 610               && ((opcode->flags & dialect) == 0
 611                   || (opcode->deprecated & dialect) != 0)))
 612         continue;
 613
 614       /* Check validity of operands.  */
 615       invalid = 0;
 616       for (opindex = opcode->operands; *opindex != 0; opindex++)
 617         {
 618           operand = powerpc_operands + *opindex;
 619           if (operand->extract)
 620             (*operand->extract) (insn, dialect, &invalid);
 621         }
 622       if (invalid)
 623         continue;
 624
 625       if ((dialect & PPC_OPCODE_RAW) == 0)
 626         return opcode;
 627
 628       /* The raw machine insn is one that is not a specialization.  */
 629       if (last == NULL
 630           || (last->mask & ~opcode->mask) != 0)
 631         last = opcode;
 632     }
 633
 634   return last;
 635 }
 636
 637 /* Find a match for INSN in the VLE opcode table.  */
 638
 639 static const struct powerpc_opcode *
 640 lookup_vle (uint64_t insn)
 641 {
 642   const struct powerpc_opcode *opcode;
 643   const struct powerpc_opcode *opcode_end;
 644   unsigned op, seg;
 645
 646   op = PPC_OP (insn);
 647   if (op >= 0x20 && op <= 0x37)
 648     {
 649       /* This insn has a 4-bit opcode.  */
 650       op &= 0x3c;
 651     }
 652   seg = VLE_OP_TO_SEG (op);
 653
 654   /* Find the first match in the opcode table for this major opcode.  */
 655   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 656   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 657        opcode < opcode_end;
 658        ++opcode)
 659     {
 660       uint64_t table_opcd = opcode->opcode;
 661       uint64_t table_mask = opcode->mask;
 662       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 663       uint64_t insn2;
 664       const unsigned char *opindex;
 665       const struct powerpc_operand *operand;
 666       int invalid;
 667
 668       insn2 = insn;
 669       if (table_op_is_short)
 670         insn2 >>= 16;
 671       if ((insn2 & table_mask) != table_opcd)
 672         continue;
 673
 674       /* Check validity of operands.  */
 675       invalid = 0;
 676       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 677         {
 678           operand = powerpc_operands + *opindex;
 679           if (operand->extract)
 680             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 681         }
 682       if (invalid)
 683         continue;
 684
 685       return opcode;
 686     }
 687
 688   return NULL;
 689 }
 690
 691 /* Find a match for INSN in the SPE2 opcode table.  */
 692
 693 static const struct powerpc_opcode *
 694 lookup_spe2 (uint64_t insn)
 695 {
 696   const struct powerpc_opcode *opcode, *opcode_end;
 697   unsigned op, xop, seg;
 698
 699   op = PPC_OP (insn);
 700   if (op != 0x4)
 701     {
 702       /* This is not SPE2 insn.
 703        * All SPE2 instructions have OP=4 and differs by XOP  */
 704       return NULL;
 705     }
 706   xop = SPE2_XOP (insn);
 707   seg = SPE2_XOP_TO_SEG (xop);
 708
 709   /* Find the first match in the opcode table for this major opcode.  */
 710   opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
 711   for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
 712        opcode < opcode_end;
 713        ++opcode)
 714     {
 715       uint64_t table_opcd = opcode->opcode;
 716       uint64_t table_mask = opcode->mask;
 717       uint64_t insn2;
 718       const unsigned char *opindex;
 719       const struct powerpc_operand *operand;
 720       int invalid;
 721
 722       insn2 = insn;
 723       if ((insn2 & table_mask) != table_opcd)
 724         continue;
 725
 726       /* Check validity of operands.  */
 727       invalid = 0;
 728       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 729         {
 730           operand = powerpc_operands + *opindex;
 731           if (operand->extract)
 732             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 733         }
 734       if (invalid)
 735         continue;
 736
 737       return opcode;
 738     }
 739
 740   return NULL;
 741 }
 742
 743 /* Print a PowerPC or POWER instruction.  */
 744
 745 static int
 746 print_insn_powerpc (bfd_vma memaddr,
 747                     struct disassemble_info *info,
 748                     int bigendian,
 749                     ppc_cpu_t dialect)
 750 {
 751   bfd_byte buffer[4];
 752   int status;
 753   uint64_t insn;
 754   const struct powerpc_opcode *opcode;
 755   int insn_length = 4;  /* Assume we have a normal 4-byte instruction.  */
 756
 757   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 758
 759   /* The final instruction may be a 2-byte VLE insn.  */
 760   if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0)
 761     {
 762       /* Clear buffer so unused bytes will not have garbage in them.  */
 763       buffer[2] = buffer[3] = 0;
 764       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 765       insn_length = 2;
 766     }
 767
 768   if (status != 0)
 769     {
 770       (*info->memory_error_func) (status, memaddr, info);
 771       return -1;
 772     }
 773
 774   if (bigendian)
 775     insn = bfd_getb32 (buffer);
 776   else
 777     insn = bfd_getl32 (buffer);
 778
 779   /* Get the major opcode of the insn.  */
 780   opcode = NULL;
 781   if ((dialect & PPC_OPCODE_POWER10) != 0
 782       && PPC_OP (insn) == 0x1)
 783     {
 784       uint64_t temp_insn, suffix;
 785       status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
 786       if (status == 0)
 787         {
 788           if (bigendian)
 789             suffix = bfd_getb32 (buffer);
 790           else
 791             suffix = bfd_getl32 (buffer);
 792           temp_insn = (insn << 32) | suffix;
 793           opcode = lookup_prefix (temp_insn, dialect & ~PPC_OPCODE_ANY);
 794           if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 795             opcode = lookup_prefix (temp_insn, dialect);
 796           if (opcode != NULL)
 797             {
 798               insn = temp_insn;
 799               insn_length = 8;
 800               if ((info->flags & WIDE_OUTPUT) != 0)
 801                 info->bytes_per_line = 8;
 802             }
 803         }
 804     }
 805   if (opcode == NULL && (dialect & PPC_OPCODE_VLE) != 0)
 806     {
 807       opcode = lookup_vle (insn);
 808       if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
 809         {
 810           /* The operands will be fetched out of the 16-bit instruction.  */
 811           insn >>= 16;
 812           insn_length = 2;
 813         }
 814     }
 815   if (opcode == NULL && insn_length == 4)
 816     {
 817       if ((dialect & PPC_OPCODE_SPE2) != 0)
 818         opcode = lookup_spe2 (insn);
 819       if (opcode == NULL)
 820         opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
 821       if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 822         opcode = lookup_powerpc (insn, dialect);
 823     }
 824
 825   if (opcode != NULL)
 826     {
 827       const unsigned char *opindex;
 828       const struct powerpc_operand *operand;
 829       enum {
 830         need_comma = 0,
 831         need_1space = 1,
 832         need_2spaces = 2,
 833         need_3spaces = 3,
 834         need_4spaces = 4,
 835         need_5spaces = 5,
 836         need_6spaces = 6,
 837         need_7spaces = 7,
 838         need_paren
 839       } op_separator;
 840       bfd_boolean skip_optional;
 841       int blanks;
 842
 843       (*info->fprintf_func) (info->stream, "%s", opcode->name);
 844       /* gdb fprintf_func doesn't return count printed.  */
 845       blanks = 8 - strlen (opcode->name);
 846       if (blanks <= 0)
 847         blanks = 1;
 848
 849       /* Now extract and print the operands.  */
 850       op_separator = blanks;
 851       skip_optional = FALSE;
 852       for (opindex = opcode->operands; *opindex != 0; opindex++)
 853         {
 854           int64_t value;
 855
 856           operand = powerpc_operands + *opindex;
 857
 858           /* If all of the optional operands past this one have their
 859              default value, then don't print any of them.  Except in
 860              raw mode, print them all.  */
 861           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 862               && (dialect & PPC_OPCODE_RAW) == 0)
 863             {
 864               if (!skip_optional)
 865                 skip_optional = skip_optional_operands (opindex, insn, dialect);
 866               if (skip_optional)
 867                 continue;
 868             }
 869
 870           value = operand_value_powerpc (operand, insn, dialect);
 871
 872           if (op_separator == need_comma)
 873             (*info->fprintf_func) (info->stream, ",");
 874           else if (op_separator == need_paren)
 875             (*info->fprintf_func) (info->stream, "(");
 876           else
 877             (*info->fprintf_func) (info->stream, "%*s", op_separator, " ");
 878
 879           /* Print the operand as directed by the flags.  */
 880           if ((operand->flags & PPC_OPERAND_GPR) != 0
 881               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 882             (*info->fprintf_func) (info->stream, "r%" PRId64, value);
 883           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 884             (*info->fprintf_func) (info->stream, "f%" PRId64, value);
 885           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 886             (*info->fprintf_func) (info->stream, "v%" PRId64, value);
 887           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 888             (*info->fprintf_func) (info->stream, "vs%" PRId64, value);
 889           else if ((operand->flags & PPC_OPERAND_ACC) != 0)
 890             (*info->fprintf_func) (info->stream, "a%" PRId64, value);
 891           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 892             (*info->print_address_func) (memaddr + value, info);
 893           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 894             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 895           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 896             (*info->fprintf_func) (info->stream, "fsl%" PRId64, value);
 897           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 898             (*info->fprintf_func) (info->stream, "fcr%" PRId64, value);
 899           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 900             (*info->fprintf_func) (info->stream, "%" PRId64, value);
 901           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 902                    && (operand->flags & PPC_OPERAND_CR_BIT) == 0
 903                    && (((dialect & PPC_OPCODE_PPC) != 0)
 904                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 905             (*info->fprintf_func) (info->stream, "cr%" PRId64, value);
 906           else if ((operand->flags & PPC_OPERAND_CR_BIT) != 0
 907                    && (operand->flags & PPC_OPERAND_CR_REG) == 0
 908                    && (((dialect & PPC_OPCODE_PPC) != 0)
 909                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 910             {
 911               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 912               int cr;
 913               int cc;
 914
 915               cr = value >> 2;
 916               if (cr != 0)
 917                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 918               cc = value & 3;
 919               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 920             }
 921           else
 922             (*info->fprintf_func) (info->stream, "%" PRId64, value);
 923
 924           if (op_separator == need_paren)
 925             (*info->fprintf_func) (info->stream, ")");
 926
 927           op_separator = need_comma;
 928           if ((operand->flags & PPC_OPERAND_PARENS) != 0)
 929             op_separator = need_paren;
 930         }
 931
 932       /* We have found and printed an instruction.  */
 933       return insn_length;
 934     }
 935
 936   /* We could not find a match.  */
 937   if (insn_length == 4)
 938     (*info->fprintf_func) (info->stream, ".long 0x%x",
 939                            (unsigned int) insn);
 940   else
 941     (*info->fprintf_func) (info->stream, ".word 0x%x",
 942                            (unsigned int) insn >> 16);
 943   return insn_length;
 944 }
 945
 946 const disasm_options_and_args_t *
 947 disassembler_options_powerpc (void)
 948 {
 949   static disasm_options_and_args_t *opts_and_args;
 950
 951   if (opts_and_args == NULL)
 952     {
 953       size_t i, num_options = ARRAY_SIZE (ppc_opts);
 954       disasm_options_t *opts;
 955
 956       opts_and_args = XNEW (disasm_options_and_args_t);
 957       opts_and_args->args = NULL;
 958
 959       opts = &opts_and_args->options;
 960       opts->name = XNEWVEC (const char *, num_options + 1);
 961       opts->description = NULL;
 962       opts->arg = NULL;
 963       for (i = 0; i < num_options; i++)
 964         opts->name[i] = ppc_opts[i].opt;
 965       /* The array we return must be NULL terminated.  */
 966       opts->name[i] = NULL;
 967     }
 968
 969   return opts_and_args;
 970 }
 971
 972 void
 973 print_ppc_disassembler_options (FILE *stream)
 974 {
 975   unsigned int i, col;
 976
 977   fprintf (stream, _("\n\
 978 The following PPC specific disassembler options are supported for use with\n\
 979 the -M switch:\n"));
 980
 981   for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 982     {
 983       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 984       if (col > 66)
 985         {
 986           fprintf (stream, "\n");
 987           col = 0;
 988         }
 989     }
 990   fprintf (stream, "\n");
 991 }