1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "opcode/ppc.h"
27 /* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
38 /* The functions used to insert and extract complicated operands. */
40 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
43 insert_arx (unsigned long insn
,
45 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
46 const char **errmsg ATTRIBUTE_UNUSED
)
48 if (value
>= 8 && value
< 24)
49 return insn
| ((value
- 8) & 0xf);
52 *errmsg
= _("invalid register");
58 extract_arx (unsigned long insn
,
59 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
60 int *invalid ATTRIBUTE_UNUSED
)
62 return (insn
& 0xf) + 8;
66 insert_ary (unsigned long insn
,
68 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
69 const char **errmsg ATTRIBUTE_UNUSED
)
71 if (value
>= 8 && value
< 24)
72 return insn
| (((value
- 8) & 0xf) << 4);
75 *errmsg
= _("invalid register");
81 extract_ary (unsigned long insn
,
82 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
83 int *invalid ATTRIBUTE_UNUSED
)
85 return ((insn
>> 4) & 0xf) + 8;
89 insert_rx (unsigned long insn
,
91 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
94 if (value
>= 0 && value
< 8)
96 else if (value
>= 24 && value
<= 31)
97 return insn
| (value
- 16);
100 *errmsg
= _("invalid register");
106 extract_rx (unsigned long insn
,
107 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
108 int *invalid ATTRIBUTE_UNUSED
)
110 int value
= insn
& 0xf;
111 if (value
>= 0 && value
< 8)
118 insert_ry (unsigned long insn
,
120 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
123 if (value
>= 0 && value
< 8)
124 return insn
| (value
<< 4);
125 else if (value
>= 24 && value
<= 31)
126 return insn
| ((value
- 16) << 4);
129 *errmsg
= _("invalid register");
135 extract_ry (unsigned long insn
,
136 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
137 int *invalid ATTRIBUTE_UNUSED
)
139 int value
= (insn
>> 4) & 0xf;
140 if (value
>= 0 && value
< 8)
146 /* The BA field in an XL form instruction when it must be the same as
147 the BT field in the same instruction. This operand is marked FAKE.
148 The insertion function just copies the BT field into the BA field,
149 and the extraction function just checks that the fields are the
153 insert_bat (unsigned long insn
,
154 long value ATTRIBUTE_UNUSED
,
155 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
156 const char **errmsg ATTRIBUTE_UNUSED
)
158 return insn
| (((insn
>> 21) & 0x1f) << 16);
162 extract_bat (unsigned long insn
,
163 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
166 if (((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
171 /* The BB field in an XL form instruction when it must be the same as
172 the BA field in the same instruction. This operand is marked FAKE.
173 The insertion function just copies the BA field into the BB field,
174 and the extraction function just checks that the fields are the
178 insert_bba (unsigned long insn
,
179 long value ATTRIBUTE_UNUSED
,
180 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
181 const char **errmsg ATTRIBUTE_UNUSED
)
183 return insn
| (((insn
>> 16) & 0x1f) << 11);
187 extract_bba (unsigned long insn
,
188 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
191 if (((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
196 /* The BD field in a B form instruction when the - modifier is used.
197 This modifier means that the branch is not expected to be taken.
198 For chips built to versions of the architecture prior to version 2
199 (ie. not Power4 compatible), we set the y bit of the BO field to 1
200 if the offset is negative. When extracting, we require that the y
201 bit be 1 and that the offset be positive, since if the y bit is 0
202 we just want to print the normal form of the instruction.
203 Power4 compatible targets use two bits, "a", and "t", instead of
204 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
205 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
206 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
207 for branch on CTR. We only handle the taken/not-taken hint here.
208 Note that we don't relax the conditions tested here when
209 disassembling with -Many because insns using extract_bdm and
210 extract_bdp always occur in pairs. One or the other will always
213 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
216 insert_bdm (unsigned long insn
,
219 const char **errmsg ATTRIBUTE_UNUSED
)
221 if ((dialect
& ISA_V2
) == 0)
223 if ((value
& 0x8000) != 0)
228 if ((insn
& (0x14 << 21)) == (0x04 << 21))
230 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
233 return insn
| (value
& 0xfffc);
237 extract_bdm (unsigned long insn
,
241 if ((dialect
& ISA_V2
) == 0)
243 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
248 if ((insn
& (0x17 << 21)) != (0x06 << 21)
249 && (insn
& (0x1d << 21)) != (0x18 << 21))
253 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
256 /* The BD field in a B form instruction when the + modifier is used.
257 This is like BDM, above, except that the branch is expected to be
261 insert_bdp (unsigned long insn
,
264 const char **errmsg ATTRIBUTE_UNUSED
)
266 if ((dialect
& ISA_V2
) == 0)
268 if ((value
& 0x8000) == 0)
273 if ((insn
& (0x14 << 21)) == (0x04 << 21))
275 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
278 return insn
| (value
& 0xfffc);
282 extract_bdp (unsigned long insn
,
286 if ((dialect
& ISA_V2
) == 0)
288 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
293 if ((insn
& (0x17 << 21)) != (0x07 << 21)
294 && (insn
& (0x1d << 21)) != (0x19 << 21))
298 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
302 valid_bo_pre_v2 (long value
)
304 /* Certain encodings have bits that are required to be zero.
305 These are (z must be zero, y may be anything):
316 if ((value
& 0x14) == 0)
318 else if ((value
& 0x14) == 0x4)
319 return (value
& 0x2) == 0;
320 else if ((value
& 0x14) == 0x10)
321 return (value
& 0x8) == 0;
323 return value
== 0x14;
327 valid_bo_post_v2 (long value
)
329 /* Certain encodings have bits that are required to be zero.
330 These are (z must be zero, a & t may be anything):
341 if ((value
& 0x14) == 0)
342 return (value
& 0x1) == 0;
343 else if ((value
& 0x14) == 0x14)
344 return value
== 0x14;
349 /* Check for legal values of a BO field. */
352 valid_bo (long value
, ppc_cpu_t dialect
, int extract
)
354 int valid_y
= valid_bo_pre_v2 (value
);
355 int valid_at
= valid_bo_post_v2 (value
);
357 /* When disassembling with -Many, accept either encoding on the
358 second pass through opcodes. */
359 if (extract
&& dialect
== ~(ppc_cpu_t
) PPC_OPCODE_ANY
)
360 return valid_y
|| valid_at
;
361 if ((dialect
& ISA_V2
) == 0)
367 /* The BO field in a B form instruction. Warn about attempts to set
368 the field to an illegal value. */
371 insert_bo (unsigned long insn
,
376 if (!valid_bo (value
, dialect
, 0))
377 *errmsg
= _("invalid conditional option");
378 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
379 *errmsg
= _("invalid counter access");
380 return insn
| ((value
& 0x1f) << 21);
384 extract_bo (unsigned long insn
,
390 value
= (insn
>> 21) & 0x1f;
391 if (!valid_bo (value
, dialect
, 1))
396 /* The BO field in a B form instruction when the + or - modifier is
397 used. This is like the BO field, but it must be even. When
398 extracting it, we force it to be even. */
401 insert_boe (unsigned long insn
,
406 if (!valid_bo (value
, dialect
, 0))
407 *errmsg
= _("invalid conditional option");
408 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
409 *errmsg
= _("invalid counter access");
410 else if ((value
& 1) != 0)
411 *errmsg
= _("attempt to set y bit when using + or - modifier");
413 return insn
| ((value
& 0x1f) << 21);
417 extract_boe (unsigned long insn
,
423 value
= (insn
>> 21) & 0x1f;
424 if (!valid_bo (value
, dialect
, 1))
429 /* The DCMX field in a X form instruction when the field is split
430 into separate DC, DM and DX fields. */
433 insert_dcmxs (unsigned long insn
,
435 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
436 const char **errmsg ATTRIBUTE_UNUSED
)
439 | ((value
& 0x1f) << 16)
440 | ((value
& 0x20) >> 3)
445 extract_dcmxs (unsigned long insn
,
446 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
447 int *invalid ATTRIBUTE_UNUSED
)
449 return (insn
& 0x40) | ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
452 /* The D field in a DX form instruction when the field is split
453 into separate D0, D1 and D2 fields. */
456 insert_dxd (unsigned long insn
,
458 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
459 const char **errmsg ATTRIBUTE_UNUSED
)
461 return insn
| (value
& 0xffc1) | ((value
& 0x3e) << 15);
465 extract_dxd (unsigned long insn
,
466 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
467 int *invalid ATTRIBUTE_UNUSED
)
469 unsigned long dxd
= (insn
& 0xffc1) | ((insn
>> 15) & 0x3e);
470 return (dxd
^ 0x8000) - 0x8000;
474 insert_dxdn (unsigned long insn
,
476 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
477 const char **errmsg ATTRIBUTE_UNUSED
)
479 return insert_dxd (insn
, -value
, dialect
, errmsg
);
483 extract_dxdn (unsigned long insn
,
484 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
485 int *invalid ATTRIBUTE_UNUSED
)
487 return -extract_dxd (insn
, dialect
, invalid
);
490 /* FXM mask in mfcr and mtcrf instructions. */
493 insert_fxm (unsigned long insn
,
498 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
499 one bit of the mask field is set. */
500 if ((insn
& (1 << 20)) != 0)
502 if (value
== 0 || (value
& -value
) != value
)
504 *errmsg
= _("invalid mask field");
509 /* If only one bit of the FXM field is set, we can use the new form
510 of the instruction, which is faster. Unlike the Power4 branch hint
511 encoding, this is not backward compatible. Do not generate the
512 new form unless -mpower4 has been given, or -many and the two
513 operand form of mfcr was used. */
515 && (value
& -value
) == value
516 && ((dialect
& PPC_OPCODE_POWER4
) != 0
517 || ((dialect
& PPC_OPCODE_ANY
) != 0
518 && (insn
& (0x3ff << 1)) == 19 << 1)))
521 /* Any other value on mfcr is an error. */
522 else if ((insn
& (0x3ff << 1)) == 19 << 1)
524 /* A value of -1 means we used the one operand form of
525 mfcr which is valid. */
527 *errmsg
= _("invalid mfcr mask");
531 return insn
| ((value
& 0xff) << 12);
535 extract_fxm (unsigned long insn
,
536 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
539 long mask
= (insn
>> 12) & 0xff;
541 /* Is this a Power4 insn? */
542 if ((insn
& (1 << 20)) != 0)
544 /* Exactly one bit of MASK should be set. */
545 if (mask
== 0 || (mask
& -mask
) != mask
)
549 /* Check that non-power4 form of mfcr has a zero MASK. */
550 else if ((insn
& (0x3ff << 1)) == 19 << 1)
562 insert_li20 (unsigned long insn
,
564 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
565 const char **errmsg ATTRIBUTE_UNUSED
)
568 | ((value
& 0xf0000) >> 5)
569 | ((value
& 0x0f800) << 5)
574 extract_li20 (unsigned long insn
,
575 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
576 int *invalid ATTRIBUTE_UNUSED
)
578 long ext
= ((insn
& 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
581 | (((insn
>> 11) & 0xf) << 16)
582 | (((insn
>> 17) & 0xf) << 12)
583 | (((insn
>> 16) & 0x1) << 11)
587 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
588 For SYNC, some L values are reserved:
589 * Value 3 is reserved on newer server cpus.
590 * Values 2 and 3 are reserved on all other cpus. */
593 insert_ls (unsigned long insn
,
598 /* For SYNC, some L values are illegal. */
599 if (((insn
>> 1) & 0x3ff) == 598)
601 long max_lvalue
= (dialect
& PPC_OPCODE_POWER4
) ? 2 : 1;
602 if (value
> max_lvalue
)
604 *errmsg
= _("illegal L operand value");
609 return insn
| ((value
& 0x3) << 21);
613 extract_ls (unsigned long insn
,
617 unsigned long lvalue
= (insn
>> 21) & 3;
619 if (((insn
>> 1) & 0x3ff) == 598)
621 unsigned long max_lvalue
= (dialect
& PPC_OPCODE_POWER4
) ? 2 : 1;
622 if (lvalue
> max_lvalue
)
628 /* The 4-bit E field in a sync instruction that accepts 2 operands.
629 If ESYNC is non-zero, then the L field must be either 0 or 1 and
630 the complement of ESYNC-bit2. */
633 insert_esync (unsigned long insn
,
638 unsigned long ls
= (insn
>> 21) & 0x03;
642 if (((dialect
& PPC_OPCODE_E6500
) != 0 && ls
> 1)
643 || ((dialect
& PPC_OPCODE_POWER9
) != 0 && ls
> 2))
644 *errmsg
= _("illegal L operand value");
649 || (((value
>> 1) & 0x1) ^ ls
) == 0)
650 *errmsg
= _("incompatible L operand value");
652 return insn
| ((value
& 0xf) << 16);
656 extract_esync (unsigned long insn
,
660 unsigned long ls
= (insn
>> 21) & 0x3;
661 unsigned long lvalue
= (insn
>> 16) & 0xf;
665 if (((dialect
& PPC_OPCODE_E6500
) != 0 && ls
> 1)
666 || ((dialect
& PPC_OPCODE_POWER9
) != 0 && ls
> 2))
670 || (((lvalue
>> 1) & 0x1) ^ ls
) == 0)
676 /* The MB and ME fields in an M form instruction expressed as a single
677 operand which is itself a bitmask. The extraction function always
678 marks it as invalid, since we never want to recognize an
679 instruction which uses a field of this type. */
682 insert_mbe (unsigned long insn
,
684 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
687 unsigned long uval
, mask
;
688 int mb
, me
, mx
, count
, last
;
694 *errmsg
= _("illegal bitmask");
706 /* mb: location of last 0->1 transition */
707 /* me: location of last 1->0 transition */
708 /* count: # transitions */
710 for (mx
= 0, mask
= 1L << 31; mx
< 32; ++mx
, mask
>>= 1)
712 if ((uval
& mask
) && !last
)
718 else if (!(uval
& mask
) && last
)
728 if (count
!= 2 && (count
!= 0 || ! last
))
729 *errmsg
= _("illegal bitmask");
731 return insn
| (mb
<< 6) | ((me
- 1) << 1);
735 extract_mbe (unsigned long insn
,
736 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
745 mb
= (insn
>> 6) & 0x1f;
746 me
= (insn
>> 1) & 0x1f;
750 for (i
= mb
; i
<= me
; i
++)
751 ret
|= 1L << (31 - i
);
753 else if (mb
== me
+ 1)
755 else /* (mb > me + 1) */
758 for (i
= me
+ 1; i
< mb
; i
++)
759 ret
&= ~(1L << (31 - i
));
764 /* The MB or ME field in an MD or MDS form instruction. The high bit
765 is wrapped to the low end. */
768 insert_mb6 (unsigned long insn
,
770 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
771 const char **errmsg ATTRIBUTE_UNUSED
)
773 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
777 extract_mb6 (unsigned long insn
,
778 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
779 int *invalid ATTRIBUTE_UNUSED
)
781 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
784 /* The NB field in an X form instruction. The value 32 is stored as
788 extract_nb (unsigned long insn
,
789 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
790 int *invalid ATTRIBUTE_UNUSED
)
794 ret
= (insn
>> 11) & 0x1f;
800 /* The NB field in an lswi instruction, which has special value
801 restrictions. The value 32 is stored as 0. */
804 insert_nbi (unsigned long insn
,
806 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
807 const char **errmsg ATTRIBUTE_UNUSED
)
809 long rtvalue
= (insn
>> 21) & 0x1f;
810 long ravalue
= (insn
>> 16) & 0x1f;
814 if (rtvalue
+ (value
+ 3) / 4 > (rtvalue
> ravalue
? ravalue
+ 32
816 *errmsg
= _("address register in load range");
817 return insn
| ((value
& 0x1f) << 11);
820 /* The NSI field in a D form instruction. This is the same as the SI
821 field, only negated. The extraction function always marks it as
822 invalid, since we never want to recognize an instruction which uses
823 a field of this type. */
826 insert_nsi (unsigned long insn
,
828 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
829 const char **errmsg ATTRIBUTE_UNUSED
)
831 return insn
| (-value
& 0xffff);
835 extract_nsi (unsigned long insn
,
836 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
840 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
843 /* The RA field in a D or X form instruction which is an updating
844 load, which means that the RA field may not be zero and may not
845 equal the RT field. */
848 insert_ral (unsigned long insn
,
850 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
854 || (unsigned long) value
== ((insn
>> 21) & 0x1f))
855 *errmsg
= "invalid register operand when updating";
856 return insn
| ((value
& 0x1f) << 16);
860 extract_ral (unsigned long insn
,
861 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
864 long rtvalue
= (insn
>> 21) & 0x1f;
865 long ravalue
= (insn
>> 16) & 0x1f;
867 if (rtvalue
== ravalue
|| ravalue
== 0)
872 /* The RA field in an lmw instruction, which has special value
876 insert_ram (unsigned long insn
,
878 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
881 if ((unsigned long) value
>= ((insn
>> 21) & 0x1f))
882 *errmsg
= _("index register in load range");
883 return insn
| ((value
& 0x1f) << 16);
887 extract_ram (unsigned long insn
,
888 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
891 unsigned long rtvalue
= (insn
>> 21) & 0x1f;
892 unsigned long ravalue
= (insn
>> 16) & 0x1f;
894 if (ravalue
>= rtvalue
)
899 /* The RA field in the DQ form lq or an lswx instruction, which have special
900 value restrictions. */
903 insert_raq (unsigned long insn
,
905 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
908 long rtvalue
= (insn
>> 21) & 0x1f;
910 if (value
== rtvalue
)
911 *errmsg
= _("source and target register operands must be different");
912 return insn
| ((value
& 0x1f) << 16);
916 extract_raq (unsigned long insn
,
917 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
920 unsigned long rtvalue
= (insn
>> 21) & 0x1f;
921 unsigned long ravalue
= (insn
>> 16) & 0x1f;
923 if (ravalue
== rtvalue
)
928 /* The RA field in a D or X form instruction which is an updating
929 store or an updating floating point load, which means that the RA
930 field may not be zero. */
933 insert_ras (unsigned long insn
,
935 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
939 *errmsg
= _("invalid register operand when updating");
940 return insn
| ((value
& 0x1f) << 16);
944 extract_ras (unsigned long insn
,
945 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
948 unsigned long ravalue
= (insn
>> 16) & 0x1f;
955 /* The RB field in an X form instruction when it must be the same as
956 the RS field in the instruction. This is used for extended
957 mnemonics like mr. This operand is marked FAKE. The insertion
958 function just copies the BT field into the BA field, and the
959 extraction function just checks that the fields are the same. */
962 insert_rbs (unsigned long insn
,
963 long value ATTRIBUTE_UNUSED
,
964 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
965 const char **errmsg ATTRIBUTE_UNUSED
)
967 return insn
| (((insn
>> 21) & 0x1f) << 11);
971 extract_rbs (unsigned long insn
,
972 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
975 if (((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
980 /* The RB field in an lswx instruction, which has special value
984 insert_rbx (unsigned long insn
,
986 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
989 long rtvalue
= (insn
>> 21) & 0x1f;
991 if (value
== rtvalue
)
992 *errmsg
= _("source and target register operands must be different");
993 return insn
| ((value
& 0x1f) << 11);
997 extract_rbx (unsigned long insn
,
998 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1001 unsigned long rtvalue
= (insn
>> 21) & 0x1f;
1002 unsigned long rbvalue
= (insn
>> 11) & 0x1f;
1004 if (rbvalue
== rtvalue
)
1009 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1010 static unsigned long
1011 insert_sci8 (unsigned long insn
,
1013 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1014 const char **errmsg
)
1016 unsigned int fill_scale
= 0;
1017 unsigned long ui8
= value
;
1019 if ((ui8
& 0xffffff00) == 0)
1021 else if ((ui8
& 0xffffff00) == 0xffffff00)
1023 else if ((ui8
& 0xffff00ff) == 0)
1025 fill_scale
= 1 << 8;
1028 else if ((ui8
& 0xffff00ff) == 0xffff00ff)
1030 fill_scale
= 0x400 | (1 << 8);
1033 else if ((ui8
& 0xff00ffff) == 0)
1035 fill_scale
= 2 << 8;
1038 else if ((ui8
& 0xff00ffff) == 0xff00ffff)
1040 fill_scale
= 0x400 | (2 << 8);
1043 else if ((ui8
& 0x00ffffff) == 0)
1045 fill_scale
= 3 << 8;
1048 else if ((ui8
& 0x00ffffff) == 0x00ffffff)
1050 fill_scale
= 0x400 | (3 << 8);
1055 *errmsg
= _("illegal immediate value");
1059 return insn
| fill_scale
| (ui8
& 0xff);
1063 extract_sci8 (unsigned long insn
,
1064 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1065 int *invalid ATTRIBUTE_UNUSED
)
1067 int fill
= insn
& 0x400;
1068 int scale_factor
= (insn
& 0x300) >> 5;
1069 long value
= (insn
& 0xff) << scale_factor
;
1072 value
|= ~((long) 0xff << scale_factor
);
1076 static unsigned long
1077 insert_sci8n (unsigned long insn
,
1080 const char **errmsg
)
1082 return insert_sci8 (insn
, -value
, dialect
, errmsg
);
1086 extract_sci8n (unsigned long insn
,
1090 return -extract_sci8 (insn
, dialect
, invalid
);
1093 static unsigned long
1094 insert_sd4h (unsigned long insn
,
1096 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1097 const char **errmsg ATTRIBUTE_UNUSED
)
1099 return insn
| ((value
& 0x1e) << 7);
1103 extract_sd4h (unsigned long insn
,
1104 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1105 int *invalid ATTRIBUTE_UNUSED
)
1107 return ((insn
>> 8) & 0xf) << 1;
1110 static unsigned long
1111 insert_sd4w (unsigned long insn
,
1113 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1114 const char **errmsg ATTRIBUTE_UNUSED
)
1116 return insn
| ((value
& 0x3c) << 6);
1120 extract_sd4w (unsigned long insn
,
1121 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1122 int *invalid ATTRIBUTE_UNUSED
)
1124 return ((insn
>> 8) & 0xf) << 2;
1127 static unsigned long
1128 insert_oimm (unsigned long insn
,
1130 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1131 const char **errmsg ATTRIBUTE_UNUSED
)
1133 return insn
| (((value
- 1) & 0x1f) << 4);
1137 extract_oimm (unsigned long insn
,
1138 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1139 int *invalid ATTRIBUTE_UNUSED
)
1141 return ((insn
>> 4) & 0x1f) + 1;
1144 /* The SH field in an MD form instruction. This is split. */
1146 static unsigned long
1147 insert_sh6 (unsigned long insn
,
1149 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1150 const char **errmsg ATTRIBUTE_UNUSED
)
1152 /* SH6 operand in the rldixor instructions. */
1153 if (PPC_OP (insn
) == 4)
1154 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 5);
1156 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1160 extract_sh6 (unsigned long insn
,
1161 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1162 int *invalid ATTRIBUTE_UNUSED
)
1164 /* SH6 operand in the rldixor instructions. */
1165 if (PPC_OP (insn
) == 4)
1166 return ((insn
>> 6) & 0x1f) | ((insn
<< 5) & 0x20);
1168 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1171 /* The SPR field in an XFX form instruction. This is flipped--the
1172 lower 5 bits are stored in the upper 5 and vice- versa. */
1174 static unsigned long
1175 insert_spr (unsigned long insn
,
1177 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1178 const char **errmsg ATTRIBUTE_UNUSED
)
1180 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1184 extract_spr (unsigned long insn
,
1185 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1186 int *invalid ATTRIBUTE_UNUSED
)
1188 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1191 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1192 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
1194 static unsigned long
1195 insert_sprg (unsigned long insn
,
1198 const char **errmsg
)
1201 || (value
> 3 && (dialect
& ALLOW8_SPRG
) == 0))
1202 *errmsg
= _("invalid sprg number");
1204 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1205 user mode. Anything else must use spr 272..279. */
1206 if (value
<= 3 || (insn
& 0x100) != 0)
1209 return insn
| ((value
& 0x17) << 16);
1213 extract_sprg (unsigned long insn
,
1217 unsigned long val
= (insn
>> 16) & 0x1f;
1219 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1220 If not BOOKE, 405 or VLE, then both use only 272..275. */
1221 if ((val
- 0x10 > 3 && (dialect
& ALLOW8_SPRG
) == 0)
1222 || (val
- 0x10 > 7 && (insn
& 0x100) != 0)
1229 /* The TBR field in an XFX instruction. This is just like SPR, but it
1232 static unsigned long
1233 insert_tbr (unsigned long insn
,
1235 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1236 const char **errmsg
)
1238 if (value
!= 268 && value
!= 269)
1239 *errmsg
= _("invalid tbr number");
1240 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1244 extract_tbr (unsigned long insn
,
1245 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1250 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1251 if (ret
!= 268 && ret
!= 269)
1256 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1258 static unsigned long
1259 insert_xt6 (unsigned long insn
,
1261 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1262 const char **errmsg ATTRIBUTE_UNUSED
)
1264 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 5);
1268 extract_xt6 (unsigned long insn
,
1269 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1270 int *invalid ATTRIBUTE_UNUSED
)
1272 return ((insn
<< 5) & 0x20) | ((insn
>> 21) & 0x1f);
1275 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
1276 static unsigned long
1277 insert_xtq6 (unsigned long insn
,
1279 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1280 const char **errmsg ATTRIBUTE_UNUSED
)
1282 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 2);
1286 extract_xtq6 (unsigned long insn
,
1287 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1288 int *invalid ATTRIBUTE_UNUSED
)
1290 return ((insn
<< 2) & 0x20) | ((insn
>> 21) & 0x1f);
1293 /* The XA field in an XX3 form instruction. This is split. */
1295 static unsigned long
1296 insert_xa6 (unsigned long insn
,
1298 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1299 const char **errmsg ATTRIBUTE_UNUSED
)
1301 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x20) >> 3);
1305 extract_xa6 (unsigned long insn
,
1306 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1307 int *invalid ATTRIBUTE_UNUSED
)
1309 return ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
1312 /* The XB field in an XX3 form instruction. This is split. */
1314 static unsigned long
1315 insert_xb6 (unsigned long insn
,
1317 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1318 const char **errmsg ATTRIBUTE_UNUSED
)
1320 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1324 extract_xb6 (unsigned long insn
,
1325 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1326 int *invalid ATTRIBUTE_UNUSED
)
1328 return ((insn
<< 4) & 0x20) | ((insn
>> 11) & 0x1f);
1331 /* The XB field in an XX3 form instruction when it must be the same as
1332 the XA field in the instruction. This is used for extended
1333 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1334 function just copies the XA field into the XB field, and the
1335 extraction function just checks that the fields are the same. */
1337 static unsigned long
1338 insert_xb6s (unsigned long insn
,
1339 long value ATTRIBUTE_UNUSED
,
1340 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1341 const char **errmsg ATTRIBUTE_UNUSED
)
1343 return insn
| (((insn
>> 16) & 0x1f) << 11) | (((insn
>> 2) & 0x1) << 1);
1347 extract_xb6s (unsigned long insn
,
1348 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1351 if ((((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1352 || (((insn
>> 2) & 0x1) != ((insn
>> 1) & 0x1)))
1357 /* The XC field in an XX4 form instruction. This is split. */
1359 static unsigned long
1360 insert_xc6 (unsigned long insn
,
1362 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1363 const char **errmsg ATTRIBUTE_UNUSED
)
1365 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 2);
1369 extract_xc6 (unsigned long insn
,
1370 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1371 int *invalid ATTRIBUTE_UNUSED
)
1373 return ((insn
<< 2) & 0x20) | ((insn
>> 6) & 0x1f);
1376 static unsigned long
1377 insert_dm (unsigned long insn
,
1379 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1380 const char **errmsg
)
1382 if (value
!= 0 && value
!= 1)
1383 *errmsg
= _("invalid constant");
1384 return insn
| (((value
) ? 3 : 0) << 8);
1388 extract_dm (unsigned long insn
,
1389 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1394 value
= (insn
>> 8) & 3;
1395 if (value
!= 0 && value
!= 3)
1397 return (value
) ? 1 : 0;
1400 /* The VLESIMM field in an I16A form instruction. This is split. */
1402 static unsigned long
1403 insert_vlesi (unsigned long insn
,
1405 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1406 const char **errmsg ATTRIBUTE_UNUSED
)
1408 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1412 extract_vlesi (unsigned long insn
,
1413 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1414 int *invalid ATTRIBUTE_UNUSED
)
1416 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1417 value
= (value
^ 0x8000) - 0x8000;
1421 static unsigned long
1422 insert_vlensi (unsigned long insn
,
1424 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1425 const char **errmsg ATTRIBUTE_UNUSED
)
1428 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1431 extract_vlensi (unsigned long insn
,
1432 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1433 int *invalid ATTRIBUTE_UNUSED
)
1435 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1436 value
= (value
^ 0x8000) - 0x8000;
1437 /* Don't use for disassembly. */
1442 /* The VLEUIMM field in an I16A form instruction. This is split. */
1444 static unsigned long
1445 insert_vleui (unsigned long insn
,
1447 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1448 const char **errmsg ATTRIBUTE_UNUSED
)
1450 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1454 extract_vleui (unsigned long insn
,
1455 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1456 int *invalid ATTRIBUTE_UNUSED
)
1458 return ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1461 /* The VLEUIMML field in an I16L form instruction. This is split. */
1463 static unsigned long
1464 insert_vleil (unsigned long insn
,
1466 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1467 const char **errmsg ATTRIBUTE_UNUSED
)
1469 return insn
| ((value
& 0xf800) << 5) | (value
& 0x7ff);
1473 extract_vleil (unsigned long insn
,
1474 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1475 int *invalid ATTRIBUTE_UNUSED
)
1477 return ((insn
>> 5) & 0xf800) | (insn
& 0x7ff);
1480 static unsigned long
1481 insert_evuimm2_ex0 (unsigned long insn
,
1483 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1484 const char **errmsg
)
1486 if (value
> 0 && value
<= 0x3e)
1487 return insn
| ((value
& 0x3e) << 10);
1490 *errmsg
= _("UIMM = 00000 is illegal");
1496 extract_evuimm2_ex0 (unsigned long insn
,
1497 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1500 long value
= ((insn
>> 10) & 0x3e);
1507 static unsigned long
1508 insert_evuimm4_ex0 (unsigned long insn
,
1510 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1511 const char **errmsg
)
1513 if (value
> 0 && value
<= 0x7c)
1514 return insn
| ((value
& 0x7c) << 9);
1517 *errmsg
= _("UIMM = 00000 is illegal");
1523 extract_evuimm4_ex0 (unsigned long insn
,
1524 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1527 long value
= ((insn
>> 9) & 0x7c);
1534 static unsigned long
1535 insert_evuimm8_ex0 (unsigned long insn
,
1537 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1538 const char **errmsg
)
1540 if (value
> 0 && value
<= 0xf8)
1541 return insn
| ((value
& 0xf8) << 8);
1544 *errmsg
= _("UIMM = 00000 is illegal");
1550 extract_evuimm8_ex0 (unsigned long insn
,
1551 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1554 long value
= ((insn
>> 8) & 0xf8);
1561 static unsigned long
1562 insert_evuimm_lt16 (unsigned long insn
,
1564 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1565 const char **errmsg
)
1567 if (value
>= 0 && value
<= 15)
1568 return insn
| ((value
& 0xf) << 11);
1571 *errmsg
= _("UIMM values >15 are illegal");
1577 extract_evuimm_lt16 (unsigned long insn
,
1578 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1581 long value
= ((insn
>> 11) & 0x1f);
1588 static unsigned long
1589 insert_rD_rS_even (unsigned long insn
,
1591 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1592 const char **errmsg
)
1594 if ((value
& 0x1) == 0)
1595 return insn
| ((value
& 0x1e) << 21);
1598 *errmsg
= _("GPR odd is illegal");
1604 extract_rD_rS_even (unsigned long insn
,
1605 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1608 long value
= ((insn
>> 21) & 0x1f);
1609 if ((value
& 0x1) != 0)
1615 static unsigned long
1616 insert_off_lsp (unsigned long insn
,
1618 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1619 const char **errmsg
)
1621 if (value
> 0 && value
<= 0x3)
1622 return insn
| (value
& 0x3);
1625 *errmsg
= _("invalid offset");
1631 extract_off_lsp (unsigned long insn
,
1632 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1635 long value
= (insn
& 0x3);
1642 /* The operands table.
1644 The fields are bitm, shift, insert, extract, flags.
1646 We used to put parens around the various additions, like the one
1647 for BA just below. However, that caused trouble with feeble
1648 compilers with a limit on depth of a parenthesized expression, like
1649 (reportedly) the compiler in Microsoft Developer Studio 5. So we
1650 omit the parens, since the macros are never used in a context where
1651 the addition will be ambiguous. */
1653 const struct powerpc_operand powerpc_operands
[] =
1655 /* The zero index is used to indicate the end of the list of
1658 { 0, 0, NULL
, NULL
, 0 },
1660 /* The BA field in an XL form instruction. */
1661 #define BA UNUSED + 1
1662 /* The BI field in a B form or XL form instruction. */
1664 #define BI_MASK (0x1f << 16)
1665 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1667 /* The BA field in an XL form instruction when it must be the same
1668 as the BT field in the same instruction. */
1670 { 0x1f, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
1672 /* The BB field in an XL form instruction. */
1674 #define BB_MASK (0x1f << 11)
1675 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1677 /* The BB field in an XL form instruction when it must be the same
1678 as the BA field in the same instruction. */
1680 /* The VB field in a VX form instruction when it must be the same
1681 as the VA field in the same instruction. */
1683 { 0x1f, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
1685 /* The BD field in a B form instruction. The lower two bits are
1688 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1690 /* The BD field in a B form instruction when absolute addressing is
1693 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
1695 /* The BD field in a B form instruction when the - modifier is used.
1696 This sets the y bit of the BO field appropriately. */
1698 { 0xfffc, 0, insert_bdm
, extract_bdm
,
1699 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1701 /* The BD field in a B form instruction when the - modifier is used
1702 and absolute address is used. */
1703 #define BDMA BDM + 1
1704 { 0xfffc, 0, insert_bdm
, extract_bdm
,
1705 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
1707 /* The BD field in a B form instruction when the + modifier is used.
1708 This sets the y bit of the BO field appropriately. */
1709 #define BDP BDMA + 1
1710 { 0xfffc, 0, insert_bdp
, extract_bdp
,
1711 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1713 /* The BD field in a B form instruction when the + modifier is used
1714 and absolute addressing is used. */
1715 #define BDPA BDP + 1
1716 { 0xfffc, 0, insert_bdp
, extract_bdp
,
1717 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
1719 /* The BF field in an X or XL form instruction. */
1721 /* The CRFD field in an X form instruction. */
1723 /* The CRD field in an XL form instruction. */
1725 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1727 /* The BF field in an X or XL form instruction. */
1729 { 0x7, 23, NULL
, NULL
, 0 },
1731 /* An optional BF field. This is used for comparison instructions,
1732 in which an omitted BF field is taken as zero. */
1734 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
1736 /* The BFA field in an X or XL form instruction. */
1738 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1740 /* The BO field in a B form instruction. Certain values are
1743 #define BO_MASK (0x1f << 21)
1744 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
1746 /* The BO field in a B form instruction when the + or - modifier is
1747 used. This is like the BO field, but it must be even. */
1749 { 0x1e, 21, insert_boe
, extract_boe
, 0 },
1751 /* The RM field in an X form instruction. */
1753 { 0x3, 11, NULL
, NULL
, 0 },
1756 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
1758 /* The BT field in an X or XL form instruction. */
1760 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1762 /* The BI16 field in a BD8 form instruction. */
1764 { 0x3, 8, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1766 /* The BI32 field in a BD15 form instruction. */
1767 #define BI32 BI16 + 1
1768 { 0xf, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1770 /* The BO32 field in a BD15 form instruction. */
1771 #define BO32 BI32 + 1
1772 { 0x3, 20, NULL
, NULL
, 0 },
1774 /* The B8 field in a BD8 form instruction. */
1776 { 0x1fe, -1, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1778 /* The B15 field in a BD15 form instruction. The lowest bit is
1781 { 0xfffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1783 /* The B24 field in a BD24 form instruction. The lowest bit is
1786 { 0x1fffffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1788 /* The condition register number portion of the BI field in a B form
1789 or XL form instruction. This is used for the extended
1790 conditional branch mnemonics, which set the lower two bits of the
1791 BI field. This field is optional. */
1793 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
1795 /* The CRB field in an X form instruction. */
1797 /* The MB field in an M form instruction. */
1799 #define MB_MASK (0x1f << 6)
1800 { 0x1f, 6, NULL
, NULL
, 0 },
1802 /* The CRD32 field in an XL form instruction. */
1803 #define CRD32 CRB + 1
1804 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1806 /* The CRFS field in an X form instruction. */
1807 #define CRFS CRD32 + 1
1808 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1810 #define CRS CRFS + 1
1811 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
1813 /* The CT field in an X form instruction. */
1815 /* The MO field in an mbar instruction. */
1817 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
1819 /* The D field in a D form instruction. This is a displacement off
1820 a register, and implies that the next operand is a register in
1823 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
1825 /* The D8 field in a D form instruction. This is a displacement off
1826 a register, and implies that the next operand is a register in
1829 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
1831 /* The DCMX field in an X form instruction. */
1833 { 0x7f, 16, NULL
, NULL
, 0 },
1835 /* The split DCMX field in an X form instruction. */
1836 #define DCMXS DCMX + 1
1837 { 0x7f, PPC_OPSHIFT_INV
, insert_dcmxs
, extract_dcmxs
, 0 },
1839 /* The DQ field in a DQ form instruction. This is like D, but the
1840 lower four bits are forced to zero. */
1841 #define DQ DCMXS + 1
1842 { 0xfff0, 0, NULL
, NULL
,
1843 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
1845 /* The DS field in a DS form instruction. This is like D, but the
1846 lower two bits are forced to zero. */
1848 { 0xfffc, 0, NULL
, NULL
,
1849 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
1851 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
1852 unsigned imediate */
1855 { 0x3ff, 11, NULL
, NULL
, 0 },
1857 /* The split D field in a DX form instruction. */
1858 #define DXD DUIS + 1
1859 { 0xffff, PPC_OPSHIFT_INV
, insert_dxd
, extract_dxd
,
1860 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
1862 /* The split ND field in a DX form instruction.
1863 This is the same as the DX field, only negated. */
1864 #define NDXD DXD + 1
1865 { 0xffff, PPC_OPSHIFT_INV
, insert_dxdn
, extract_dxdn
,
1866 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
1868 /* The E field in a wrteei instruction. */
1869 /* And the W bit in the pair singles instructions. */
1870 /* And the ST field in a VX form instruction. */
1874 { 0x1, 15, NULL
, NULL
, 0 },
1876 /* The FL1 field in a POWER SC form instruction. */
1878 /* The U field in an X form instruction. */
1880 { 0xf, 12, NULL
, NULL
, 0 },
1882 /* The FL2 field in a POWER SC form instruction. */
1884 { 0x7, 2, NULL
, NULL
, 0 },
1886 /* The FLM field in an XFL form instruction. */
1888 { 0xff, 17, NULL
, NULL
, 0 },
1890 /* The FRA field in an X or A form instruction. */
1892 #define FRA_MASK (0x1f << 16)
1893 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
1895 /* The FRAp field of DFP instructions. */
1896 #define FRAp FRA + 1
1897 { 0x1e, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
1899 /* The FRB field in an X or A form instruction. */
1900 #define FRB FRAp + 1
1901 #define FRB_MASK (0x1f << 11)
1902 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
1904 /* The FRBp field of DFP instructions. */
1905 #define FRBp FRB + 1
1906 { 0x1e, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
1908 /* The FRC field in an A form instruction. */
1909 #define FRC FRBp + 1
1910 #define FRC_MASK (0x1f << 6)
1911 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
1913 /* The FRS field in an X form instruction or the FRT field in a D, X
1914 or A form instruction. */
1917 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
1919 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
1921 #define FRSp FRS + 1
1923 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
1925 /* The FXM field in an XFX instruction. */
1926 #define FXM FRSp + 1
1927 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
1929 /* Power4 version for mfcr. */
1930 #define FXM4 FXM + 1
1931 { 0xff, 12, insert_fxm
, extract_fxm
,
1932 PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL_VALUE
},
1933 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
1934 { -1, -1, NULL
, NULL
, 0},
1936 /* The IMM20 field in an LI instruction. */
1937 #define IMM20 FXM4 + 2
1938 { 0xfffff, PPC_OPSHIFT_INV
, insert_li20
, extract_li20
, PPC_OPERAND_SIGNED
},
1940 /* The L field in a D or X form instruction. */
1942 { 0x1, 21, NULL
, NULL
, 0 },
1944 /* The optional L field in tlbie and tlbiel instructions. */
1946 /* The R field in a HTM X form instruction. */
1948 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
1950 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
1951 #define L32OPT LOPT + 1
1952 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL32
},
1954 /* The L field in dcbf instruction. */
1955 #define L2OPT L32OPT + 1
1956 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
1958 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
1959 #define SVC_LEV L2OPT + 1
1960 { 0x7f, 5, NULL
, NULL
, 0 },
1962 /* The LEV field in an SC form instruction. */
1963 #define LEV SVC_LEV + 1
1964 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
1966 /* The LI field in an I form instruction. The lower two bits are
1969 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1971 /* The LI field in an I form instruction when used as an absolute
1974 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
1976 /* The LS or WC field in an X (sync or wait) form instruction. */
1979 { 0x3, 21, insert_ls
, extract_ls
, PPC_OPERAND_OPTIONAL
},
1981 /* The ME field in an M form instruction. */
1983 #define ME_MASK (0x1f << 1)
1984 { 0x1f, 1, NULL
, NULL
, 0 },
1986 /* The MB and ME fields in an M form instruction expressed a single
1987 operand which is a bitmask indicating which bits to select. This
1988 is a two operand form using PPC_OPERAND_NEXT. See the
1989 description in opcode/ppc.h for what this means. */
1991 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
1992 { -1, 0, insert_mbe
, extract_mbe
, 0 },
1994 /* The MB or ME field in an MD or MDS form instruction. The high
1995 bit is wrapped to the low end. */
1998 #define MB6_MASK (0x3f << 5)
1999 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
2001 /* The NB field in an X form instruction. The value 32 is stored as
2004 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
2006 /* The NBI field in an lswi instruction, which has special value
2007 restrictions. The value 32 is stored as 0. */
2009 { 0x1f, 11, insert_nbi
, extract_nb
, PPC_OPERAND_PLUS1
},
2011 /* The NSI field in a D form instruction. This is the same as the
2012 SI field, only negated. */
2014 { 0xffff, 0, insert_nsi
, extract_nsi
,
2015 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
2017 /* The NSI field in a D form instruction when we accept a wide range
2018 of positive values. */
2019 #define NSISIGNOPT NSI + 1
2020 { 0xffff, 0, insert_nsi
, extract_nsi
,
2021 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2023 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
2024 #define RA NSISIGNOPT + 1
2025 #define RA_MASK (0x1f << 16)
2026 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
2028 /* As above, but 0 in the RA field means zero, not r0. */
2030 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
2032 /* The RA field in the DQ form lq or an lswx instruction, which have
2033 special value restrictions. */
2036 { 0x1f, 16, insert_raq
, extract_raq
, PPC_OPERAND_GPR_0
},
2038 /* The RA field in a D or X form instruction which is an updating
2039 load, which means that the RA field may not be zero and may not
2040 equal the RT field. */
2042 { 0x1f, 16, insert_ral
, extract_ral
, PPC_OPERAND_GPR_0
},
2044 /* The RA field in an lmw instruction, which has special value
2047 { 0x1f, 16, insert_ram
, extract_ram
, PPC_OPERAND_GPR_0
},
2049 /* The RA field in a D or X form instruction which is an updating
2050 store or an updating floating point load, which means that the RA
2051 field may not be zero. */
2053 { 0x1f, 16, insert_ras
, extract_ras
, PPC_OPERAND_GPR_0
},
2055 /* The RA field of the tlbwe, dccci and iccci instructions,
2056 which are optional. */
2057 #define RAOPT RAS + 1
2058 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2060 /* The RB field in an X, XO, M, or MDS form instruction. */
2061 #define RB RAOPT + 1
2062 #define RB_MASK (0x1f << 11)
2063 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
2065 /* The RB field in an X form instruction when it must be the same as
2066 the RS field in the instruction. This is used for extended
2067 mnemonics like mr. */
2069 { 0x1f, 11, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
2071 /* The RB field in an lswx instruction, which has special value
2074 { 0x1f, 11, insert_rbx
, extract_rbx
, PPC_OPERAND_GPR
},
2076 /* The RB field of the dccci and iccci instructions, which are optional. */
2077 #define RBOPT RBX + 1
2078 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2080 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
2081 #define RC RBOPT + 1
2082 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_GPR
},
2084 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
2085 instruction or the RT field in a D, DS, X, XFX or XO form
2089 #define RT_MASK (0x1f << 21)
2091 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
2093 #define RD_EVEN RS + 1
2094 #define RS_EVEN RD_EVEN
2095 { 0x1f, 21, insert_rD_rS_even
, extract_rD_rS_even
, PPC_OPERAND_GPR
},
2097 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
2098 which have special value restrictions. */
2099 #define RSQ RS_EVEN + 1
2101 #define Q_MASK (1 << 21)
2102 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
2104 /* The RS field of the tlbwe instruction, which is optional. */
2107 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2109 /* The RX field of the SE_RR form instruction. */
2111 { 0x1f, PPC_OPSHIFT_INV
, insert_rx
, extract_rx
, PPC_OPERAND_GPR
},
2113 /* The ARX field of the SE_RR form instruction. */
2115 { 0x1f, PPC_OPSHIFT_INV
, insert_arx
, extract_arx
, PPC_OPERAND_GPR
},
2117 /* The RY field of the SE_RR form instruction. */
2120 { 0x1f, PPC_OPSHIFT_INV
, insert_ry
, extract_ry
, PPC_OPERAND_GPR
},
2122 /* The ARY field of the SE_RR form instruction. */
2124 { 0x1f, PPC_OPSHIFT_INV
, insert_ary
, extract_ary
, PPC_OPERAND_GPR
},
2126 /* The SCLSCI8 field in a D form instruction. */
2127 #define SCLSCI8 ARY + 1
2128 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8
, extract_sci8
, 0 },
2130 /* The SCLSCI8N field in a D form instruction. This is the same as the
2131 SCLSCI8 field, only negated. */
2132 #define SCLSCI8N SCLSCI8 + 1
2133 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8n
, extract_sci8n
,
2134 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
2136 /* The SD field of the SD4 form instruction. */
2137 #define SE_SD SCLSCI8N + 1
2138 { 0xf, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
2140 /* The SD field of the SD4 form instruction, for halfword. */
2141 #define SE_SDH SE_SD + 1
2142 { 0x1e, PPC_OPSHIFT_INV
, insert_sd4h
, extract_sd4h
, PPC_OPERAND_PARENS
},
2144 /* The SD field of the SD4 form instruction, for word. */
2145 #define SE_SDW SE_SDH + 1
2146 { 0x3c, PPC_OPSHIFT_INV
, insert_sd4w
, extract_sd4w
, PPC_OPERAND_PARENS
},
2148 /* The SH field in an X or M form instruction. */
2149 #define SH SE_SDW + 1
2150 #define SH_MASK (0x1f << 11)
2151 /* The other UIMM field in a EVX form instruction. */
2153 /* The FC field in an atomic X form instruction. */
2155 { 0x1f, 11, NULL
, NULL
, 0 },
2157 #define EVUIMM_LT16 SH + 1
2158 { 0x1f, 11, insert_evuimm_lt16
, extract_evuimm_lt16
, 0 },
2160 /* The SI field in a HTM X form instruction. */
2161 #define HTM_SI EVUIMM_LT16 + 1
2162 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2164 /* The SH field in an MD form instruction. This is split. */
2165 #define SH6 HTM_SI + 1
2166 #define SH6_MASK ((0x1f << 11) | (1 << 1))
2167 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_sh6
, 0 },
2169 /* The SH field of some variants of the tlbre and tlbwe
2170 instructions, and the ELEV field of the e_sc instruction. */
2173 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2175 /* The SI field in a D form instruction. */
2177 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2179 /* The SI field in a D form instruction when we accept a wide range
2180 of positive values. */
2181 #define SISIGNOPT SI + 1
2182 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2184 /* The SI8 field in a D form instruction. */
2185 #define SI8 SISIGNOPT + 1
2186 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2188 /* The SPR field in an XFX form instruction. This is flipped--the
2189 lower 5 bits are stored in the upper 5 and vice- versa. */
2193 #define SPR_MASK (0x3ff << 11)
2194 { 0x3ff, 11, insert_spr
, extract_spr
, PPC_OPERAND_SPR
},
2196 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
2197 #define SPRBAT SPR + 1
2198 #define SPRBAT_MASK (0x3 << 17)
2199 { 0x3, 17, NULL
, NULL
, 0 },
2201 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
2202 #define SPRG SPRBAT + 1
2203 { 0x1f, 16, insert_sprg
, extract_sprg
, PPC_OPERAND_SPR
},
2205 /* The SR field in an X form instruction. */
2207 /* The 4-bit UIMM field in a VX form instruction. */
2209 { 0xf, 16, NULL
, NULL
, 0 },
2211 /* The STRM field in an X AltiVec form instruction. */
2213 /* The T field in a tlbilx form instruction. */
2215 /* The L field in wclr instructions. */
2217 { 0x3, 21, NULL
, NULL
, 0 },
2219 /* The ESYNC field in an X (sync) form instruction. */
2220 #define ESYNC STRM + 1
2221 { 0xf, 16, insert_esync
, extract_esync
, PPC_OPERAND_OPTIONAL
},
2223 /* The SV field in a POWER SC form instruction. */
2224 #define SV ESYNC + 1
2225 { 0x3fff, 2, NULL
, NULL
, 0 },
2227 /* The TBR field in an XFX form instruction. This is like the SPR
2228 field, but it is optional. */
2230 { 0x3ff, 11, insert_tbr
, extract_tbr
,
2231 PPC_OPERAND_SPR
| PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL_VALUE
},
2232 /* If the TBR operand is ommitted, use the value 268. */
2233 { -1, 268, NULL
, NULL
, 0},
2235 /* The TO field in a D or X form instruction. */
2238 #define TO_MASK (0x1f << 21)
2239 { 0x1f, 21, NULL
, NULL
, 0 },
2241 /* The UI field in a D form instruction. */
2243 { 0xffff, 0, NULL
, NULL
, 0 },
2245 #define UISIGNOPT UI + 1
2246 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
2248 /* The IMM field in an SE_IM5 instruction. */
2249 #define UI5 UISIGNOPT + 1
2250 { 0x1f, 4, NULL
, NULL
, 0 },
2252 /* The OIMM field in an SE_OIM5 instruction. */
2253 #define OIMM5 UI5 + 1
2254 { 0x1f, PPC_OPSHIFT_INV
, insert_oimm
, extract_oimm
, PPC_OPERAND_PLUS1
},
2256 /* The UI7 field in an SE_LI instruction. */
2257 #define UI7 OIMM5 + 1
2258 { 0x7f, 4, NULL
, NULL
, 0 },
2260 /* The VA field in a VA, VX or VXR form instruction. */
2262 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
2264 /* The VB field in a VA, VX or VXR form instruction. */
2266 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
2268 /* The VC field in a VA form instruction. */
2270 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
2272 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
2275 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
2277 /* The SIMM field in a VX form instruction, and TE in Z form. */
2280 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2282 /* The UIMM field in a VX form instruction. */
2283 #define UIMM SIMM + 1
2285 { 0x1f, 16, NULL
, NULL
, 0 },
2287 /* The 3-bit UIMM field in a VX form instruction. */
2288 #define UIMM3 UIMM + 1
2289 { 0x7, 16, NULL
, NULL
, 0 },
2291 /* The 6-bit UIM field in a X form instruction. */
2292 #define UIM6 UIMM3 + 1
2293 { 0x3f, 16, NULL
, NULL
, 0 },
2295 /* The SIX field in a VX form instruction. */
2296 #define SIX UIM6 + 1
2297 { 0xf, 11, NULL
, NULL
, 0 },
2299 /* The PS field in a VX form instruction. */
2301 { 0x1, 9, NULL
, NULL
, 0 },
2303 /* The SHB field in a VA form instruction. */
2305 { 0xf, 6, NULL
, NULL
, 0 },
2307 /* The other UIMM field in a half word EVX form instruction. */
2308 #define EVUIMM_2 SHB + 1
2309 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
2311 #define EVUIMM_2_EX0 EVUIMM_2 + 1
2312 { 0x3e, 10, insert_evuimm2_ex0
, extract_evuimm2_ex0
, PPC_OPERAND_PARENS
},
2314 /* The other UIMM field in a word EVX form instruction. */
2315 #define EVUIMM_4 EVUIMM_2_EX0 + 1
2316 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
2318 #define EVUIMM_4_EX0 EVUIMM_4 + 1
2319 { 0x7c, 9, insert_evuimm4_ex0
, extract_evuimm4_ex0
, PPC_OPERAND_PARENS
},
2321 /* The other UIMM field in a double EVX form instruction. */
2322 #define EVUIMM_8 EVUIMM_4_EX0 + 1
2323 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
2325 #define EVUIMM_8_EX0 EVUIMM_8 + 1
2326 { 0xf8, 8, insert_evuimm8_ex0
, extract_evuimm8_ex0
, PPC_OPERAND_PARENS
},
2328 /* The WS or DRM field in an X form instruction. */
2329 #define WS EVUIMM_8_EX0 + 1
2331 { 0x7, 11, NULL
, NULL
, 0 },
2333 /* PowerPC paired singles extensions. */
2334 /* W bit in the pair singles instructions for x type instructions. */
2336 /* The BO16 field in a BD8 form instruction. */
2338 { 0x1, 10, 0, 0, 0 },
2340 /* IDX bits for quantization in the pair singles instructions. */
2341 #define PSQ PSWM + 1
2342 { 0x7, 12, 0, 0, PPC_OPERAND_GQR
},
2344 /* IDX bits for quantization in the pair singles x-type instructions. */
2345 #define PSQM PSQ + 1
2346 { 0x7, 7, 0, 0, PPC_OPERAND_GQR
},
2348 /* Smaller D field for quantization in the pair singles instructions. */
2349 #define PSD PSQM + 1
2350 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
2352 /* The L field in an mtmsrd or A form instruction or R or W in an
2357 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2359 /* The RMC or CY field in a Z23 form instruction. */
2362 { 0x3, 9, NULL
, NULL
, 0 },
2365 { 0x1, 16, NULL
, NULL
, 0 },
2368 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2371 { 0x1, 17, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2374 { 0x3, 19, NULL
, NULL
, 0 },
2377 { 0x1, 20, NULL
, NULL
, 0 },
2379 /* The S field in a XL form instruction. */
2381 { 0x1, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL_VALUE
},
2382 /* If the SXL operand is ommitted, use the value 1. */
2383 { -1, 1, NULL
, NULL
, 0},
2385 /* SH field starting at bit position 16. */
2386 #define SH16 SXL + 2
2387 /* The DCM and DGM fields in a Z form instruction. */
2390 { 0x3f, 10, NULL
, NULL
, 0 },
2392 /* The EH field in larx instruction. */
2394 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2396 /* The L field in an mtfsf or XFL form instruction. */
2397 /* The A field in a HTM X form instruction. */
2398 #define XFL_L EH + 1
2400 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2402 /* Xilinx APU related masks and macros */
2403 #define FCRT XFL_L + 1
2404 #define FCRT_MASK (0x1f << 21)
2405 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
2407 /* Xilinx FSL related masks and macros */
2408 #define FSL FCRT + 1
2409 #define FSL_MASK (0x1f << 11)
2410 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
2412 /* Xilinx UDI related masks and macros */
2414 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
2417 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
2420 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
2423 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
2425 /* The VLESIMM field in a D form instruction. */
2426 #define VLESIMM URC + 1
2427 { 0xffff, PPC_OPSHIFT_INV
, insert_vlesi
, extract_vlesi
,
2428 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2430 /* The VLENSIMM field in a D form instruction. */
2431 #define VLENSIMM VLESIMM + 1
2432 { 0xffff, PPC_OPSHIFT_INV
, insert_vlensi
, extract_vlensi
,
2433 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2435 /* The VLEUIMM field in a D form instruction. */
2436 #define VLEUIMM VLENSIMM + 1
2437 { 0xffff, PPC_OPSHIFT_INV
, insert_vleui
, extract_vleui
, 0 },
2439 /* The VLEUIMML field in a D form instruction. */
2440 #define VLEUIMML VLEUIMM + 1
2441 { 0xffff, PPC_OPSHIFT_INV
, insert_vleil
, extract_vleil
, 0 },
2443 /* The XT and XS fields in an XX1 or XX3 form instruction. This is
2445 #define XS6 VLEUIMML + 1
2447 { 0x3f, PPC_OPSHIFT_INV
, insert_xt6
, extract_xt6
, PPC_OPERAND_VSR
},
2449 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
2450 #define XSQ6 XT6 + 1
2452 { 0x3f, PPC_OPSHIFT_INV
, insert_xtq6
, extract_xtq6
, PPC_OPERAND_VSR
},
2454 /* The XA field in an XX3 form instruction. This is split. */
2455 #define XA6 XTQ6 + 1
2456 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6
, extract_xa6
, PPC_OPERAND_VSR
},
2458 /* The XB field in an XX2 or XX3 form instruction. This is split. */
2460 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6
, extract_xb6
, PPC_OPERAND_VSR
},
2462 /* The XB field in an XX3 form instruction when it must be the same as
2463 the XA field in the instruction. This is used in extended mnemonics
2464 like xvmovdp. This is split. */
2465 #define XB6S XB6 + 1
2466 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6s
, extract_xb6s
, PPC_OPERAND_FAKE
},
2468 /* The XC field in an XX4 form instruction. This is split. */
2469 #define XC6 XB6S + 1
2470 { 0x3f, PPC_OPSHIFT_INV
, insert_xc6
, extract_xc6
, PPC_OPERAND_VSR
},
2472 /* The DM or SHW field in an XX3 form instruction. */
2475 { 0x3, 8, NULL
, NULL
, 0 },
2477 /* The DM field in an extended mnemonic XX3 form instruction. */
2479 { 0x3, 8, insert_dm
, extract_dm
, 0 },
2481 /* The UIM field in an XX2 form instruction. */
2482 #define UIM DMEX + 1
2483 /* The 2-bit UIMM field in a VX form instruction. */
2485 /* The 2-bit L field in a darn instruction. */
2487 { 0x3, 16, NULL
, NULL
, 0 },
2489 #define ERAT_T UIM + 1
2490 { 0x7, 21, NULL
, NULL
, 0 },
2492 #define IH ERAT_T + 1
2493 { 0x7, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2495 /* The 8-bit IMM8 field in a XX1 form instruction. */
2497 { 0xff, 11, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
2499 #define VX_OFF IMM8 + 1
2500 { 0x3, 0, insert_off_lsp
, extract_off_lsp
, 0 },
2503 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
2504 / sizeof (powerpc_operands
[0]));
2506 /* Macros used to form opcodes. */
2508 /* The main opcode. */
2509 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2510 #define OP_MASK OP (0x3f)
2512 /* The main opcode combined with a trap code in the TO field of a D
2513 form instruction. Used for extended mnemonics for the trap
2515 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2516 #define OPTO_MASK (OP_MASK | TO_MASK)
2518 /* The main opcode combined with a comparison size bit in the L field
2519 of a D form or X form instruction. Used for extended mnemonics for
2520 the comparison instructions. */
2521 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2522 #define OPL_MASK OPL (0x3f,1)
2524 /* The main opcode combined with an update code in D form instruction.
2525 Used for extended mnemonics for VLE memory instructions. */
2526 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2527 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2529 /* The main opcode combined with an update code and the RT fields
2530 specified in D form instruction. Used for VLE volatile context
2531 save/restore instructions. */
2532 #define OPVUPRT(x,vup,rt) \
2534 | ((((unsigned long)(rt)) & 0x1f) << 21))
2535 #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2537 /* An A form instruction. */
2538 #define A(op, xop, rc) \
2540 | ((((unsigned long)(xop)) & 0x1f) << 1) \
2541 | (((unsigned long)(rc)) & 1))
2542 #define A_MASK A (0x3f, 0x1f, 1)
2544 /* An A_MASK with the FRB field fixed. */
2545 #define AFRB_MASK (A_MASK | FRB_MASK)
2547 /* An A_MASK with the FRC field fixed. */
2548 #define AFRC_MASK (A_MASK | FRC_MASK)
2550 /* An A_MASK with the FRA and FRC fields fixed. */
2551 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2553 /* An AFRAFRC_MASK, but with L bit clear. */
2554 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2556 /* A B form instruction. */
2557 #define B(op, aa, lk) \
2559 | ((((unsigned long)(aa)) & 1) << 1) \
2561 #define B_MASK B (0x3f, 1, 1)
2563 /* A BD8 form instruction. This is a 16-bit instruction. */
2564 #define BD8(op, aa, lk) \
2565 (((((unsigned long)(op)) & 0x3f) << 10) \
2566 | (((aa) & 1) << 9) \
2567 | (((lk) & 1) << 8))
2568 #define BD8_MASK BD8 (0x3f, 1, 1)
2570 /* Another BD8 form instruction. This is a 16-bit instruction. */
2571 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2572 #define BD8IO_MASK BD8IO (0x1f)
2574 /* A BD8 form instruction for simplified mnemonics. */
2575 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2576 /* A mask that excludes BO32 and BI32. */
2577 #define EBD8IO1_MASK 0xf800
2578 /* A mask that includes BO32 and excludes BI32. */
2579 #define EBD8IO2_MASK 0xfc00
2580 /* A mask that include BO32 AND BI32. */
2581 #define EBD8IO3_MASK 0xff00
2583 /* A BD15 form instruction. */
2584 #define BD15(op, aa, lk) \
2586 | ((((unsigned long)(aa)) & 0xf) << 22) \
2588 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2590 /* A BD15 form instruction for extended conditional branch mnemonics. */
2591 #define EBD15(op, aa, bo, lk) \
2592 (((op) & 0x3f) << 26) \
2593 | (((aa) & 0xf) << 22) \
2594 | (((bo) & 0x3) << 20) \
2596 #define EBD15_MASK 0xfff00001
2598 /* A BD15 form instruction for extended conditional branch mnemonics
2600 #define EBD15BI(op, aa, bo, bi, lk) \
2601 ((((op) & 0x3f) << 26) \
2602 | (((aa) & 0xf) << 22) \
2603 | (((bo) & 0x3) << 20) \
2604 | (((bi) & 0x3) << 16) \
2607 #define EBD15BI_MASK 0xfff30001
2609 /* A BD24 form instruction. */
2610 #define BD24(op, aa, lk) \
2612 | ((((unsigned long)(aa)) & 1) << 25) \
2614 #define BD24_MASK BD24 (0x3f, 1, 1)
2616 /* A B form instruction setting the BO field. */
2617 #define BBO(op, bo, aa, lk) \
2618 (B ((op), (aa), (lk)) \
2619 | ((((unsigned long)(bo)) & 0x1f) << 21))
2620 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2622 /* A BBO_MASK with the y bit of the BO field removed. This permits
2623 matching a conditional branch regardless of the setting of the y
2624 bit. Similarly for the 'at' bits used for power4 branch hints. */
2625 #define Y_MASK (((unsigned long) 1) << 21)
2626 #define AT1_MASK (((unsigned long) 3) << 21)
2627 #define AT2_MASK (((unsigned long) 9) << 21)
2628 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2629 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2631 /* A B form instruction setting the BO field and the condition bits of
2633 #define BBOCB(op, bo, cb, aa, lk) \
2634 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2635 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2637 /* A BBOCB_MASK with the y bit of the BO field removed. */
2638 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2639 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2640 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2642 /* A BBOYCB_MASK in which the BI field is fixed. */
2643 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2644 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2646 /* A VLE C form instruction. */
2647 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2648 #define C_LK_MASK C_LK(0x7fff, 1)
2649 #define C(x) ((((unsigned long)(x)) & 0xffff))
2650 #define C_MASK C(0xffff)
2652 /* An Context form instruction. */
2653 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
2654 #define CTX_MASK CTX(0x3f, 0x7)
2656 /* An User Context form instruction. */
2657 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2658 #define UCTX_MASK UCTX(0x3f, 0x1f)
2660 /* The main opcode mask with the RA field clear. */
2661 #define DRA_MASK (OP_MASK | RA_MASK)
2663 /* A DQ form VSX instruction. */
2664 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2665 #define DQX_MASK DQX (0x3f, 7)
2667 /* A DS form instruction. */
2668 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2669 #define DS_MASK DSO (0x3f, 3)
2671 /* An DX form instruction. */
2672 #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2673 #define DX_MASK DX (0x3f, 0x1f)
2674 /* An DX form instruction with the D bits specified. */
2675 #define NODX_MASK (DX_MASK | 0x1fffc1)
2677 /* An EVSEL form instruction. */
2678 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2679 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2681 /* An IA16 form instruction. */
2682 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2683 #define IA16_MASK IA16(0x3f, 0x1f)
2685 /* An I16A form instruction. */
2686 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2687 #define I16A_MASK I16A(0x3f, 0x1f)
2689 /* An I16L form instruction. */
2690 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2691 #define I16L_MASK I16L(0x3f, 0x1f)
2693 /* An IM7 form instruction. */
2694 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2695 #define IM7_MASK IM7(0x1f)
2697 /* An M form instruction. */
2698 #define M(op, rc) (OP (op) | ((rc) & 1))
2699 #define M_MASK M (0x3f, 1)
2701 /* An LI20 form instruction. */
2702 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2703 #define LI20_MASK LI20(0x3f, 0x1)
2705 /* An M form instruction with the ME field specified. */
2706 #define MME(op, me, rc) \
2708 | ((((unsigned long)(me)) & 0x1f) << 1))
2710 /* An M_MASK with the MB and ME fields fixed. */
2711 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2713 /* An M_MASK with the SH and ME fields fixed. */
2714 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2716 /* An MD form instruction. */
2717 #define MD(op, xop, rc) \
2719 | ((((unsigned long)(xop)) & 0x7) << 2) \
2721 #define MD_MASK MD (0x3f, 0x7, 1)
2723 /* An MD_MASK with the MB field fixed. */
2724 #define MDMB_MASK (MD_MASK | MB6_MASK)
2726 /* An MD_MASK with the SH field fixed. */
2727 #define MDSH_MASK (MD_MASK | SH6_MASK)
2729 /* An MDS form instruction. */
2730 #define MDS(op, xop, rc) \
2732 | ((((unsigned long)(xop)) & 0xf) << 1) \
2734 #define MDS_MASK MDS (0x3f, 0xf, 1)
2736 /* An MDS_MASK with the MB field fixed. */
2737 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2739 /* An SC form instruction. */
2740 #define SC(op, sa, lk) \
2742 | ((((unsigned long)(sa)) & 1) << 1) \
2746 | (((unsigned long) 0x3ff) << 16) \
2747 | (((unsigned long) 1) << 1) \
2750 /* An SCI8 form instruction. */
2751 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2752 #define SCI8_MASK SCI8(0x3f, 0x1f)
2754 /* An SCI8 form instruction. */
2755 #define SCI8BF(op, fop, xop) \
2757 | ((((unsigned long)(xop)) & 0x1f) << 11) \
2758 | (((fop) & 7) << 23))
2759 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2761 /* An SD4 form instruction. This is a 16-bit instruction. */
2762 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2763 #define SD4_MASK SD4(0xf)
2765 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2766 #define SE_IM5(op, xop) \
2767 (((((unsigned long)(op)) & 0x3f) << 10) \
2768 | (((xop) & 0x1) << 9))
2769 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2771 /* An SE_R form instruction. This is a 16-bit instruction. */
2772 #define SE_R(op, xop) \
2773 (((((unsigned long)(op)) & 0x3f) << 10) \
2774 | (((xop) & 0x3f) << 4))
2775 #define SE_R_MASK SE_R(0x3f, 0x3f)
2777 /* An SE_RR form instruction. This is a 16-bit instruction. */
2778 #define SE_RR(op, xop) \
2779 (((((unsigned long)(op)) & 0x3f) << 10) \
2780 | (((xop) & 0x3) << 8))
2781 #define SE_RR_MASK SE_RR(0x3f, 3)
2783 /* A VX form instruction. */
2784 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2786 /* The mask for an VX form instruction. */
2787 #define VX_MASK VX(0x3f, 0x7ff)
2789 /* A VX LSP form instruction. */
2790 #define VX_LSP(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xffff))
2792 /* The mask for an VX LSP form instruction. */
2793 #define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
2794 #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
2796 /* A VX_MASK with the VA field fixed. */
2797 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2799 /* A VX_MASK with the VB field fixed. */
2800 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2802 /* A VX_MASK with the VA and VB fields fixed. */
2803 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2805 /* A VX_MASK with the VD and VA fields fixed. */
2806 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2808 /* A VX_MASK with a UIMM4 field. */
2809 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2811 /* A VX_MASK with a UIMM3 field. */
2812 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2814 /* A VX_MASK with a UIMM2 field. */
2815 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2817 /* A VX_MASK with a PS field. */
2818 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2820 /* A VX_MASK with the VA field fixed with a PS field. */
2821 #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2823 /* A VA form instruction. */
2824 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2826 /* The mask for an VA form instruction. */
2827 #define VXA_MASK VXA(0x3f, 0x3f)
2829 /* A VXA_MASK with a SHB field. */
2830 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2832 /* A VXR form instruction. */
2833 #define VXR(op, xop, rc) \
2835 | (((rc) & 1) << 10) \
2836 | (((unsigned long)(xop)) & 0x3ff))
2838 /* The mask for a VXR form instruction. */
2839 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2841 /* A VX form instruction with a VA tertiary opcode. */
2842 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2844 #define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2845 #define VXASH_MASK VXASH (0x3f, 0x1f)
2847 /* An X form instruction. */
2848 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2850 /* A X form instruction for Quad-Precision FP Instructions. */
2851 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2853 /* An EX form instruction. */
2854 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2856 /* The mask for an EX form instruction. */
2857 #define EX_MASK EX (0x3f, 0x7ff)
2859 /* An XX2 form instruction. */
2860 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2862 /* A XX2 form instruction with the VA bits specified. */
2863 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2865 /* An XX3 form instruction. */
2866 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2868 /* An XX3 form instruction with the RC bit specified. */
2869 #define XX3RC(op, xop, rc) \
2871 | (((rc) & 1) << 10) \
2872 | ((((unsigned long)(xop)) & 0x7f) << 3))
2874 /* An XX4 form instruction. */
2875 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2877 /* A Z form instruction. */
2878 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2880 /* An X form instruction with the RC bit specified. */
2881 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2883 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2884 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2886 /* An X form instruction with the RA bits specified as two ops. */
2887 #define XMMF(op, xop, mop0, mop1) \
2889 | ((mop0) & 3) << 19 \
2890 | ((mop1) & 7) << 16)
2892 /* A Z form instruction with the RC bit specified. */
2893 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2895 /* The mask for an X form instruction. */
2896 #define X_MASK XRC (0x3f, 0x3ff, 1)
2898 /* The mask for an X form instruction with the BF bits specified. */
2899 #define XBF_MASK (X_MASK | (3 << 21))
2901 /* An X form wait instruction with everything filled in except the WC
2903 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2905 /* The mask for an XX1 form instruction. */
2906 #define XX1_MASK X (0x3f, 0x3ff)
2908 /* An XX1_MASK with the RB field fixed. */
2909 #define XX1RB_MASK (XX1_MASK | RB_MASK)
2911 /* The mask for an XX2 form instruction. */
2912 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2914 /* The mask for an XX2 form instruction with the UIM bits specified. */
2915 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2917 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2918 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2920 /* The mask for an XX2 form instruction with the BF bits specified. */
2921 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2923 /* The mask for an XX2 form instruction with the BF and DCMX bits
2925 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2927 /* The mask for an XX2 form instruction with a split DCMX bits
2929 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2931 /* The mask for an XX3 form instruction. */
2932 #define XX3_MASK XX3 (0x3f, 0xff)
2934 /* The mask for an XX3 form instruction with the BF bits specified. */
2935 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2937 /* The mask for an XX3 form instruction with the DM or SHW bits
2939 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2940 #define XX3SHW_MASK XX3DM_MASK
2942 /* The mask for an XX4 form instruction. */
2943 #define XX4_MASK XX4 (0x3f, 0x3)
2945 /* An X form wait instruction with everything filled in except the WC
2947 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2949 /* The mask for an XMMF form instruction. */
2950 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2952 /* The mask for a Z form instruction. */
2953 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2954 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2956 /* An X_MASK with the RA/VA field fixed. */
2957 #define XRA_MASK (X_MASK | RA_MASK)
2958 #define XVA_MASK XRA_MASK
2960 /* An XRA_MASK with the A_L/W field clear. */
2961 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2962 #define XRLA_MASK XWRA_MASK
2964 /* An X_MASK with the RB field fixed. */
2965 #define XRB_MASK (X_MASK | RB_MASK)
2967 /* An X_MASK with the RT field fixed. */
2968 #define XRT_MASK (X_MASK | RT_MASK)
2970 /* An XRT_MASK mask with the L bits clear. */
2971 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2973 /* An X_MASK with the RA and RB fields fixed. */
2974 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2976 /* An XBF_MASK with the RA and RB fields fixed. */
2977 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2979 /* An XRARB_MASK, but with the L bit clear. */
2980 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2982 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2983 #define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2985 /* An X_MASK with the RT and RA fields fixed. */
2986 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2988 /* An X_MASK with the RT and RB fields fixed. */
2989 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2991 /* An XRTRA_MASK, but with L bit clear. */
2992 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2994 /* An X_MASK with the RT, RA and RB fields fixed. */
2995 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2997 /* An XRTRARB_MASK, but with L bit clear. */
2998 #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
3000 /* An XRTRARB_MASK, but with A bit clear. */
3001 #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
3003 /* An XRTRARB_MASK, but with BF bits clear. */
3004 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
3006 /* An X form instruction with the L bit specified. */
3007 #define XOPL(op, xop, l) \
3009 | ((((unsigned long)(l)) & 1) << 21))
3011 /* An X form instruction with the L bits specified. */
3012 #define XOPL2(op, xop, l) \
3014 | ((((unsigned long)(l)) & 3) << 21))
3016 /* An X form instruction with the L bit and RC bit specified. */
3017 #define XRCL(op, xop, l, rc) \
3018 (XRC ((op), (xop), (rc)) \
3019 | ((((unsigned long)(l)) & 1) << 21))
3021 /* An X form instruction with RT fields specified */
3022 #define XRT(op, xop, rt) \
3024 | ((((unsigned long)(rt)) & 0x1f) << 21))
3026 /* An X form instruction with RT and RA fields specified */
3027 #define XRTRA(op, xop, rt, ra) \
3029 | ((((unsigned long)(rt)) & 0x1f) << 21) \
3030 | ((((unsigned long)(ra)) & 0x1f) << 16))
3032 /* The mask for an X form comparison instruction. */
3033 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
3035 /* The mask for an X form comparison instruction with the L field
3037 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
3039 /* An X form trap instruction with the TO field specified. */
3040 #define XTO(op, xop, to) \
3042 | ((((unsigned long)(to)) & 0x1f) << 21))
3043 #define XTO_MASK (X_MASK | TO_MASK)
3045 /* An X form tlb instruction with the SH field specified. */
3046 #define XTLB(op, xop, sh) \
3048 | ((((unsigned long)(sh)) & 0x1f) << 11))
3049 #define XTLB_MASK (X_MASK | SH_MASK)
3051 /* An X form sync instruction. */
3052 #define XSYNC(op, xop, l) \
3054 | ((((unsigned long)(l)) & 3) << 21))
3056 /* An X form sync instruction with everything filled in except the LS
3058 #define XSYNC_MASK (0xff9fffff)
3060 /* An X form sync instruction with everything filled in except the L
3062 #define XSYNCLE_MASK (0xff90ffff)
3064 /* An X_MASK, but with the EH bit clear. */
3065 #define XEH_MASK (X_MASK & ~((unsigned long )1))
3067 /* An X form AltiVec dss instruction. */
3068 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
3069 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
3071 /* An XFL form instruction. */
3072 #define XFL(op, xop, rc) \
3074 | ((((unsigned long)(xop)) & 0x3ff) << 1) \
3075 | (((unsigned long)(rc)) & 1))
3076 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
3078 /* An X form isel instruction. */
3079 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
3080 #define XISEL_MASK XISEL(0x3f, 0x1f)
3082 /* An XL form instruction with the LK field set to 0. */
3083 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
3085 /* An XL form instruction which uses the LK field. */
3086 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
3088 /* The mask for an XL form instruction. */
3089 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
3091 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
3092 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
3094 /* An XL form instruction which explicitly sets the BO field. */
3095 #define XLO(op, bo, xop, lk) \
3096 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
3097 #define XLO_MASK (XL_MASK | BO_MASK)
3099 /* An XL form instruction which explicitly sets the y bit of the BO
3101 #define XLYLK(op, xop, y, lk) \
3102 (XLLK ((op), (xop), (lk)) \
3103 | ((((unsigned long)(y)) & 1) << 21))
3104 #define XLYLK_MASK (XL_MASK | Y_MASK)
3106 /* An XL form instruction which sets the BO field and the condition
3107 bits of the BI field. */
3108 #define XLOCB(op, bo, cb, xop, lk) \
3109 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
3110 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
3112 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
3113 #define XLBB_MASK (XL_MASK | BB_MASK)
3114 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
3115 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
3117 /* A mask for branch instructions using the BH field. */
3118 #define XLBH_MASK (XL_MASK | (0x1c << 11))
3120 /* An XL_MASK with the BO and BB fields fixed. */
3121 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
3123 /* An XL_MASK with the BO, BI and BB fields fixed. */
3124 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
3126 /* An X form mbar instruction with MO field. */
3127 #define XMBAR(op, xop, mo) \
3129 | ((((unsigned long)(mo)) & 1) << 21))
3131 /* An XO form instruction. */
3132 #define XO(op, xop, oe, rc) \
3134 | ((((unsigned long)(xop)) & 0x1ff) << 1) \
3135 | ((((unsigned long)(oe)) & 1) << 10) \
3136 | (((unsigned long)(rc)) & 1))
3137 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
3139 /* An XO_MASK with the RB field fixed. */
3140 #define XORB_MASK (XO_MASK | RB_MASK)
3142 /* An XOPS form instruction for paired singles. */
3143 #define XOPS(op, xop, rc) \
3145 | ((((unsigned long)(xop)) & 0x3ff) << 1) \
3146 | (((unsigned long)(rc)) & 1))
3147 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
3150 /* An XS form instruction. */
3151 #define XS(op, xop, rc) \
3153 | ((((unsigned long)(xop)) & 0x1ff) << 2) \
3154 | (((unsigned long)(rc)) & 1))
3155 #define XS_MASK XS (0x3f, 0x1ff, 1)
3157 /* A mask for the FXM version of an XFX form instruction. */
3158 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
3160 /* An XFX form instruction with the FXM field filled in. */
3161 #define XFXM(op, xop, fxm, p4) \
3163 | ((((unsigned long)(fxm)) & 0xff) << 12) \
3164 | ((unsigned long)(p4) << 20))
3166 /* An XFX form instruction with the SPR field filled in. */
3167 #define XSPR(op, xop, spr) \
3169 | ((((unsigned long)(spr)) & 0x1f) << 16) \
3170 | ((((unsigned long)(spr)) & 0x3e0) << 6))
3171 #define XSPR_MASK (X_MASK | SPR_MASK)
3173 /* An XFX form instruction with the SPR field filled in except for the
3175 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
3177 /* An XFX form instruction with the SPR field filled in except for the
3179 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
3181 /* An X form instruction with everything filled in except the E field. */
3182 #define XE_MASK (0xffff7fff)
3184 /* An X form user context instruction. */
3185 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
3186 #define XUC_MASK XUC(0x3f, 0x1f)
3188 /* An XW form instruction. */
3189 #define XW(op, xop, rc) \
3191 | ((((unsigned long)(xop)) & 0x3f) << 1) \
3193 /* The mask for a G form instruction. rc not supported at present. */
3194 #define XW_MASK XW (0x3f, 0x3f, 0)
3196 /* An APU form instruction. */
3197 #define APU(op, xop, rc) \
3199 | (((unsigned long)(xop)) & 0x3ff) << 1 \
3202 /* The mask for an APU form instruction. */
3203 #define APU_MASK APU (0x3f, 0x3ff, 1)
3204 #define APU_RT_MASK (APU_MASK | RT_MASK)
3205 #define APU_RA_MASK (APU_MASK | RA_MASK)
3207 /* The BO encodings used in extended conditional branch mnemonics. */
3208 #define BODNZF (0x0)
3209 #define BODNZFP (0x1)
3211 #define BODZFP (0x3)
3212 #define BODNZT (0x8)
3213 #define BODNZTP (0x9)
3215 #define BODZTP (0xb)
3226 #define BODNZ (0x10)
3227 #define BODNZP (0x11)
3229 #define BODZP (0x13)
3230 #define BODNZM4 (0x18)
3231 #define BODNZP4 (0x19)
3232 #define BODZM4 (0x1a)
3233 #define BODZP4 (0x1b)
3237 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
3241 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
3244 #define BO32DNZ (0x2)
3245 #define BO32DZ (0x3)
3247 /* The BI condition bit encodings used in extended conditional branch
3254 /* The TO encodings used in extended trap mnemonics. */
3271 /* Smaller names for the flags so each entry in the opcodes table will
3272 fit on a single line. */
3274 #define PPC PPC_OPCODE_PPC
3275 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3276 #define POWER4 PPC_OPCODE_POWER4
3277 #define POWER5 PPC_OPCODE_POWER5
3278 #define POWER6 PPC_OPCODE_POWER6
3279 #define POWER7 PPC_OPCODE_POWER7
3280 #define POWER8 PPC_OPCODE_POWER8
3281 #define POWER9 PPC_OPCODE_POWER9
3282 #define CELL PPC_OPCODE_CELL
3283 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
3284 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
3285 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
3286 #define PPC403 PPC_OPCODE_403
3287 #define PPC405 PPC_OPCODE_405
3288 #define PPC440 PPC_OPCODE_440
3289 #define PPC464 PPC440
3290 #define PPC476 PPC_OPCODE_476
3291 #define PPC750 PPC_OPCODE_750
3292 #define PPC7450 PPC_OPCODE_7450
3293 #define PPC860 PPC_OPCODE_860
3294 #define PPCPS PPC_OPCODE_PPCPS
3295 #define PPCVEC PPC_OPCODE_ALTIVEC
3296 #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500)
3297 #define PPCVEC3 PPC_OPCODE_POWER9
3298 #define PPCVSX PPC_OPCODE_VSX
3299 #define PPCVSX2 PPC_OPCODE_POWER8
3300 #define PPCVSX3 PPC_OPCODE_POWER9
3301 #define POWER PPC_OPCODE_POWER
3302 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
3303 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3304 #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \
3305 | PPC_OPCODE_COMMON)
3306 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3307 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
3308 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
3309 #define MFDEC1 PPC_OPCODE_POWER
3310 #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \
3312 #define BOOKE PPC_OPCODE_BOOKE
3313 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
3314 #define PPCE300 PPC_OPCODE_E300
3315 #define PPCSPE PPC_OPCODE_SPE
3316 #define PPCISEL PPC_OPCODE_ISEL
3317 #define PPCEFS PPC_OPCODE_EFS
3318 #define PPCBRLK PPC_OPCODE_BRLOCK
3319 #define PPCPMR PPC_OPCODE_PMR
3320 #define PPCTMR PPC_OPCODE_TMR
3321 #define PPCCHLK PPC_OPCODE_CACHELCK
3322 #define PPCRFMCI PPC_OPCODE_RFMCI
3323 #define E500MC PPC_OPCODE_E500MC
3324 #define PPCA2 PPC_OPCODE_A2
3325 #define TITAN PPC_OPCODE_TITAN
3326 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
3327 #define E500 PPC_OPCODE_E500
3328 #define E6500 PPC_OPCODE_E6500
3329 #define PPCVLE PPC_OPCODE_VLE
3330 #define PPCHTM PPC_OPCODE_POWER8
3331 #define E200Z4 PPC_OPCODE_E200Z4
3332 #define PPCLSP PPC_OPCODE_LSP
3333 /* The list of embedded processors that use the embedded operand ordering
3334 for the 3 operand dcbt and dcbtst instructions. */
3335 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3340 /* The opcode table.
3342 The format of the opcode table is:
3344 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
3346 NAME is the name of the instruction.
3347 OPCODE is the instruction opcode.
3348 MASK is the opcode mask; this is used to tell the disassembler
3349 which bits in the actual opcode must match OPCODE.
3350 FLAGS are flags indicating which processors support the instruction.
3351 ANTI indicates which processors don't support the instruction.
3352 OPERANDS is the list of operands.
3354 The disassembler reads the table in order and prints the first
3355 instruction which matches, so this table is sorted to put more
3356 specific instructions before more general instructions.
3358 This table must be sorted by major opcode. Please try to keep it
3359 vaguely sorted within major opcode too, except of course where
3360 constrained otherwise by disassembler operation. */
3362 const struct powerpc_opcode powerpc_opcodes
[] = {
3363 {"attn", X(0,256), X_MASK
, POWER4
|PPCA2
, PPC476
|PPCVLE
, {0}},
3364 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3365 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3366 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3367 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3368 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3369 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3370 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3371 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3372 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3373 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3374 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3375 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3376 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3377 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3378 {"tdui", OPTO(2,TOU
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3379 {"tdi", OP(2), OP_MASK
, PPC64
, PPCVLE
, {TO
, RA
, SI
}},
3381 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3382 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3383 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3384 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3385 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3386 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3387 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3388 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3389 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3390 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3391 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3392 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3393 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3394 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3395 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3396 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3397 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3398 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3399 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3400 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3401 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3402 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3403 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3404 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3405 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3406 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3407 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3408 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3409 {"twui", OPTO(3,TOU
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3410 {"tui", OPTO(3,TOU
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3411 {"twi", OP(3), OP_MASK
, PPCCOM
, PPCVLE
, {TO
, RA
, SI
}},
3412 {"ti", OP(3), OP_MASK
, PWRCOM
, PPCVLE
, {TO
, RA
, SI
}},
3414 {"ps_cmpu0", X (4, 0), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3415 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3416 {"vmul10cuq", VX (4, 1), VXVB_MASK
, PPCVEC3
, 0, {VD
, VA
}},
3417 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3418 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3419 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3420 {"vcmpneb", VXR(4, 7,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3421 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3422 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3423 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, 0, {FRT
,RA
,RB
,PSWM
,PSQM
}},
3424 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3425 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, 0, {FRS
,RA
,RB
,PSWM
,PSQM
}},
3426 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3427 {"mulhhwu", XRC(4, 8,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3428 {"mulhhwu.", XRC(4, 8,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3429 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3430 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3431 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3432 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3433 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3434 {"machhwu", XO (4, 12,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3435 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3436 {"machhwu.", XO (4, 12,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3437 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3438 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3439 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3440 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3441 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3442 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3443 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3444 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3445 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3446 {"vmsumudm", VXA(4, 35), VXA_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, VC
}},
3447 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3448 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3449 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3450 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3451 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3452 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3453 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3454 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3455 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3456 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3457 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3458 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3459 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3460 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3461 {"vsldoi", VXA(4, 44), VXASHB_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, SHB
}},
3462 {"vpermxor", VXA(4, 45), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3463 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3464 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VC
, VB
}},
3465 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3466 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VC
, VB
}},
3467 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3468 {"maddhd", VXA(4, 48), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
3469 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3470 {"maddhdu", VXA(4, 49), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
3471 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3472 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3473 {"maddld", VXA(4, 51), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
3474 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3475 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3476 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3477 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3478 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3479 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3480 {"vpermr", VXA(4, 59), VXA_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, VC
}},
3481 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3482 {"vaddeuqm", VXA(4, 60), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3483 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3484 {"vaddecuq", VXA(4, 61), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3485 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3486 {"vsubeuqm", VXA(4, 62), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3487 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3488 {"vsubecuq", VXA(4, 63), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3489 {"ps_cmpo0", X (4, 32), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3490 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3491 {"vmul10ecuq", VX (4, 65), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3492 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3493 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3494 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3495 {"vcmpneh", VXR(4, 71,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3496 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3497 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3498 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, 0, {FRT
,RA
,RB
,PSWM
,PSQM
}},
3499 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3500 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, 0, {FRS
,RA
,RB
,PSWM
,PSQM
}},
3501 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3502 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3503 {"mulhhw", XRC(4, 40,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3504 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3505 {"mulhhw.", XRC(4, 40,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3506 {"machhw", XO (4, 44,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3507 {"machhw.", XO (4, 44,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3508 {"nmachhw", XO (4, 46,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3509 {"nmachhw.", XO (4, 46,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3510 {"ps_cmpu1", X (4, 64), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3511 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3512 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3513 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3514 {"vrlwmi", VX (4, 133), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3515 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3516 {"vcmpnew", VXR(4, 135,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3517 {"vmulouw", VX (4, 136), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3518 {"vmuluwm", VX (4, 137), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3519 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3520 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3521 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3522 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3523 {"machhwsu", XO (4, 76,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3524 {"machhwsu.", XO (4, 76,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3525 {"ps_cmpo1", X (4, 96), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3526 {"vaddudm", VX (4, 192), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3527 {"vmaxud", VX (4, 194), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3528 {"vrld", VX (4, 196), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3529 {"vrldmi", VX (4, 197), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3530 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3531 {"vcmpequd", VXR(4, 199,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3532 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3533 {"machhws", XO (4, 108,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3534 {"machhws.", XO (4, 108,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3535 {"nmachhws", XO (4, 110,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3536 {"nmachhws.", XO (4, 110,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3537 {"vadduqm", VX (4, 256), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3538 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3539 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3540 {"vcmpnezb", VXR(4, 263,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3541 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3542 {"vrefp", VX (4, 266), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3543 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3544 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3545 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3546 {"mulchwu", XRC(4, 136,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3547 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3548 {"mulchwu.", XRC(4, 136,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3549 {"macchwu", XO (4, 140,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3550 {"macchwu.", XO (4, 140,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3551 {"vaddcuq", VX (4, 320), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3552 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3553 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3554 {"vcmpnezh", VXR(4, 327,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3555 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3556 {"vrsqrtefp", VX (4, 330), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3557 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3558 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3559 {"mulchw", XRC(4, 168,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3560 {"mulchw.", XRC(4, 168,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3561 {"macchw", XO (4, 172,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3562 {"macchw.", XO (4, 172,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3563 {"nmacchw", XO (4, 174,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3564 {"nmacchw.", XO (4, 174,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3565 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3566 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3567 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3568 {"vrlwnm", VX (4, 389), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3569 {"vcmpnezw", VXR(4, 391,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3570 {"vmulosw", VX (4, 392), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3571 {"vexptefp", VX (4, 394), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3572 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3573 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3574 {"macchwsu", XO (4, 204,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3575 {"macchwsu.", XO (4, 204,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3576 {"vmaxsd", VX (4, 450), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3577 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3578 {"vrldnm", VX (4, 453), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3579 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3580 {"vlogefp", VX (4, 458), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3581 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3582 {"macchws", XO (4, 236,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3583 {"macchws.", XO (4, 236,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3584 {"nmacchws", XO (4, 238,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3585 {"nmacchws.", XO (4, 238,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3586 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3587 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3588 {"vmul10uq", VX (4, 513), VXVB_MASK
, PPCVEC3
, 0, {VD
, VA
}},
3589 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
, 0, {RS
, RB
, UIMM
}},
3590 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3591 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3592 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, 0, {RS
, RB
, RA
}},
3593 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3594 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
, 0, {RS
, UIMM
, RB
}},
3595 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, 0, {RS
, RB
, UIMM
}},
3596 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3597 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3598 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3599 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3600 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3601 {"vrfin", VX (4, 522), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3602 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3603 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3604 {"vspltb", VX (4, 524), VXUIMM4_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM4
}},
3605 {"vextractub", VX (4, 525), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3606 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3607 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3608 {"vupkhsb", VX (4, 526), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3609 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3610 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3611 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3612 {"evand", VX (4, 529), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3613 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3614 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3615 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
, 0, {RS
, RA
, BBA
}},
3616 {"evor", VX (4, 535), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3617 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3618 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
, 0, {RS
, RA
, BBA
}},
3619 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3620 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3621 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3622 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3623 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3624 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3625 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3626 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3627 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3628 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3629 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3630 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
, 0, {RS
, SIMM
}},
3631 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3632 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
, 0, {RS
, SIMM
}},
3633 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3634 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3635 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3636 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3637 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3638 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3639 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3640 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3641 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3642 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3643 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3644 {"vmul10euq", VX (4, 577), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3645 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3646 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3647 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3648 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3649 {"vrfiz", VX (4, 586), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3650 {"vsplth", VX (4, 588), VXUIMM3_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM3
}},
3651 {"vextractuh", VX (4, 589), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3652 {"vupkhsh", VX (4, 590), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3653 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3654 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
, 0, {RS
, RA
, RB
, CRFS
}},
3655 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3656 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3657 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3658 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3659 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3660 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3661 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3662 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3663 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3664 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3665 {"vmuleuw", VX (4, 648), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3666 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3667 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3668 {"vrfip", VX (4, 650), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3669 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3670 {"vspltw", VX (4, 652), VXUIMM2_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM2
}},
3671 {"vextractuw", VX (4, 653), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3672 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3673 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3674 {"vupklsb", VX (4, 654), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3675 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3676 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3677 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3678 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3679 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3680 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3681 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3682 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3683 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3684 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3685 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3686 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3687 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3688 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3689 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3690 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3691 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3692 {"vminud", VX (4, 706), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3693 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3694 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3695 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3696 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3697 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3698 {"vcmpgtud", VXR(4, 711,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3699 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3700 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3701 {"vrfim", VX (4, 714), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3702 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3703 {"vextractd", VX (4, 717), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3704 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3705 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3706 {"vupklsh", VX (4, 718), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3707 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3708 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3709 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3710 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3711 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3712 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3713 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3714 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3715 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3716 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3717 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3718 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3719 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3720 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3721 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3722 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3723 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3724 {"efdcfuid", VX (4, 738), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3725 {"efdcfsid", VX (4, 739), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3726 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3727 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3728 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3729 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3730 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3731 {"efdctuidz", VX (4, 746), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3732 {"efdctsidz", VX (4, 747), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3733 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3734 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3735 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3736 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3737 {"efdcfui", VX (4, 752), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3738 {"efdcfsi", VX (4, 753), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3739 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3740 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3741 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3742 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3743 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3744 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3745 {"efdctuiz", VX (4, 760), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3746 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3747 {"efdctsiz", VX (4, 762), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3748 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3749 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3750 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3751 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3752 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3753 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3754 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3755 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3756 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3757 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3758 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3759 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3760 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3761 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3762 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3763 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
3764 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
3765 {"vcuxwfp", VX (4, 778), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
3766 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3767 {"vspltisb", VX (4, 780), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
3768 {"vinsertb", VX (4, 781), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3769 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
3770 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3771 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3772 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
3773 {"mullhwu", XRC(4, 392,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3774 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3775 {"mullhwu.", XRC(4, 392,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3776 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
3777 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3778 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
3779 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3780 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
3781 {"maclhwu", XO (4, 396,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3782 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3783 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3784 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
3785 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3786 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
3787 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3788 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3789 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3790 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3791 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3792 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3793 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3794 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
3795 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3796 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
3797 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3798 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
3799 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3800 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
3801 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3802 {"bcdcpsgn.", VX (4, 833), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3803 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3804 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3805 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3806 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3807 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
3808 {"vcsxwfp", VX (4, 842), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
3809 {"vspltish", VX (4, 844), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
3810 {"vinserth", VX (4, 845), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3811 {"vupkhpx", VX (4, 846), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3812 {"mullhw", XRC(4, 424,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3813 {"mullhw.", XRC(4, 424,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3814 {"maclhw", XO (4, 428,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3815 {"maclhw.", XO (4, 428,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3816 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3817 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3818 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3819 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3820 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3821 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3822 {"vmulesw", VX (4, 904), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3823 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
3824 {"vcfpuxws", VX (4, 906), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
3825 {"vspltisw", VX (4, 908), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
3826 {"vinsertw", VX (4, 909), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3827 {"maclhwsu", XO (4, 460,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3828 {"maclhwsu.", XO (4, 460,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3829 {"vminsd", VX (4, 962), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3830 {"vsrad", VX (4, 964), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3831 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3832 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3833 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
3834 {"vcfpsxws", VX (4, 970), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
3835 {"vinsertd", VX (4, 973), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3836 {"vupklpx", VX (4, 974), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3837 {"maclhws", XO (4, 492,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3838 {"maclhws.", XO (4, 492,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3839 {"nmaclhws", XO (4, 494,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3840 {"nmaclhws.", XO (4, 494,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3841 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3842 {"bcdadd.", VX (4,1025), VXPS_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, PS
}},
3843 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3844 {"vabsdub", VX (4,1027), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3845 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3846 {"vand", VX (4,1028), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3847 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3848 {"vcmpneb.", VXR(4, 7,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3849 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3850 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3851 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3852 {"vpmsumb", VX (4,1032), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3853 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3854 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3855 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3856 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3857 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3858 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3859 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3860 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3861 {"machhwuo", XO (4, 12,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3862 {"machhwuo.", XO (4, 12,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3863 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3864 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3865 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3866 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3867 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3868 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3869 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3870 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3871 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3872 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3873 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3874 {"bcdsub.", VX (4,1089), VXPS_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, PS
}},
3875 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3876 {"vabsduh", VX (4,1091), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3877 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3878 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3879 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3880 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3881 {"vcmpneh.", VXR(4, 71,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3882 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3883 {"vpmsumh", VX (4,1096), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3884 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3885 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3886 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3887 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3888 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3889 {"vpkudum", VX (4,1102), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3890 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3891 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3892 {"machhwo", XO (4, 44,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3893 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3894 {"machhwo.", XO (4, 44,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3895 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3896 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3897 {"nmachhwo", XO (4, 46,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3898 {"nmachhwo.", XO (4, 46,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3899 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3900 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3901 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3902 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3903 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3904 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3905 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3906 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3907 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3908 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3909 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3910 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3911 {"bcdus.", VX (4,1153), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3912 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3913 {"vabsduw", VX (4,1155), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3914 {"vmr", VX (4,1156), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VBA
}},
3915 {"vor", VX (4,1156), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3916 {"vcmpnew.", VXR(4, 135,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3917 {"vpmsumw", VX (4,1160), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3918 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3919 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3920 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3921 {"machhwsuo", XO (4, 76,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3922 {"machhwsuo.", XO (4, 76,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3923 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3924 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3925 {"vsubudm", VX (4,1216), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3926 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3927 {"bcds.", VX (4,1217), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
3928 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3929 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3930 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3931 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3932 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3933 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3934 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3935 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3936 {"vcmpequd.", VXR(4, 199,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3937 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3938 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3939 {"vpmsumd", VX (4,1224), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3940 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3941 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3942 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3943 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3944 {"vpkudus", VX (4,1230), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3945 {"machhwso", XO (4, 108,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3946 {"machhwso.", XO (4, 108,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3947 {"nmachhwso", XO (4, 110,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3948 {"nmachhwso.", XO (4, 110,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3949 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3950 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3951 {"vsubuqm", VX (4,1280), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3952 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3953 {"bcdtrunc.", VX (4,1281), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
3954 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3955 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3956 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3957 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3958 {"vnot", VX (4,1284), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VBA
}},
3959 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3960 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3961 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3962 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3963 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3964 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3965 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3966 {"vcipher", VX (4,1288), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3967 {"vcipherlast", VX (4,1289), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3968 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3969 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3970 {"vgbbd", VX (4,1292), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
3971 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3972 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3973 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3974 {"macchwuo", XO (4, 140,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3975 {"macchwuo.", XO (4, 140,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3976 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3977 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3978 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3979 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3980 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3981 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3982 {"vsubcuq", VX (4,1344), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3983 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3984 {"bcdutrunc.", VX (4,1345), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3985 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3986 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3987 {"vorc", VX (4,1348), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3988 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3989 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
3990 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3991 {"vncipher", VX (4,1352), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3992 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3993 {"vncipherlast",VX (4,1353), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3994 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3995 {"vbpermq", VX (4,1356), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3996 {"vpksdus", VX (4,1358), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3997 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3998 {"macchwo", XO (4, 172,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3999 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4000 {"macchwo.", XO (4, 172,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4001 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4002 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4003 {"nmacchwo", XO (4, 174,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4004 {"nmacchwo.", XO (4, 174,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4005 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4006 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4007 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4008 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4009 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4010 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4011 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4012 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4013 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4014 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4015 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4016 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4017 {"vnand", VX (4,1412), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4018 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4019 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4020 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4021 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4022 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4023 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4024 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4025 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4026 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4027 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4028 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4029 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4030 {"macchwsuo", XO (4, 204,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4031 {"macchwsuo.", XO (4, 204,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4032 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4033 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4034 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4035 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4036 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4037 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4038 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4039 {"bcdsr.", VX (4,1473), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
4040 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4041 {"vsld", VX (4,1476), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4042 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4043 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4044 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4045 {"vsbox", VX (4,1480), VXVB_MASK
, PPCVEC2
, 0, {VD
, VA
}},
4046 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4047 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4048 {"vbpermd", VX (4,1484), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4049 {"vpksdss", VX (4,1486), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4050 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4051 {"macchwso", XO (4, 236,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4052 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4053 {"macchwso.", XO (4, 236,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4054 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4055 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4056 {"nmacchwso", XO (4, 238,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4057 {"nmacchwso.", XO (4, 238,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4058 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4059 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK
, PPCVEC3
, 0, {RT
, VB
}},
4060 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK
, PPCVEC3
, 0, {RT
, VB
}},
4061 {"vnegw", VXVA(4,1538,6), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4062 {"vnegd", VXVA(4,1538,7), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4063 {"vprtybw", VXVA(4,1538,8), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4064 {"vprtybd", VXVA(4,1538,9), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4065 {"vprtybq", VXVA(4,1538,10), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4066 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4067 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4068 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4069 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4070 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4071 {"vctzb", VXVA(4,1538,28), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4072 {"vctzh", VXVA(4,1538,29), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4073 {"vctzw", VXVA(4,1538,30), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4074 {"vctzd", VXVA(4,1538,31), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4075 {"mfvscr", VX (4,1540), VXVAVB_MASK
, PPCVEC
, 0, {VD
}},
4076 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4077 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4078 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4079 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4080 {"vextublx", VX (4,1549), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4081 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4082 {"mtvscr", VX (4,1604), VXVDVA_MASK
, PPCVEC
, 0, {VB
}},
4083 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4084 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4085 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4086 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4087 {"vextuhlx", VX (4,1613), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4088 {"vupkhsw", VX (4,1614), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4089 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4090 {"vshasigmaw", VX (4,1666), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, ST
, SIX
}},
4091 {"veqv", VX (4,1668), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4092 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4093 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4094 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4095 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4096 {"vmrgow", VX (4,1676), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4097 {"vextuwlx", VX (4,1677), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4098 {"vshasigmad", VX (4,1730), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, ST
, SIX
}},
4099 {"vsrd", VX (4,1732), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4100 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4101 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4102 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4103 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4104 {"vupklsw", VX (4,1742), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4105 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4106 {"vclzb", VX (4,1794), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4107 {"vpopcntb", VX (4,1795), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4108 {"vsrv", VX (4,1796), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4109 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4110 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4111 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4112 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4113 {"vextubrx", VX (4,1805), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4114 {"maclhwuo", XO (4, 396,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4115 {"maclhwuo.", XO (4, 396,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4116 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4117 {"vclzh", VX (4,1858), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4118 {"vpopcnth", VX (4,1859), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4119 {"vslv", VX (4,1860), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4120 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4121 {"vextuhrx", VX (4,1869), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4122 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4123 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4124 {"maclhwo", XO (4, 428,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4125 {"maclhwo.", XO (4, 428,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4126 {"nmaclhwo", XO (4, 430,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4127 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4128 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4129 {"vclzw", VX (4,1922), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4130 {"vpopcntw", VX (4,1923), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4131 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4132 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4133 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4134 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4135 {"vmrgew", VX (4,1932), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4136 {"vextuwrx", VX (4,1933), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4137 {"maclhwsuo", XO (4, 460,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4138 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4139 {"vclzd", VX (4,1986), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4140 {"vpopcntd", VX (4,1987), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4141 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4142 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4143 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4144 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4145 {"maclhwso", XO (4, 492,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4146 {"maclhwso.", XO (4, 492,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4147 {"nmaclhwso", XO (4, 494,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4148 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4149 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, 0, {RA
, RB
}},
4151 {"mulli", OP(7), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4152 {"muli", OP(7), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4154 {"subfic", OP(8), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4155 {"sfi", OP(8), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4157 {"dozi", OP(9), OP_MASK
, M601
, PPCVLE
, {RT
, RA
, SI
}},
4159 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, PPCVLE
, {OBF
, RA
, UISIGNOPT
}},
4160 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, PPCVLE
, {OBF
, RA
, UISIGNOPT
}},
4161 {"cmpli", OP(10), OP_MASK
, PPC
, PPCVLE
, {BF
, L32OPT
, RA
, UISIGNOPT
}},
4162 {"cmpli", OP(10), OP_MASK
, PWRCOM
, PPC
|PPCVLE
, {BF
, RA
, UISIGNOPT
}},
4164 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, PPCVLE
, {OBF
, RA
, SI
}},
4165 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, PPCVLE
, {OBF
, RA
, SI
}},
4166 {"cmpi", OP(11), OP_MASK
, PPC
, PPCVLE
, {BF
, L32OPT
, RA
, SI
}},
4167 {"cmpi", OP(11), OP_MASK
, PWRCOM
, PPC
|PPCVLE
, {BF
, RA
, SI
}},
4169 {"addic", OP(12), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4170 {"ai", OP(12), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4171 {"subic", OP(12), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, NSI
}},
4173 {"addic.", OP(13), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4174 {"ai.", OP(13), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4175 {"subic.", OP(13), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, NSI
}},
4177 {"li", OP(14), DRA_MASK
, PPCCOM
, PPCVLE
, {RT
, SI
}},
4178 {"lil", OP(14), DRA_MASK
, PWRCOM
, PPCVLE
, {RT
, SI
}},
4179 {"addi", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, SI
}},
4180 {"cal", OP(14), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
4181 {"subi", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, NSI
}},
4182 {"la", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RA0
}},
4184 {"lis", OP(15), DRA_MASK
, PPCCOM
, PPCVLE
, {RT
, SISIGNOPT
}},
4185 {"liu", OP(15), DRA_MASK
, PWRCOM
, PPCVLE
, {RT
, SISIGNOPT
}},
4186 {"addis", OP(15), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, SISIGNOPT
}},
4187 {"cau", OP(15), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA0
, SISIGNOPT
}},
4188 {"subis", OP(15), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, NSISIGNOPT
}},
4190 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4191 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4192 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BD
}},
4193 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BD
}},
4194 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4195 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4196 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BD
}},
4197 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BD
}},
4198 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4199 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4200 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDA
}},
4201 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BDA
}},
4202 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4203 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4204 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDA
}},
4205 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BDA
}},
4206 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4207 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4208 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, PPCVLE
, {BD
}},
4209 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4210 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4211 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, PPCVLE
, {BD
}},
4212 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4213 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4214 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, PPCVLE
, {BDA
}},
4215 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4216 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4217 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, PPCVLE
, {BDA
}},
4219 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4220 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4221 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4222 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4223 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4224 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4225 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4226 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4227 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4228 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4229 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4230 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4231 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4232 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4233 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4234 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4235 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4236 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4237 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4238 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4239 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4240 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4241 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4242 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4243 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4244 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4245 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4246 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4247 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4248 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4249 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4250 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4251 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4252 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4253 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4254 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4255 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4256 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4257 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4258 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4259 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4260 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4261 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4262 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4263 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4264 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4265 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4266 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4267 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4268 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4269 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4270 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4271 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4272 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4273 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4274 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4275 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4276 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4277 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4278 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4279 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4280 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4281 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4282 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4283 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4284 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4285 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4286 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4287 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4288 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4289 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4290 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4291 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4292 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4293 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4294 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4295 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4296 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4297 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4298 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4299 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4300 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4301 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4302 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4304 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4305 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4306 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4307 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4308 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4309 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4310 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4311 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4312 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4313 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4314 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4315 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4316 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4317 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4318 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4319 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4320 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4321 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4322 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4323 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4324 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4325 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4326 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4327 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4328 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4329 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4330 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4331 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4332 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4333 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4334 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4335 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4336 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4337 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4338 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4339 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4340 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4341 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4342 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4343 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4344 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4345 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4346 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4347 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4348 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4349 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4350 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4351 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4352 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4353 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4354 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4355 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4356 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4357 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4358 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4359 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4360 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4361 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4362 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4363 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4365 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4366 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4367 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4368 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4369 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4370 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4371 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4372 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4373 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4374 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4375 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4376 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4377 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4378 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4379 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4380 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4381 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4382 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4383 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4384 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4385 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4386 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4387 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4388 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4390 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4391 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4392 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4393 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4394 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4395 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4396 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4397 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4398 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4399 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4400 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4401 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4402 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4403 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4404 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4405 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4407 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4408 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4409 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4410 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4411 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4412 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4413 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4414 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4415 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4416 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4417 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4418 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4419 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4420 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4421 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4422 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4423 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4424 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4425 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4426 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4427 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4428 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4429 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4430 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4432 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4433 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4434 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4435 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4436 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4437 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4438 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4439 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4440 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4441 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4442 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4443 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4444 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4445 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4446 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4447 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4449 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDM
}},
4450 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDP
}},
4451 {"bc", B(16,0,0), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BD
}},
4452 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDM
}},
4453 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDP
}},
4454 {"bcl", B(16,0,1), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BD
}},
4455 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDMA
}},
4456 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDPA
}},
4457 {"bca", B(16,1,0), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BDA
}},
4458 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDMA
}},
4459 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDPA
}},
4460 {"bcla", B(16,1,1), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BDA
}},
4462 {"svc", SC(17,0,0), SC_MASK
, POWER
, PPCVLE
, {SVC_LEV
, FL1
, FL2
}},
4463 {"scv", SC(17,0,1), SC_MASK
, POWER9
, PPCVLE
, {SVC_LEV
}},
4464 {"svcl", SC(17,0,1), SC_MASK
, POWER
, PPCVLE
, {SVC_LEV
, FL1
, FL2
}},
4465 {"sc", SC(17,1,0), SC_MASK
, PPC
, PPCVLE
, {LEV
}},
4466 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, PPCVLE
, {SV
}},
4467 {"svcla", SC(17,1,1), SC_MASK
, POWER
, PPCVLE
, {SV
}},
4469 {"b", B(18,0,0), B_MASK
, COM
, PPCVLE
, {LI
}},
4470 {"bl", B(18,0,1), B_MASK
, COM
, PPCVLE
, {LI
}},
4471 {"ba", B(18,1,0), B_MASK
, COM
, PPCVLE
, {LIA
}},
4472 {"bla", B(18,1,1), B_MASK
, COM
, PPCVLE
, {LIA
}},
4474 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, PPCVLE
, {BF
, BFA
}},
4476 {"lnia", DX(19,2), NODX_MASK
, POWER9
, PPCVLE
, {RT
}},
4477 {"addpcis", DX(19,2), DX_MASK
, POWER9
, PPCVLE
, {RT
, DXD
}},
4478 {"subpcis", DX(19,2), DX_MASK
, POWER9
, PPCVLE
, {RT
, NDXD
}},
4480 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4481 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4482 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4483 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4484 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4485 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4486 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4487 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4488 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4489 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4490 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4491 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4492 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4493 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, PPCVLE
, {0}},
4494 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4495 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, PPCVLE
, {0}},
4496 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4497 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4498 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4499 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4500 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4501 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4502 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4503 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4505 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4506 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4507 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4508 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4509 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4510 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4511 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4512 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4513 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4514 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4515 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4516 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4517 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4518 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4519 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4520 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4521 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4522 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4523 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4524 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4525 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4526 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4527 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4528 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4529 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4530 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4531 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4532 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4533 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4534 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4535 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4536 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4537 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4538 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4539 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4540 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4541 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4542 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4543 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4544 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4545 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4546 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4547 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4548 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4549 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4550 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4551 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4552 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4553 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4554 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4555 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4556 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4557 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4558 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4559 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4560 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4561 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4562 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4563 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4564 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4565 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4566 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4567 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4568 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4569 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4570 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4571 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4572 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4573 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4574 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4575 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4576 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4577 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4578 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4579 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4580 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4581 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4582 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4583 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4584 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4585 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4586 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4587 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4588 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4589 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4590 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4591 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4592 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4593 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4594 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4595 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4596 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4597 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4598 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4599 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4600 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4601 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4602 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4603 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4604 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4605 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4606 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4607 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4608 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4609 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4610 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4611 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4612 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4613 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4614 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4615 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4616 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4617 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4618 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4619 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4620 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4621 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4622 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4623 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4624 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4625 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4626 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4627 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4628 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4629 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4630 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4631 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4632 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4633 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4634 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4635 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4636 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4637 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4638 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4639 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4640 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4641 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4642 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4643 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4644 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4646 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4647 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4648 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4649 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4650 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4651 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4652 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4653 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4654 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4655 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4656 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4657 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4658 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4659 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4660 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4661 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4662 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4663 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4664 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4665 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4666 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4667 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4668 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4669 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4670 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4671 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4672 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4673 {"bdnztlrl-", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4674 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4675 {"bdnztlrl+", XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4676 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4677 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4678 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4679 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4680 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4681 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4682 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4683 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4684 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4685 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4686 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4687 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4688 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4689 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4690 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4691 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4692 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4693 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4695 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4696 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4697 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4698 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4699 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
4700 {"bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
4701 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
4702 {"bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
4704 {"rfid", XL(19,18), 0xffffffff, PPC64
, PPCVLE
, {0}},
4706 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BA
, BBA
}},
4707 {"crnor", XL(19,33), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4708 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
|PPCA2
|PPC476
, PPCVLE
, {0}},
4710 {"rfdi", XL(19,39), 0xffffffff, E500MC
, PPCVLE
, {0}},
4711 {"rfi", XL(19,50), 0xffffffff, COM
, PPCVLE
, {0}},
4712 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
|PPCE300
|PPCA2
|PPC476
, PPCVLE
, {0}},
4714 {"rfscv", XL(19,82), 0xffffffff, POWER9
, PPCVLE
, {0}},
4715 {"rfsvc", XL(19,82), 0xffffffff, POWER
, PPCVLE
, {0}},
4717 {"rfgi", XL(19,102), 0xffffffff, E500MC
|PPCA2
, PPCVLE
, {0}},
4719 {"crandc", XL(19,129), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4721 {"rfebb", XL(19,146), XLS_MASK
, POWER8
, PPCVLE
, {SXL
}},
4723 {"isync", XL(19,150), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
4724 {"ics", XL(19,150), 0xffffffff, PWRCOM
, PPCVLE
, {0}},
4726 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BAT
, BBA
}},
4727 {"crxor", XL(19,193), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4729 {"dnh", X(19,198), X_MASK
, E500MC
, PPCVLE
, {DUI
, DUIS
}},
4731 {"crnand", XL(19,225), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4733 {"crand", XL(19,257), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4735 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, PPC476
|PPCVLE
, {0}},
4737 {"crset", XL(19,289), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BAT
, BBA
}},
4738 {"creqv", XL(19,289), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4740 {"urfid", XL(19,306), 0xffffffff, POWER9
, PPCVLE
, {0}},
4741 {"stop", XL(19,370), 0xffffffff, POWER9
, PPCVLE
, {0}},
4743 {"doze", XL(19,402), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
4745 {"crorc", XL(19,417), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4747 {"nap", XL(19,434), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
4749 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BA
, BBA
}},
4750 {"cror", XL(19,449), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4752 {"sleep", XL(19,466), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
4753 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
4755 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, PPCVLE
, {0}},
4756 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, PPCVLE
, {0}},
4758 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4759 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4760 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4761 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4762 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4763 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4764 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4765 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4766 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4767 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4768 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4769 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4770 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4771 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4772 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4773 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4774 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4775 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4776 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4777 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4778 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4779 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4780 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4781 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4782 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4783 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4784 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4785 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4786 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4787 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4788 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4789 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4790 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4791 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4792 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4793 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4794 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4795 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4796 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4797 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4798 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4799 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4800 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4801 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4802 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4803 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4804 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4805 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4806 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4807 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4808 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4809 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4810 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4811 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4812 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4813 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4814 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4815 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4816 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4817 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4818 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4819 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4820 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4821 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4822 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4823 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4824 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4825 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4826 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4827 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4828 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4829 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4830 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4831 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4832 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4833 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4834 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4835 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4836 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4837 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4838 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4839 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4840 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4841 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4842 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4843 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4844 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4845 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4846 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4847 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4848 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4849 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4850 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4851 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4852 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4853 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4854 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4855 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4856 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4857 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4858 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4859 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4860 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4861 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4862 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4863 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4864 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4865 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4866 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4867 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4868 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4869 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4870 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4871 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4872 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4873 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4874 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4875 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4876 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4877 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4879 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4880 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4881 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4882 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4883 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4884 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4885 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4886 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4887 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4888 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4889 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4890 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4891 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4892 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4893 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4894 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4895 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4896 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4897 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4898 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4900 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4901 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4902 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4903 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4904 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
4905 {"bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
4906 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
4907 {"bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
4909 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
4910 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
4911 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
4912 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
4913 {"bctar", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCVLE
, {BO
, BI
, BH
}},
4914 {"bctarl", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCVLE
, {BO
, BI
, BH
}},
4916 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
4917 {"rlimi", M(20,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
4919 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
4920 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
4922 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
}},
4923 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, MB
}},
4924 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
4925 {"rlinm", M(21,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
4926 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
}},
4927 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, MB
}},
4928 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
4929 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
4931 {"rlmi", M(22,0), M_MASK
, M601
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
4932 {"rlmi.", M(22,1), M_MASK
, M601
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
4934 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
}},
4935 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
4936 {"rlnm", M(23,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
4937 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
}},
4938 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
4939 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
4941 {"nop", OP(24), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
4942 {"ori", OP(24), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
4943 {"oril", OP(24), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
4945 {"oris", OP(25), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
4946 {"oriu", OP(25), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
4948 {"xnop", OP(26), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
4949 {"xori", OP(26), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
4950 {"xoril", OP(26), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
4952 {"xoris", OP(27), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
4953 {"xoriu", OP(27), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
4955 {"andi.", OP(28), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
4956 {"andil.", OP(28), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
4958 {"andis.", OP(29), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
4959 {"andiu.", OP(29), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
4961 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
}},
4962 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, PPCVLE
, {RA
, RS
, MB6
}},
4963 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
4964 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
}},
4965 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, PPCVLE
, {RA
, RS
, MB6
}},
4966 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
4968 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, ME6
}},
4969 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, ME6
}},
4971 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
4972 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
4974 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
4975 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
4977 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
}},
4978 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, MB6
}},
4979 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
}},
4980 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, MB6
}},
4982 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, ME6
}},
4983 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, ME6
}},
4985 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, 0, {OBF
, RA
, RB
}},
4986 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, 0, {OBF
, RA
, RB
}},
4987 {"cmp", X(31,0), XCMP_MASK
, PPC
, 0, {BF
, L32OPT
, RA
, RB
}},
4988 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4990 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
4991 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
4992 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
4993 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
4994 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
4995 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
4996 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
4997 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
4998 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
4999 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5000 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5001 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5002 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5003 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5004 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5005 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5006 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5007 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5008 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5009 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5010 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5011 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5012 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5013 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5014 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5015 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5016 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5017 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5018 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
, 0, {0}},
5019 {"twu", XTO(31,4,TOU
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5020 {"tu", XTO(31,4,TOU
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5021 {"tw", X(31,4), X_MASK
, PPCCOM
, 0, {TO
, RA
, RB
}},
5022 {"t", X(31,4), X_MASK
, PWRCOM
, 0, {TO
, RA
, RB
}},
5024 {"lvsl", X(31,6), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5025 {"lvebx", X(31,7), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5026 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5028 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5029 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5030 {"subc", XO(31,8,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
5031 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5032 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5033 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
5035 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5036 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5038 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5039 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5040 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5041 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5043 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5044 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5046 {"lxsiwzx", X(31,12), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
5048 {"isellt", X(31,15), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
5050 {"tlbilxlpid", XTO(31,18,0), XTO_MASK
, E500MC
|PPCA2
, 0, {0}},
5051 {"tlbilxpid", XTO(31,18,1), XTO_MASK
, E500MC
|PPCA2
, 0, {0}},
5052 {"tlbilxva", XTO(31,18,3), XTO_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
5053 {"tlbilx", X(31,18), X_MASK
, E500MC
|PPCA2
, 0, {T
, RA0
, RB
}},
5055 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, COM
, 0, {RT
, FXM4
}},
5056 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
, 0, {RT
, FXM
}},
5058 {"lwarx", X(31,20), XEH_MASK
, PPC
, 0, {RT
, RA0
, RB
, EH
}},
5060 {"ldx", X(31,21), X_MASK
, PPC64
, 0, {RT
, RA0
, RB
}},
5062 {"icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
|PPCA2
|PPC476
, 0, {CT
, RA0
, RB
}},
5064 {"lwzx", X(31,23), X_MASK
, PPCCOM
, 0, {RT
, RA0
, RB
}},
5065 {"lx", X(31,23), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5067 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
5068 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
5069 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
5070 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
5072 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
5073 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
5074 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
5075 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
5077 {"sld", XRC(31,27,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
5078 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
5080 {"and", XRC(31,28,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5081 {"and.", XRC(31,28,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5083 {"maskg", XRC(31,29,0), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
5084 {"maskg.", XRC(31,29,1), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
5086 {"ldepx", X(31,29), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5088 {"waitasec", X(31,30), XRTRARB_MASK
, POWER8
, POWER9
, {0}},
5089 {"wait", X(31,30), XWC_MASK
, POWER9
, 0, {WC
}},
5091 {"lwepx", X(31,31), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5093 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
, 0, {OBF
, RA
, RB
}},
5094 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, 0, {OBF
, RA
, RB
}},
5095 {"cmpl", X(31,32), XCMP_MASK
, PPC
, 0, {BF
, L32OPT
, RA
, RB
}},
5096 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
5098 {"lvsr", X(31,38), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5099 {"lvehx", X(31,39), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5100 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5102 {"mviwsplt", X(31,46), X_MASK
, E6500
, 0, {VD
, RA
, RB
}},
5104 {"iselgt", X(31,47), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
5106 {"lvewx", X(31,71), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5108 {"addg6s", XO(31,74,0,0), XO_MASK
, POWER6
, 0, {RT
, RA
, RB
}},
5110 {"lxsiwax", X(31,76), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
5112 {"iseleq", X(31,79), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
5114 {"isel", XISEL(31,15), XISEL_MASK
, PPCISEL
|TITAN
, 0, {RT
, RA0
, RB
, CRB
}},
5116 {"subf", XO(31,40,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5117 {"sub", XO(31,40,0,0), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
5118 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5119 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
5121 {"mfvsrd", X(31,51), XX1RB_MASK
, PPCVSX2
, 0, {RA
, XS6
}},
5122 {"mffprd", X(31,51), XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, FRS
}},
5123 {"mfvrd", X(31,51)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, VS
}},
5124 {"eratilx", X(31,51), X_MASK
, PPCA2
, 0, {ERAT_T
, RA
, RB
}},
5126 {"lbarx", X(31,52), XEH_MASK
, POWER8
|E6500
, 0, {RT
, RA0
, RB
, EH
}},
5128 {"ldux", X(31,53), X_MASK
, PPC64
, 0, {RT
, RAL
, RB
}},
5130 {"dcbst", X(31,54), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
5132 {"lwzux", X(31,55), X_MASK
, PPCCOM
, 0, {RT
, RAL
, RB
}},
5133 {"lux", X(31,55), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5135 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
5136 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
5138 {"andc", XRC(31,60,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5139 {"andc.", XRC(31,60,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5141 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
5142 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
5143 {"wait", X(31,62), XWC_MASK
, E500MC
|PPCA2
, 0, {WC
}},
5145 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
5147 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5148 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5149 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5150 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5151 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5152 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5153 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5154 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5155 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5156 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5157 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5158 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5159 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5160 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5161 {"tdu", XTO(31,68,TOU
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5162 {"td", X(31,68), X_MASK
, PPC64
, 0, {TO
, RA
, RB
}},
5164 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5165 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5166 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5168 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5169 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5171 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA
, RS
, RB
}},
5172 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA
, RS
, RB
}},
5174 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, 0, {SR
, RS
}},
5176 {"mfmsr", X(31,83), XRARB_MASK
, COM
, 0, {RT
}},
5178 {"ldarx", X(31,84), XEH_MASK
, PPC64
, 0, {RT
, RA0
, RB
, EH
}},
5180 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, PPC476
, {RA0
, RB
}},
5181 {"dcbf", X(31,86), XLRT_MASK
, PPC
, 0, {RA0
, RB
, L2OPT
}},
5183 {"lbzx", X(31,87), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
5185 {"lbepx", X(31,95), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5187 {"dni", XRC(31,97,1), XRB_MASK
, E6500
, 0, {DUI
, DCTL
}},
5189 {"lvx", X(31,103), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5190 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5192 {"neg", XO(31,104,0,0), XORB_MASK
, COM
, 0, {RT
, RA
}},
5193 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
, 0, {RT
, RA
}},
5195 {"mul", XO(31,107,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5196 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5198 {"mvidsplt", X(31,110), X_MASK
, E6500
, 0, {VD
, RA
, RB
}},
5200 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, 0, {RS
, RB
}},
5202 {"mffprwz", X(31,115), XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, FRS
}},
5203 {"mfvrwz", X(31,115)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, VS
}},
5204 {"mfvsrwz", X(31,115), XX1RB_MASK
, PPCVSX2
, 0, {RA
, XS6
}},
5206 {"lharx", X(31,116), XEH_MASK
, POWER8
|E6500
, 0, {RT
, RA0
, RB
, EH
}},
5208 {"clf", X(31,118), XTO_MASK
, POWER
, 0, {RA
, RB
}},
5210 {"lbzux", X(31,119), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
5212 {"popcntb", X(31,122), XRB_MASK
, POWER5
, 0, {RA
, RS
}},
5214 {"not", XRC(31,124,0), X_MASK
, COM
, 0, {RA
, RS
, RBS
}},
5215 {"nor", XRC(31,124,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5216 {"not.", XRC(31,124,1), X_MASK
, COM
, 0, {RA
, RS
, RBS
}},
5217 {"nor.", XRC(31,124,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5219 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
5221 {"setb", X(31,128), XRB_MASK
|(3<<16), POWER9
, 0, {RT
, BFA
}},
5223 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RS
}},
5225 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
5227 {"stvebx", X(31,135), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5228 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5230 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5231 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5232 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5233 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5235 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5236 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5237 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5238 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5240 {"stxsiwx", X(31,140), XX1_MASK
, PPCVSX2
, 0, {XS6
, RA0
, RB
}},
5242 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK
, POWER8
, 0, {RB
}},
5243 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
5245 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, 0, {RS
}},
5246 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
, 0, {FXM
, RS
}},
5247 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
, 0, {FXM
, RS
}},
5249 {"mtmsr", X(31,146), XRLARB_MASK
, COM
, 0, {RS
, A_L
}},
5251 {"mtsle", X(31,147), XRTLRARB_MASK
, POWER8
, 0, {L
}},
5253 {"eratsx", XRC(31,147,0), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
5254 {"eratsx.", XRC(31,147,1), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
5256 {"stdx", X(31,149), X_MASK
, PPC64
, 0, {RS
, RA0
, RB
}},
5258 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
, 0, {RS
, RA0
, RB
}},
5260 {"stwx", X(31,151), X_MASK
, PPCCOM
, 0, {RS
, RA0
, RB
}},
5261 {"stx", X(31,151), X_MASK
, PWRCOM
, 0, {RS
, RA
, RB
}},
5263 {"slq", XRC(31,152,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5264 {"slq.", XRC(31,152,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5266 {"sle", XRC(31,153,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5267 {"sle.", XRC(31,153,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5269 {"prtyw", X(31,154), XRB_MASK
, POWER6
|PPCA2
|PPC476
, 0, {RA
, RS
}},
5271 {"stdepx", X(31,157), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
5273 {"stwepx", X(31,159), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
5275 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {E
}},
5277 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
5279 {"stvehx", X(31,167), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5280 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5282 {"addex", ZRC(31,170,0), Z2_MASK
, POWER9
, 0, {RT
, RA
, RB
, CY
}},
5284 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK
, POWER8
, 0, {RB
}},
5285 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
5287 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, 0, {RS
, A_L
}},
5289 {"mtvsrd", X(31,179), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
5290 {"mtfprd", X(31,179), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
5291 {"mtvrd", X(31,179)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
5292 {"eratre", X(31,179), X_MASK
, PPCA2
, 0, {RT
, RA
, WS
}},
5294 {"stdux", X(31,181), X_MASK
, PPC64
, 0, {RS
, RAS
, RB
}},
5296 {"stqcx.", XRC(31,182,1), X_MASK
|Q_MASK
, POWER8
, 0, {RSQ
, RA0
, RB
}},
5297 {"wchkall", X(31,182), X_MASK
, PPCA2
, 0, {OBF
}},
5299 {"stwux", X(31,183), X_MASK
, PPCCOM
, 0, {RS
, RAS
, RB
}},
5300 {"stux", X(31,183), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
5302 {"sliq", XRC(31,184,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5303 {"sliq.", XRC(31,184,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5305 {"prtyd", X(31,186), XRB_MASK
, POWER6
|PPCA2
, 0, {RA
, RS
}},
5307 {"cmprb", X(31,192), XCMP_MASK
, POWER9
, 0, {BF
, L
, RA
, RB
}},
5309 {"icblq.", XRC(31,198,1), X_MASK
, E6500
, 0, {CT
, RA0
, RB
}},
5311 {"stvewx", X(31,199), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5312 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5314 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5315 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5316 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5317 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5319 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5320 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5321 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5322 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5324 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
, 0, {RB
}},
5326 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM
, NON32
, {SR
, RS
}},
5328 {"mtfprwa", X(31,211), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
5329 {"mtvrwa", X(31,211)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
5330 {"mtvsrwa", X(31,211), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
5331 {"eratwe", X(31,211), X_MASK
, PPCA2
, 0, {RS
, RA
, WS
}},
5333 {"ldawx.", XRC(31,212,1), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
5335 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
, 0, {RS
, RA0
, RB
}},
5337 {"stbx", X(31,215), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
5339 {"sllq", XRC(31,216,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5340 {"sllq.", XRC(31,216,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5342 {"sleq", XRC(31,217,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5343 {"sleq.", XRC(31,217,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5345 {"stbepx", X(31,223), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
5347 {"cmpeqb", X(31,224), XCMPL_MASK
, POWER9
, 0, {BF
, RA
, RB
}},
5349 {"icblc", X(31,230), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
5351 {"stvx", X(31,231), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5352 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5354 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5355 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5356 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5357 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5359 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5360 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5362 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5363 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5364 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5365 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5367 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5368 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5369 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5370 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5372 {"icblce", X(31,238), X_MASK
, PPCCHLK
, E500MC
|PPCA2
, {CT
, RA
, RB
}},
5373 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
, 0, {RB
}},
5374 {"mtsrin", X(31,242), XRA_MASK
, PPC
, NON32
, {RS
, RB
}},
5375 {"mtsri", X(31,242), XRA_MASK
, POWER
, NON32
, {RS
, RB
}},
5377 {"mtfprwz", X(31,243), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
5378 {"mtvrwz", X(31,243)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
5379 {"mtvsrwz", X(31,243), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
5381 {"dcbtstt", XRT(31,246,0x10), XRT_MASK
, POWER7
, 0, {RA0
, RB
}},
5382 {"dcbtst", X(31,246), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
5383 {"dcbtst", X(31,246), X_MASK
, DCBT_EO
, 0, {CT
, RA0
, RB
}},
5384 {"dcbtst", X(31,246), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
5386 {"stbux", X(31,247), X_MASK
, COM
, 0, {RS
, RAS
, RB
}},
5388 {"slliq", XRC(31,248,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5389 {"slliq.", XRC(31,248,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5391 {"bpermd", X(31,252), X_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
, RB
}},
5393 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5395 {"mfdcrx", X(31,259), X_MASK
, BOOKE
|PPCA2
|PPC476
, TITAN
, {RS
, RA
}},
5396 {"mfdcrx.", XRC(31,259,1), X_MASK
, PPCA2
, 0, {RS
, RA
}},
5398 {"lvexbx", X(31,261), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5400 {"icbt", X(31,262), XRT_MASK
, PPC403
, 0, {RA
, RB
}},
5402 {"lvepxl", X(31,263), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5404 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5405 {"doz", XO(31,264,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5406 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5408 {"modud", X(31,265), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
5410 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5411 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5412 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5413 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5415 {"moduw", X(31,267), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
5417 {"lxvx", X(31,268), XX1_MASK
|1<<6, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5418 {"lxvl", X(31,269), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5420 {"ehpriv", X(31,270), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
5422 {"tlbiel", X(31,274), X_MASK
|1<<20,POWER9
, 0, {RB
, RSO
, RIC
, PRS
, X_R
}},
5423 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, POWER9
|PPC476
, {RB
, LOPT
}},
5425 {"mfapidi", X(31,275), X_MASK
, BOOKE
, E500
|TITAN
, {RT
, RA
}},
5427 {"lqarx", X(31,276), XEH_MASK
|Q_MASK
, POWER8
, 0, {RTQ
, RAX
, RBX
, EH
}},
5429 {"lscbx", XRC(31,277,0), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
5430 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
5432 {"dcbtt", XRT(31,278,0x10), XRT_MASK
, POWER7
, 0, {RA0
, RB
}},
5433 {"dcbt", X(31,278), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
5434 {"dcbt", X(31,278), X_MASK
, DCBT_EO
, 0, {CT
, RA0
, RB
}},
5435 {"dcbt", X(31,278), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
5437 {"lhzx", X(31,279), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
5439 {"cdtbcd", X(31,282), XRB_MASK
, POWER6
, 0, {RA
, RS
}},
5441 {"eqv", XRC(31,284,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5442 {"eqv.", XRC(31,284,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5444 {"lhepx", X(31,287), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5446 {"mfdcrux", X(31,291), X_MASK
, PPC464
|PPC476
, 0, {RS
, RA
}},
5448 {"lvexhx", X(31,293), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5449 {"lvepx", X(31,295), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5451 {"lxvll", X(31,301), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5453 {"mfbhrbe", X(31,302), X_MASK
, POWER8
, 0, {RT
, BHRBE
}},
5455 {"tlbie", X(31,306), X_MASK
|1<<20,POWER9
, TITAN
, {RB
, RS
, RIC
, PRS
, X_R
}},
5456 {"tlbie", X(31,306), XRA_MASK
, POWER7
, POWER9
|TITAN
, {RB
, RS
}},
5457 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, E500
|POWER7
|TITAN
, {RB
, LOPT
}},
5458 {"tlbi", X(31,306), XRT_MASK
, POWER
, 0, {RA0
, RB
}},
5460 {"mfvsrld", X(31,307), XX1RB_MASK
, PPCVSX3
, 0, {RA
, XS6
}},
5462 {"ldmx", X(31,309), X_MASK
, POWER9
, 0, {RT
, RA0
, RB
}},
5464 {"eciwx", X(31,310), X_MASK
, PPC
, E500
|TITAN
, {RT
, RA0
, RB
}},
5466 {"lhzux", X(31,311), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
5468 {"cbcdtd", X(31,314), XRB_MASK
, POWER6
, 0, {RA
, RS
}},
5470 {"xor", XRC(31,316,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5471 {"xor.", XRC(31,316,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5473 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5475 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, 0, {RT
}},
5476 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, 0, {RT
}},
5477 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, 0, {RT
}},
5478 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, 0, {RT
}},
5479 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, 0, {RT
}},
5480 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, 0, {RT
}},
5481 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, 0, {RT
}},
5482 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, 0, {RT
}},
5483 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, 0, {RT
}},
5484 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, 0, {RT
}},
5485 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, 0, {RT
}},
5486 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, 0, {RT
}},
5487 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, 0, {RT
}},
5488 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, 0, {RT
}},
5489 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, 0, {RT
}},
5490 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, 0, {RT
}},
5491 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, 0, {RT
}},
5492 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, 0, {RT
}},
5493 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, 0, {RT
}},
5494 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, 0, {RT
}},
5495 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, 0, {RT
}},
5496 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, 0, {RT
}},
5497 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, 0, {RT
}},
5498 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, 0, {RT
}},
5499 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, 0, {RT
}},
5500 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, 0, {RT
}},
5501 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, 0, {RT
}},
5502 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, 0, {RT
}},
5503 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, 0, {RT
}},
5504 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, 0, {RT
}},
5505 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, 0, {RT
}},
5506 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, 0, {RT
}},
5507 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, 0, {RT
}},
5508 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, 0, {RT
}},
5509 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, E500
|TITAN
, {RT
, SPR
}},
5510 {"mfdcr.", XRC(31,323,1), X_MASK
, PPCA2
, 0, {RT
, SPR
}},
5512 {"lvexwx", X(31,325), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5514 {"dcread", X(31,326), X_MASK
, PPC476
|TITAN
, 0, {RT
, RA0
, RB
}},
5516 {"div", XO(31,331,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5517 {"div.", XO(31,331,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5519 {"lxvdsx", X(31,332), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
5521 {"mfpmr", X(31,334), X_MASK
, PPCPMR
|PPCE300
, 0, {RT
, PMR
}},
5522 {"mftmr", X(31,366), X_MASK
, PPCTMR
, 0, {RT
, TMR
}},
5524 {"slbsync", X(31,338), 0xffffffff, POWER9
, 0, {0}},
5526 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, 0, {RT
}},
5527 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
, 0, {RT
}},
5528 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, TITAN
, {RT
}},
5529 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, TITAN
, {RT
}},
5530 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, 0, {RT
}},
5531 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
, 0, {RT
}},
5532 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
, 0, {RT
}},
5533 {"mfdscr", XSPR(31,339, 17), XSPR_MASK
, POWER6
, 0, {RT
}},
5534 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, 0, {RT
}},
5535 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, TITAN
, {RT
}},
5536 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, TITAN
, {RT
}},
5537 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, MFDEC1
, {RT
}},
5538 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, 0, {RT
}},
5539 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, TITAN
, {RT
}},
5540 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, 0, {RT
}},
5541 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, 0, {RT
}},
5542 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, 0, {RT
}},
5543 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
, 0, {RT
}},
5544 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
, 0, {RT
}},
5545 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
, 0, {RT
}},
5546 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
, 0, {RT
}},
5547 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
, 0, {RT
}},
5548 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
, 0, {RT
}},
5549 {"mfctrl", XSPR(31,339,136), XSPR_MASK
, POWER4
, 0, {RT
}},
5550 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, 0, {RT
}},
5551 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, 0, {RT
}},
5552 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, 0, {RT
}},
5553 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, 0, {RT
}},
5554 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, 0, {RT
}},
5555 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, 0, {RT
}},
5556 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, 0, {RT
}},
5557 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, 0, {RT
}},
5558 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, 0, {RT
}},
5559 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, 0, {RT
}},
5560 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, 0, {RT
}},
5561 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, 0, {RT
}},
5562 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, 0, {RT
}},
5563 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, 0, {RT
}},
5564 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, 0, {RT
}},
5565 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, 0, {RT
}},
5566 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, 0, {RT
}},
5567 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
, 0, {RT
}},
5568 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
, 0, {RT
, SPRG
}},
5569 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5570 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5571 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5572 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5573 {"mftbu", XSPR(31,339,269), XSPR_MASK
, POWER4
|BOOKE
, 0, {RT
}},
5574 {"mftb", X(31,339), X_MASK
, POWER4
|BOOKE
, 0, {RT
, TBR
}},
5575 {"mftbl", XSPR(31,339,268), XSPR_MASK
, POWER4
|BOOKE
, 0, {RT
}},
5576 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
, 0, {RT
}},
5577 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
, 0, {RT
}},
5578 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
, 0, {RT
}},
5579 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
, 0, {RT
}},
5580 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, 0, {RT
}},
5581 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, TITAN
, {RT
}},
5582 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
, 0, {RT
}},
5583 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
, 0, {RT
}},
5584 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
, 0, {RT
}},
5585 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
, 0, {RT
}},
5586 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
, 0, {RT
}},
5587 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
, 0, {RT
}},
5588 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
, 0, {RT
}},
5589 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
, 0, {RT
}},
5590 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
, 0, {RT
}},
5591 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
, 0, {RT
}},
5592 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
, 0, {RT
}},
5593 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
, 0, {RT
}},
5594 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
, 0, {RT
}},
5595 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
, 0, {RT
}},
5596 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
, 0, {RT
}},
5597 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
, 0, {RT
}},
5598 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
, 0, {RT
}},
5599 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
, 0, {RT
}},
5600 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
, 0, {RT
}},
5601 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
, 0, {RT
}},
5602 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
, 0, {RT
}},
5603 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
, 0, {RT
}},
5604 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
, 0, {RT
}},
5605 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
, 0, {RT
}},
5606 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
, 0, {RT
}},
5607 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
, 0, {RT
}},
5608 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
, 0, {RT
}},
5609 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
, 0, {RT
}},
5610 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
, 0, {RT
}},
5611 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
, 0, {RT
}},
5612 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
, 0, {RT
}},
5613 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
, 0, {RT
}},
5614 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, 0, {RT
}},
5615 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, 0, {RT
}},
5616 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, 0, {RT
}},
5617 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
|E6500
, 0, {RT
}},
5618 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
|E6500
, 0, {RT
}},
5619 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, 0, {RT
}},
5620 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, 0, {RT
}},
5621 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5622 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5623 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5624 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5625 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, 0, {RT
}},
5626 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, 0, {RT
}},
5627 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, 0, {RT
}},
5628 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, 0, {RT
}},
5629 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, 0, {RT
}},
5630 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, 0, {RT
}},
5631 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
5632 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
5633 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
5634 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, TITAN
, {RT
}},
5635 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, 0, {RT
}},
5636 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, 0, {RT
}},
5637 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, 0, {RT
}},
5638 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, 0, {RT
}},
5639 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, 0, {RT
}},
5640 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, 0, {RT
}},
5641 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, 0, {RT
}},
5642 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, 0, {RT
}},
5643 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, 0, {RT
}},
5644 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, 0, {RT
}},
5645 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, 0, {RT
}},
5646 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, 0, {RT
}},
5647 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, 0, {RT
}},
5648 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, 0, {RT
}},
5649 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, 0, {RT
}},
5650 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, 0, {RT
}},
5651 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, 0, {RT
}},
5652 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, 0, {RT
}},
5653 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, 0, {RT
}},
5654 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, 0, {RT
}},
5655 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, 0, {RT
}},
5656 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, 0, {RT
}},
5657 {"mfivndx", XSPR(31,339,880), XSPR_MASK
, TITAN
, 0, {RT
}},
5658 {"mfdvndx", XSPR(31,339,881), XSPR_MASK
, TITAN
, 0, {RT
}},
5659 {"mfivlim", XSPR(31,339,882), XSPR_MASK
, TITAN
, 0, {RT
}},
5660 {"mfdvlim", XSPR(31,339,883), XSPR_MASK
, TITAN
, 0, {RT
}},
5661 {"mfclcsr", XSPR(31,339,884), XSPR_MASK
, TITAN
, 0, {RT
}},
5662 {"mfccr1", XSPR(31,339,888), XSPR_MASK
, TITAN
, 0, {RT
}},
5663 {"mfppr", XSPR(31,339,896), XSPR_MASK
, POWER7
, 0, {RT
}},
5664 {"mfppr32", XSPR(31,339,898), XSPR_MASK
, POWER7
, 0, {RT
}},
5665 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK
, TITAN
, 0, {RT
}},
5666 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK
, TITAN
, 0, {RT
}},
5667 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK
, TITAN
, 0, {RT
}},
5668 {"mficdbtr", XSPR(31,339,927), XSPR_MASK
, TITAN
, 0, {RT
}},
5669 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, 0, {RT
}},
5670 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, 0, {RT
}},
5671 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, 0, {RT
}},
5672 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, 0, {RT
}},
5673 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, 0, {RT
}},
5674 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, 0, {RT
}},
5675 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, 0, {RT
}},
5676 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, 0, {RT
}},
5677 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, 0, {RT
}},
5678 {"mfmmucr", XSPR(31,339,946), XSPR_MASK
, TITAN
, 0, {RT
}},
5679 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
|TITAN
, 0, {RT
}},
5680 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, 0, {RT
}},
5681 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, 0, {RT
}},
5682 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, 0, {RT
}},
5683 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, 0, {RT
}},
5684 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, 0, {RT
}},
5685 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, 0, {RT
}},
5686 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, 0, {RT
}},
5687 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, 0, {RT
}},
5688 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, 0, {RT
}},
5689 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, 0, {RT
}},
5690 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, 0, {RT
}},
5691 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, 0, {RT
}},
5692 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, 0, {RT
}},
5693 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, 0, {RT
}},
5694 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, 0, {RT
}},
5695 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, 0, {RT
}},
5696 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
|TITAN
, 0, {RT
}},
5697 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, 0, {RT
}},
5698 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, 0, {RT
}},
5699 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, 0, {RT
}},
5700 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, 0, {RT
}},
5701 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, 0, {RT
}},
5702 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, 0, {RT
}},
5703 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, 0, {RT
}},
5704 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, 0, {RT
}},
5705 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, 0, {RT
}},
5706 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, 0, {RT
}},
5707 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, 0, {RT
}},
5708 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, 0, {RT
}},
5709 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, 0, {RT
}},
5710 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK
, TITAN
, 0, {RS
}},
5711 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, 0, {RT
}},
5712 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, 0, {RT
}},
5713 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, 0, {RT
}},
5714 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, 0, {RT
}},
5715 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, 0, {RT
}},
5716 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, 0, {RT
}},
5717 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, 0, {RT
}},
5718 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, 0, {RT
}},
5719 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, 0, {RT
}},
5720 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, 0, {RT
}},
5721 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, 0, {RT
}},
5722 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, 0, {RT
}},
5723 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, 0, {RT
}},
5724 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, 0, {RT
}},
5725 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, 0, {RT
}},
5726 {"mfspr", X(31,339), X_MASK
, COM
, 0, {RT
, SPR
}},
5728 {"lwax", X(31,341), X_MASK
, PPC64
, 0, {RT
, RA0
, RB
}},
5730 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
5732 {"lhax", X(31,343), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
5734 {"lvxl", X(31,359), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5736 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
5737 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
5739 {"divs", XO(31,363,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5740 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5742 {"lxvwsx", X(31,364), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5744 {"tlbia", X(31,370), 0xffffffff, PPC
, E500
|TITAN
, {0}},
5746 {"mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, NO371
|POWER4
, {RT
}},
5747 {"mftb", X(31,371), X_MASK
, PPC
, NO371
|POWER4
, {RT
, TBR
}},
5748 {"mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, NO371
|POWER4
, {RT
}},
5750 {"lwaux", X(31,373), X_MASK
, PPC64
, 0, {RT
, RAL
, RB
}},
5752 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
5754 {"lhaux", X(31,375), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
5756 {"popcntw", X(31,378), XRB_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
}},
5758 {"mtdcrx", X(31,387), X_MASK
, BOOKE
|PPCA2
|PPC476
, TITAN
, {RA
, RS
}},
5759 {"mtdcrx.", XRC(31,387,1), X_MASK
, PPCA2
, 0, {RA
, RS
}},
5761 {"stvexbx", X(31,389), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
5763 {"dcblc", X(31,390), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
5764 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5766 {"divdeu", XO(31,393,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
5767 {"divdeu.", XO(31,393,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
5768 {"divweu", XO(31,395,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
5769 {"divweu.", XO(31,395,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
5771 {"stxvx", X(31,396), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
5772 {"stxvl", X(31,397), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
5774 {"dcblce", X(31,398), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
5776 {"slbmte", X(31,402), XRA_MASK
, PPC64
, 0, {RS
, RB
}},
5778 {"mtvsrws", X(31,403), XX1RB_MASK
, PPCVSX3
, 0, {XT6
, RA
}},
5780 {"pbt.", XRC(31,404,1), X_MASK
, POWER8
, 0, {RS
, RA0
, RB
}},
5782 {"icswx", XRC(31,406,0), X_MASK
, POWER7
|PPCA2
, 0, {RS
, RA
, RB
}},
5783 {"icswx.", XRC(31,406,1), X_MASK
, POWER7
|PPCA2
, 0, {RS
, RA
, RB
}},
5785 {"sthx", X(31,407), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
5787 {"orc", XRC(31,412,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5788 {"orc.", XRC(31,412,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5790 {"sthepx", X(31,415), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
5792 {"mtdcrux", X(31,419), X_MASK
, PPC464
|PPC476
, 0, {RA
, RS
}},
5794 {"stvexhx", X(31,421), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
5796 {"dcblq.", XRC(31,422,1), X_MASK
, E6500
, 0, {CT
, RA0
, RB
}},
5798 {"divde", XO(31,425,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
5799 {"divde.", XO(31,425,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
5800 {"divwe", XO(31,427,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
5801 {"divwe.", XO(31,427,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
5803 {"stxvll", X(31,429), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
5805 {"clrbhrb", X(31,430), 0xffffffff, POWER8
, 0, {0}},
5807 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, 0, {RB
}},
5809 {"mtvsrdd", X(31,435), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5811 {"ecowx", X(31,438), X_MASK
, PPC
, E500
|TITAN
, {RT
, RA0
, RB
}},
5813 {"sthux", X(31,439), X_MASK
, COM
, 0, {RS
, RAS
, RB
}},
5815 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, 0, {0}},
5817 {"miso", 0x7f5ad378, 0xffffffff, E6500
, 0, {0}},
5819 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5820 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5821 {"yield", 0x7f7bdb78, 0xffffffff, POWER7
, 0, {0}},
5822 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7
, 0, {0}},
5823 {"mdoom", 0x7fdef378, 0xffffffff, POWER7
, 0, {0}},
5824 {"mr", XRC(31,444,0), X_MASK
, COM
, 0, {RA
, RS
, RBS
}},
5825 {"or", XRC(31,444,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5826 {"mr.", XRC(31,444,1), X_MASK
, COM
, 0, {RA
, RS
, RBS
}},
5827 {"or.", XRC(31,444,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5829 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, 0, {RS
}},
5830 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, 0, {RS
}},
5831 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, 0, {RS
}},
5832 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, 0, {RS
}},
5833 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, 0, {RS
}},
5834 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, 0, {RS
}},
5835 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, 0, {RS
}},
5836 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, 0, {RS
}},
5837 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, 0, {RS
}},
5838 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, 0, {RS
}},
5839 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, 0, {RS
}},
5840 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, 0, {RS
}},
5841 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, 0, {RS
}},
5842 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, 0, {RS
}},
5843 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, 0, {RS
}},
5844 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, 0, {RS
}},
5845 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, 0, {RS
}},
5846 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, 0, {RS
}},
5847 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, 0, {RS
}},
5848 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, 0, {RS
}},
5849 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, 0, {RS
}},
5850 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, 0, {RS
}},
5851 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, 0, {RS
}},
5852 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, 0, {RS
}},
5853 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, 0, {RS
}},
5854 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, 0, {RS
}},
5855 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, 0, {RS
}},
5856 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, 0, {RS
}},
5857 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, 0, {RS
}},
5858 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, 0, {RS
}},
5859 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, 0, {RS
}},
5860 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, 0, {RS
}},
5861 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, 0, {RS
}},
5862 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, 0, {RS
}},
5863 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, E500
|TITAN
, {SPR
, RS
}},
5864 {"mtdcr.", XRC(31,451,1), X_MASK
, PPCA2
, 0, {SPR
, RS
}},
5866 {"stvexwx", X(31,453), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
5868 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCA2
, 0, {RAOPT
, RBOPT
}},
5869 {"dci", X(31,454), XRARB_MASK
, PPCA2
|PPC476
, 0, {CT
}},
5871 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5872 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5874 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5875 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5877 {"mtpmr", X(31,462), X_MASK
, PPCPMR
|PPCE300
, 0, {PMR
, RS
}},
5878 {"mttmr", X(31,494), X_MASK
, PPCTMR
, 0, {TMR
, RS
}},
5880 {"slbieg", X(31,466), XRA_MASK
, POWER9
, 0, {RS
, RB
}},
5882 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, 0, {RS
}},
5883 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
, 0, {RS
}},
5884 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
, 0, {RS
}},
5885 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
, 0, {RS
}},
5886 {"mtdscr", XSPR(31,467, 17), XSPR_MASK
, POWER6
, 0, {RS
}},
5887 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, 0, {RS
}},
5888 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, TITAN
, {RS
}},
5889 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, TITAN
, {RS
}},
5890 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, TITAN
, {RS
}},
5891 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, TITAN
, {RS
}},
5892 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, 0, {RS
}},
5893 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, 0, {RS
}},
5894 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, TITAN
, {RS
}},
5895 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
, 0, {RS
}},
5896 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
, 0, {RS
}},
5897 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, 0, {RS
}},
5898 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
, 0, {RS
}},
5899 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
, 0, {RS
}},
5900 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
, 0, {RS
}},
5901 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
, 0, {RS
}},
5902 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
, 0, {RS
}},
5903 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
, 0, {RS
}},
5904 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
, 0, {RS
}},
5905 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, 0, {RS
}},
5906 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, 0, {RS
}},
5907 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, 0, {RS
}},
5908 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, 0, {RS
}},
5909 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, 0, {RS
}},
5910 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, 0, {RS
}},
5911 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, 0, {RS
}},
5912 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, 0, {RS
}},
5913 {"mtctrl", XSPR(31,467,152), XSPR_MASK
, POWER4
, 0, {RS
}},
5914 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, 0, {RS
}},
5915 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, 0, {RS
}},
5916 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, 0, {RS
}},
5917 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, 0, {RS
}},
5918 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, 0, {RS
}},
5919 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, 0, {RS
}},
5920 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, 0, {RS
}},
5921 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, 0, {RS
}},
5922 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, 0, {RS
}},
5923 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
, 0, {RS
}},
5924 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
, PPC
, 0, {SPRG
, RS
}},
5925 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
, 0, {RS
}},
5926 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
, 0, {RS
}},
5927 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
, 0, {RS
}},
5928 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
, 0, {RS
}},
5929 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
5930 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
5931 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
5932 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
5933 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, 0, {RS
}},
5934 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, TITAN
, {RS
}},
5935 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, 0, {RS
}},
5936 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, 0, {RS
}},
5937 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
, 0, {RS
}},
5938 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
, 0, {RS
}},
5939 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
, 0, {RS
}},
5940 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
, 0, {RS
}},
5941 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
, 0, {RS
}},
5942 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
, 0, {RS
}},
5943 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
, 0, {RS
}},
5944 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
, 0, {RS
}},
5945 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
, 0, {RS
}},
5946 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
, 0, {RS
}},
5947 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
, 0, {RS
}},
5948 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
, 0, {RS
}},
5949 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
, 0, {RS
}},
5950 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
, 0, {RS
}},
5951 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
, 0, {RS
}},
5952 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
, 0, {RS
}},
5953 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
, 0, {RS
}},
5954 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
, 0, {RS
}},
5955 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
, 0, {RS
}},
5956 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
, 0, {RS
}},
5957 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
, 0, {RS
}},
5958 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
, 0, {RS
}},
5959 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
, 0, {RS
}},
5960 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
, 0, {RS
}},
5961 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
, 0, {RS
}},
5962 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
, 0, {RS
}},
5963 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
, 0, {RS
}},
5964 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
, 0, {RS
}},
5965 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
, 0, {RS
}},
5966 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
, 0, {RS
}},
5967 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, 0, {RS
}},
5968 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, 0, {RS
}},
5969 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, 0, {RS
}},
5970 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
|E6500
, 0, {RS
}},
5971 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
|E6500
, 0, {RS
}},
5972 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, 0, {RS
}},
5973 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, 0, {RS
}},
5974 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5975 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5976 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5977 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5978 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
5979 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
5980 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
5981 {"mtivndx", XSPR(31,467,880), XSPR_MASK
, TITAN
, 0, {RS
}},
5982 {"mtdvndx", XSPR(31,467,881), XSPR_MASK
, TITAN
, 0, {RS
}},
5983 {"mtivlim", XSPR(31,467,882), XSPR_MASK
, TITAN
, 0, {RS
}},
5984 {"mtdvlim", XSPR(31,467,883), XSPR_MASK
, TITAN
, 0, {RS
}},
5985 {"mtclcsr", XSPR(31,467,884), XSPR_MASK
, TITAN
, 0, {RS
}},
5986 {"mtccr1", XSPR(31,467,888), XSPR_MASK
, TITAN
, 0, {RS
}},
5987 {"mtppr", XSPR(31,467,896), XSPR_MASK
, POWER7
, 0, {RS
}},
5988 {"mtppr32", XSPR(31,467,898), XSPR_MASK
, POWER7
, 0, {RS
}},
5989 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, 0, {RS
}},
5990 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, 0, {RS
}},
5991 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, 0, {RS
}},
5992 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, 0, {RS
}},
5993 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, 0, {RS
}},
5994 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, 0, {RS
}},
5995 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, 0, {RS
}},
5996 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, 0, {RS
}},
5997 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, 0, {RS
}},
5998 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK
, TITAN
, 0, {RS
}},
5999 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
|TITAN
, 0, {RS
}},
6000 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, 0, {RS
}},
6001 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, 0, {RS
}},
6002 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, 0, {RS
}},
6003 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, 0, {RS
}},
6004 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, 0, {RS
}},
6005 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, 0, {RS
}},
6006 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, 0, {RS
}},
6007 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, 0, {RS
}},
6008 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, 0, {RS
}},
6009 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, 0, {RS
}},
6010 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, 0, {RS
}},
6011 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, 0, {RS
}},
6012 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, 0, {RS
}},
6013 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, 0, {RS
}},
6014 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, 0, {RS
}},
6015 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, 0, {RS
}},
6016 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, 0, {RS
}},
6017 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, 0, {RS
}},
6018 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, 0, {RS
}},
6019 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, 0, {RS
}},
6020 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, 0, {RS
}},
6021 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, 0, {RS
}},
6022 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, 0, {RS
}},
6023 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, 0, {RS
}},
6024 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, 0, {RS
}},
6025 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, 0, {RS
}},
6026 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, 0, {RS
}},
6027 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, 0, {RS
}},
6028 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, 0, {RS
}},
6029 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK
, TITAN
, 0, {RS
}},
6030 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, 0, {RS
}},
6031 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, 0, {RS
}},
6032 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, 0, {RS
}},
6033 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, 0, {RS
}},
6034 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, 0, {RS
}},
6035 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, 0, {RS
}},
6036 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, 0, {RS
}},
6037 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, 0, {RS
}},
6038 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, 0, {RS
}},
6039 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, 0, {RS
}},
6040 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, 0, {RS
}},
6041 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, 0, {RS
}},
6042 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, 0, {RS
}},
6043 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, 0, {RS
}},
6044 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, 0, {RS
}},
6045 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, 0, {RS
}},
6046 {"mtspr", X(31,467), X_MASK
, COM
, 0, {SPR
, RS
}},
6048 {"dcbi", X(31,470), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6050 {"nand", XRC(31,476,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6051 {"nand.", XRC(31,476,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6053 {"dsn", X(31,483), XRT_MASK
, E500MC
, 0, {RA
, RB
}},
6055 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
, PPCA2
, {RT
, RA0
, RB
}},
6057 {"icbtls", X(31,486), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
6059 {"stvxl", X(31,487), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
6061 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6062 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6064 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6065 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6067 {"divw", XO(31,491,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6068 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6070 {"icbtlse", X(31,494), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
6072 {"slbia", X(31,498), 0xff1fffff, POWER6
, 0, {IH
}},
6073 {"slbia", X(31,498), 0xffffffff, PPC64
, POWER6
, {0}},
6075 {"cli", X(31,502), XRB_MASK
, POWER
, 0, {RT
, RA
}},
6077 {"popcntd", X(31,506), XRB_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
}},
6079 {"cmpb", X(31,508), X_MASK
, POWER6
|PPCA2
|PPC476
, 0, {RA
, RS
, RB
}},
6081 {"mcrxr", X(31,512), XBFRARB_MASK
, COM
, POWER7
, {BF
}},
6083 {"lbdcbx", X(31,514), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
6084 {"lbdx", X(31,515), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
6086 {"bblels", X(31,518), X_MASK
, PPCBRLK
, 0, {0}},
6088 {"lvlx", X(31,519), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6089 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6091 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6092 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6093 {"subco", XO(31,8,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
6094 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6095 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6096 {"subco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
6098 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6099 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6100 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6101 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6103 {"lxsspx", X(31,524), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
6105 {"clcs", X(31,531), XRB_MASK
, M601
, 0, {RT
, RA
}},
6107 {"ldbrx", X(31,532), X_MASK
, CELL
|POWER7
|PPCA2
, 0, {RT
, RA0
, RB
}},
6109 {"lswx", X(31,533), X_MASK
, PPCCOM
, E500
|E500MC
, {RT
, RAX
, RBX
}},
6110 {"lsx", X(31,533), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6112 {"lwbrx", X(31,534), X_MASK
, PPCCOM
, 0, {RT
, RA0
, RB
}},
6113 {"lbrx", X(31,534), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6115 {"lfsx", X(31,535), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
6117 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6118 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6119 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6120 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6122 {"rrib", XRC(31,537,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6123 {"rrib.", XRC(31,537,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6125 {"cnttzw", XRC(31,538,0), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6126 {"cnttzw.", XRC(31,538,1), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6128 {"srd", XRC(31,539,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6129 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6131 {"maskir", XRC(31,541,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6132 {"maskir.", XRC(31,541,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6134 {"lhdcbx", X(31,546), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
6135 {"lhdx", X(31,547), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
6137 {"lvtrx", X(31,549), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6139 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, 0, {0}},
6141 {"lvrx", X(31,551), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6142 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6144 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6145 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
6146 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6147 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
6149 {"tlbsync", X(31,566), 0xffffffff, PPC
, 0, {0}},
6151 {"lfsux", X(31,567), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
6153 {"cnttzd", XRC(31,570,0), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6154 {"cnttzd.", XRC(31,570,1), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6156 {"mcrxrx", X(31,576), XBFRARB_MASK
, POWER9
, 0, {BF
}},
6158 {"lwdcbx", X(31,578), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
6159 {"lwdx", X(31,579), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
6161 {"lvtlx", X(31,581), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6163 {"lwat", X(31,582), X_MASK
, POWER9
, 0, {RT
, RA0
, FC
}},
6165 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6167 {"lxsdx", X(31,588), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
6169 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM
, NON32
, {RT
, SR
}},
6171 {"lswi", X(31,597), X_MASK
, PPCCOM
, E500
|E500MC
, {RT
, RAX
, NBI
}},
6172 {"lsi", X(31,597), X_MASK
, PWRCOM
, 0, {RT
, RA0
, NB
}},
6174 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4
, BOOKE
|PPC476
, {0}},
6175 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, E500
, {0}},
6176 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, 0, {0}},
6177 {"sync", X(31,598), XSYNCLE_MASK
, E6500
, 0, {LS
, ESYNC
}},
6178 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
, BOOKE
|PPC476
, {LS
}},
6179 {"msync", X(31,598), 0xffffffff, BOOKE
|PPCA2
|PPC476
, 0, {0}},
6180 {"sync", X(31,598), 0xffffffff, BOOKE
|PPC476
, E6500
, {0}},
6181 {"lwsync", X(31,598), 0xffffffff, E500
, 0, {0}},
6182 {"dcs", X(31,598), 0xffffffff, PWRCOM
, 0, {0}},
6184 {"lfdx", X(31,599), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
6186 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, POWER7
, {FRT
, RB
}},
6187 {"lfdepx", X(31,607), X_MASK
, E500MC
|PPCA2
, 0, {FRT
, RA0
, RB
}},
6189 {"lddx", X(31,611), X_MASK
, E500MC
, 0, {RT
, RA
, RB
}},
6191 {"lvswx", X(31,613), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6193 {"ldat", X(31,614), X_MASK
, POWER9
, 0, {RT
, RA0
, FC
}},
6195 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6197 {"nego", XO(31,104,1,0), XORB_MASK
, COM
, 0, {RT
, RA
}},
6198 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
, 0, {RT
, RA
}},
6200 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6201 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6203 {"mfsri", X(31,627), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
6205 {"dclst", X(31,630), XRB_MASK
, M601
, 0, {RS
, RA
}},
6207 {"lfdux", X(31,631), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
6209 {"stbdcbx", X(31,642), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
6210 {"stbdx", X(31,643), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
6212 {"stvlx", X(31,647), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6213 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6215 {"stxsspx", X(31,652), XX1_MASK
, PPCVSX2
, 0, {XS6
, RA0
, RB
}},
6217 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK
, PPCHTM
, 0, {HTM_R
}},
6219 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6220 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6221 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6222 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6224 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6225 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6226 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6227 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6229 {"mfsrin", X(31,659), XRA_MASK
, PPC
, NON32
, {RT
, RB
}},
6231 {"stdbrx", X(31,660), X_MASK
, CELL
|POWER7
|PPCA2
, 0, {RS
, RA0
, RB
}},
6233 {"stswx", X(31,661), X_MASK
, PPCCOM
, E500
|E500MC
, {RS
, RA0
, RB
}},
6234 {"stsx", X(31,661), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
6236 {"stwbrx", X(31,662), X_MASK
, PPCCOM
, 0, {RS
, RA0
, RB
}},
6237 {"stbrx", X(31,662), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
6239 {"stfsx", X(31,663), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
6241 {"srq", XRC(31,664,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6242 {"srq.", XRC(31,664,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6244 {"sre", XRC(31,665,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6245 {"sre.", XRC(31,665,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6247 {"sthdcbx", X(31,674), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
6248 {"sthdx", X(31,675), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
6250 {"stvfrx", X(31,677), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6252 {"stvrx", X(31,679), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6253 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6255 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK
, PPCHTM
, 0, {0}},
6256 {"tend.", XRC(31,686,1), XRTARARB_MASK
, PPCHTM
, 0, {HTM_A
}},
6258 {"stbcx.", XRC(31,694,1), X_MASK
, POWER8
|E6500
, 0, {RS
, RA0
, RB
}},
6260 {"stfsux", X(31,695), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
6262 {"sriq", XRC(31,696,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6263 {"sriq.", XRC(31,696,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6265 {"stwdcbx", X(31,706), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
6266 {"stwdx", X(31,707), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
6268 {"stvflx", X(31,709), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6270 {"stwat", X(31,710), X_MASK
, POWER9
, 0, {RS
, RA0
, FC
}},
6272 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6274 {"stxsdx", X(31,716), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
6276 {"tcheck", X(31,718), XRTBFRARB_MASK
, PPCHTM
, 0, {BF
}},
6278 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6279 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6280 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6281 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6283 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6284 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6285 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6286 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6288 {"stswi", X(31,725), X_MASK
, PPCCOM
, E500
|E500MC
, {RS
, RA0
, NB
}},
6289 {"stsi", X(31,725), X_MASK
, PWRCOM
, 0, {RS
, RA0
, NB
}},
6291 {"sthcx.", XRC(31,726,1), X_MASK
, POWER8
|E6500
, 0, {RS
, RA0
, RB
}},
6293 {"stfdx", X(31,727), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
6295 {"srlq", XRC(31,728,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6296 {"srlq.", XRC(31,728,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6298 {"sreq", XRC(31,729,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6299 {"sreq.", XRC(31,729,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6301 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, POWER7
, {RT
, FRB
}},
6302 {"stfdepx", X(31,735), X_MASK
, E500MC
|PPCA2
, 0, {FRS
, RA0
, RB
}},
6304 {"stddx", X(31,739), X_MASK
, E500MC
, 0, {RS
, RA
, RB
}},
6306 {"stvswx", X(31,741), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6308 {"stdat", X(31,742), X_MASK
, POWER9
, 0, {RS
, RA0
, FC
}},
6310 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6312 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6313 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6314 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6315 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6317 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6318 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6320 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6321 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6322 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6323 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6325 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6326 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6327 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6328 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6330 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
6331 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
6332 {"tsr.", XRC(31,750,1), XRTLRARB_MASK
,PPCHTM
, 0, {L
}},
6334 {"darn", X(31,755), XLRAND_MASK
, POWER9
, 0, {RT
, LRAND
}},
6336 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
|PPCA2
|PPC476
, 0, {RA0
, RB
}},
6337 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, 0, {RA0
, RB
}},
6339 {"stfdux", X(31,759), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
6341 {"srliq", XRC(31,760,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6342 {"srliq.", XRC(31,760,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6344 {"lvsm", X(31,773), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6346 {"copy", XOPL(31,774,1), XRT_MASK
, POWER9
, 0, {RA0
, RB
}},
6348 {"stvepxl", X(31,775), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6349 {"lvlxl", X(31,775), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6350 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6352 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6353 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6355 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6356 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6357 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6358 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6360 {"modsd", X(31,777), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
6361 {"modsw", X(31,779), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
6363 {"lxvw4x", X(31,780), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
6364 {"lxsibzx", X(31,781), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6366 {"tabortwc.", XRC(31,782,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, RB
}},
6368 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
|PPCA2
|PPC476
, 0, {RA0
, RB
}},
6370 {"lwzcix", X(31,789), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6372 {"lhbrx", X(31,790), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
6374 {"lfdpx", X(31,791), X_MASK
|Q_MASK
, POWER6
, POWER7
, {FRTp
, RA0
, RB
}},
6375 {"lfqx", X(31,791), X_MASK
, POWER2
, 0, {FRT
, RA
, RB
}},
6377 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6378 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6379 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6380 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6382 {"srad", XRC(31,794,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6383 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6385 {"lfddx", X(31,803), X_MASK
, E500MC
, 0, {FRT
, RA
, RB
}},
6387 {"lvtrxl", X(31,805), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6388 {"stvepx", X(31,807), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6389 {"lvrxl", X(31,807), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6391 {"lxvh8x", X(31,812), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6392 {"lxsihzx", X(31,813), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6394 {"tabortdc.", XRC(31,814,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, RB
}},
6396 {"rac", X(31,818), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
6398 {"erativax", X(31,819), X_MASK
, PPCA2
, 0, {RS
, RA0
, RB
}},
6400 {"lhzcix", X(31,821), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6402 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, 0, {STRM
}},
6404 {"lfqux", X(31,823), X_MASK
, POWER2
, 0, {FRT
, RA
, RB
}},
6406 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, SH
}},
6407 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, SH
}},
6408 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, SH
}},
6409 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, SH
}},
6411 {"sradi", XS(31,413,0), XS_MASK
, PPC64
, 0, {RA
, RS
, SH6
}},
6412 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
, 0, {RA
, RS
, SH6
}},
6414 {"lvtlxl", X(31,837), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6416 {"cpabort", X(31,838), XRTRARB_MASK
,POWER9
, 0, {0}},
6418 {"divo", XO(31,331,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6419 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6421 {"lxvd2x", X(31,844), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
6422 {"lxvx", X(31,844), XX1_MASK
, POWER8
, POWER9
|PPCVSX3
, {XT6
, RA0
, RB
}},
6424 {"tabortwci.", XRC(31,846,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, HTM_SI
}},
6426 {"tlbsrx.", XRC(31,850,1), XRT_MASK
, PPCA2
, 0, {RA0
, RB
}},
6428 {"slbiag", X(31,850), XRARB_MASK
, POWER9
, 0, {RS
}},
6429 {"slbmfev", X(31,851), XRLA_MASK
, POWER9
, 0, {RT
, RB
, A_L
}},
6430 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, POWER9
, {RT
, RB
}},
6432 {"lbzcix", X(31,853), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6434 {"eieio", X(31,854), 0xffffffff, PPC
, BOOKE
|PPCA2
|PPC476
, {0}},
6435 {"mbar", X(31,854), X_MASK
, BOOKE
|PPCA2
|PPC476
, 0, {MO
}},
6436 {"eieio", XMBAR(31,854,1),0xffffffff, E500
, 0, {0}},
6437 {"eieio", X(31,854), 0xffffffff, PPCA2
|PPC476
, 0, {0}},
6439 {"lfiwax", X(31,855), X_MASK
, POWER6
|PPCA2
|PPC476
, 0, {FRT
, RA0
, RB
}},
6441 {"lvswxl", X(31,869), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6443 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6444 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6446 {"divso", XO(31,363,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6447 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6449 {"lxvb16x", X(31,876), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6451 {"tabortdci.", XRC(31,878,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, HTM_SI
}},
6453 {"rmieg", X(31,882), XRTRA_MASK
, POWER9
, 0, {RB
}},
6455 {"ldcix", X(31,885), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6457 {"msgsync", X(31,886), 0xffffffff, POWER9
, 0, {0}},
6459 {"lfiwzx", X(31,887), X_MASK
, POWER7
|PPCA2
, 0, {FRT
, RA0
, RB
}},
6461 {"extswsli", XS(31,445,0), XS_MASK
, POWER9
, 0, {RA
, RS
, SH6
}},
6462 {"extswsli.", XS(31,445,1), XS_MASK
, POWER9
, 0, {RA
, RS
, SH6
}},
6464 {"paste.", XRCL(31,902,1,1),XRT_MASK
, POWER9
, 0, {RA0
, RB
}},
6466 {"stvlxl", X(31,903), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6467 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6469 {"divdeuo", XO(31,393,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6470 {"divdeuo.", XO(31,393,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6471 {"divweuo", XO(31,395,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6472 {"divweuo.", XO(31,395,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6474 {"stxvw4x", X(31,908), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
6475 {"stxsibx", X(31,909), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6477 {"tabort.", XRC(31,910,1), XRTRB_MASK
, PPCHTM
, 0, {RA
}},
6479 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RTO
, RA0
, RB
}},
6480 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RTO
, RA0
, RB
}},
6482 {"slbmfee", X(31,915), XRLA_MASK
, POWER9
, 0, {RT
, RB
, A_L
}},
6483 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, POWER9
, {RT
, RB
}},
6485 {"stwcix", X(31,917), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6487 {"sthbrx", X(31,918), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
6489 {"stfdpx", X(31,919), X_MASK
|Q_MASK
, POWER6
, POWER7
, {FRSp
, RA0
, RB
}},
6490 {"stfqx", X(31,919), X_MASK
, POWER2
, 0, {FRS
, RA0
, RB
}},
6492 {"sraq", XRC(31,920,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6493 {"sraq.", XRC(31,920,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6495 {"srea", XRC(31,921,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6496 {"srea.", XRC(31,921,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6498 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
6499 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
6500 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
6501 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
6503 {"stfddx", X(31,931), X_MASK
, E500MC
, 0, {FRS
, RA
, RB
}},
6505 {"stvfrxl", X(31,933), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6507 {"wclrone", XOPL2(31,934,2),XRT_MASK
, PPCA2
, 0, {RA0
, RB
}},
6508 {"wclrall", X(31,934), XRARB_MASK
, PPCA2
, 0, {L2
}},
6509 {"wclr", X(31,934), X_MASK
, PPCA2
, 0, {L2
, RA0
, RB
}},
6511 {"stvrxl", X(31,935), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6513 {"divdeo", XO(31,425,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6514 {"divdeo.", XO(31,425,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6515 {"divweo", XO(31,427,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6516 {"divweo.", XO(31,427,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6518 {"stxvh8x", X(31,940), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6519 {"stxsihx", X(31,941), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6521 {"treclaim.", XRC(31,942,1), XRTRB_MASK
, PPCHTM
, 0, {RA
}},
6523 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
6524 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
6525 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RSO
, RAOPT
, SHO
}},
6527 {"sthcix", X(31,949), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6529 {"icswepx", XRC(31,950,0), X_MASK
, PPCA2
, 0, {RS
, RA
, RB
}},
6530 {"icswepx.", XRC(31,950,1), X_MASK
, PPCA2
, 0, {RS
, RA
, RB
}},
6532 {"stfqux", X(31,951), X_MASK
, POWER2
, 0, {FRS
, RA
, RB
}},
6534 {"sraiq", XRC(31,952,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6535 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6537 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
, 0, {RA
, RS
}},
6538 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
, 0, {RA
, RS
}},
6540 {"stvflxl", X(31,965), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6542 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCA2
, 0, {RAOPT
, RBOPT
}},
6543 {"ici", X(31,966), XRARB_MASK
, PPCA2
|PPC476
, 0, {CT
}},
6545 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6546 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6548 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6549 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6551 {"stxvd2x", X(31,972), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
6552 {"stxvx", X(31,972), XX1_MASK
, POWER8
, POWER9
|PPCVSX3
, {XS6
, RA0
, RB
}},
6554 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, PPC403
|BOOKE
|PPCA2
|PPC476
, {RB
}},
6555 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, 0, {RT
, RA
}},
6556 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, 0, {RT
, RA
}},
6557 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RSO
, RAOPT
, SHO
}},
6559 {"slbfee.", XRC(31,979,1), XRA_MASK
, POWER6
, 0, {RT
, RB
}},
6561 {"stbcix", X(31,981), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6563 {"icbi", X(31,982), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6565 {"stfiwx", X(31,983), X_MASK
, PPC
, PPCEFS
, {FRS
, RA0
, RB
}},
6567 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
6568 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
6570 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
6572 {"stvswxl", X(31,997), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6574 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA0
, RB
}},
6576 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6577 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6579 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6580 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6582 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6583 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6585 {"stxvb16x", X(31,1004), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6587 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
6589 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, TITAN
, {RB
}},
6591 {"stdcix", X(31,1013), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6593 {"dcbz", X(31,1014), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6594 {"dclz", X(31,1014), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6596 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
6598 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
|E500MC
, PPC476
, {RA0
, RB
}},
6600 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, 0, {0}},
6601 {"cctpm", 0x7c421378, 0xffffffff, CELL
, 0, {0}},
6602 {"cctph", 0x7c631b78, 0xffffffff, CELL
, 0, {0}},
6604 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
6605 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
6606 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, 0, {0}},
6608 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, 0, {0}},
6609 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, 0, {0}},
6610 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, 0, {0}},
6611 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, 0, {0}},
6613 {"lwz", OP(32), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RA0
}},
6614 {"l", OP(32), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
6616 {"lwzu", OP(33), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RAL
}},
6617 {"lu", OP(33), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
6619 {"lbz", OP(34), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
6621 {"lbzu", OP(35), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
6623 {"stw", OP(36), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RA0
}},
6624 {"st", OP(36), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
6626 {"stwu", OP(37), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RAS
}},
6627 {"stu", OP(37), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
6629 {"stb", OP(38), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RA0
}},
6631 {"stbu", OP(39), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RAS
}},
6633 {"lhz", OP(40), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
6635 {"lhzu", OP(41), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
6637 {"lha", OP(42), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
6639 {"lhau", OP(43), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
6641 {"sth", OP(44), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RA0
}},
6643 {"sthu", OP(45), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RAS
}},
6645 {"lmw", OP(46), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RAM
}},
6646 {"lm", OP(46), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
6648 {"stmw", OP(47), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RA0
}},
6649 {"stm", OP(47), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
6651 {"lfs", OP(48), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RA0
}},
6653 {"lfsu", OP(49), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RAS
}},
6655 {"lfd", OP(50), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RA0
}},
6657 {"lfdu", OP(51), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RAS
}},
6659 {"stfs", OP(52), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RA0
}},
6661 {"stfsu", OP(53), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RAS
}},
6663 {"stfd", OP(54), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RA0
}},
6665 {"stfdu", OP(55), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RAS
}},
6667 {"lq", OP(56), OP_MASK
|Q_MASK
, POWER4
, PPC476
|PPCVLE
, {RTQ
, DQ
, RAQ
}},
6668 {"psq_l", OP(56), OP_MASK
, PPCPS
, PPCVLE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
6669 {"lfq", OP(56), OP_MASK
, POWER2
, PPCVLE
, {FRT
, D
, RA0
}},
6671 {"lxsd", DSO(57,2), DS_MASK
, PPCVSX3
, PPCVLE
, {VD
, DS
, RA0
}},
6672 {"lxssp", DSO(57,3), DS_MASK
, PPCVSX3
, PPCVLE
, {VD
, DS
, RA0
}},
6673 {"lfdp", OP(57), OP_MASK
|Q_MASK
, POWER6
, POWER7
|PPCVLE
, {FRTp
, DS
, RA0
}},
6674 {"psq_lu", OP(57), OP_MASK
, PPCPS
, PPCVLE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
6675 {"lfqu", OP(57), OP_MASK
, POWER2
, PPCVLE
, {FRT
, D
, RA0
}},
6677 {"ld", DSO(58,0), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RA0
}},
6678 {"ldu", DSO(58,1), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RAL
}},
6679 {"lwa", DSO(58,2), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RA0
}},
6681 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6682 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6684 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, PPCVLE
, {FRT
,FRA
,FRB
,RMC
}},
6685 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, PPCVLE
, {FRT
,FRA
,FRB
,RMC
}},
6687 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6688 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6690 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6691 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6693 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6694 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6696 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, TITAN
|PPCVLE
, {FRT
, FRB
}},
6697 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, TITAN
|PPCVLE
, {FRT
, FRB
}},
6699 {"fres", A(59,24,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6700 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6701 {"fres.", A(59,24,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6702 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6704 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
6705 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
6707 {"frsqrtes", A(59,26,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6708 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6709 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6710 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6712 {"fmsubs", A(59,28,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6713 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6715 {"fmadds", A(59,29,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6716 {"fmadds.", A(59,29,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6718 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6719 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6721 {"fnmadds", A(59,31,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6722 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6724 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6725 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6727 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
, RMC
}},
6728 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
, RMC
}},
6730 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
6731 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
6733 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, PPCVLE
, {TE
, FRT
,FRB
,RMC
}},
6734 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, PPCVLE
, {TE
, FRT
,FRB
,RMC
}},
6736 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
6737 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
6739 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
6740 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
6742 {"dcmpo", X(59,130), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
6744 {"dtstex", X(59,162), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
6745 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, DCM
}},
6746 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, DGM
}},
6748 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
6749 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
6751 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
6752 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
6754 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
6755 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
6757 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, PPCVLE
, {SP
, FRT
, FRB
}},
6758 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, PPCVLE
, {SP
, FRT
, FRB
}},
6760 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
6761 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
6763 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6764 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6766 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6767 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6769 {"dcmpu", X(59,642), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
6771 {"dtstsf", X(59,674), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
6772 {"dtstsfi", X(59,675), X_MASK
|1<<22,POWER9
, PPCVLE
, {BF
, UIM6
, FRB
}},
6774 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
6775 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
6777 {"dcffix", XRC(59,802,0), X_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6778 {"dcffix.", XRC(59,802,1), X_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6780 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, PPCVLE
, {S
, FRT
, FRB
}},
6781 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, PPCVLE
, {S
, FRT
, FRB
}},
6783 {"fcfids", XRC(59,846,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
6784 {"fcfids.", XRC(59,846,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
6786 {"diex", XRC(59,866,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6787 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6789 {"fcfidus", XRC(59,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
6790 {"fcfidus.", XRC(59,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
6792 {"xsaddsp", XX3(60,0), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6793 {"xsmaddasp", XX3(60,1), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6794 {"xxsldwi", XX3(60,2), XX3SHW_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, SHW
}},
6795 {"xscmpeqdp", XX3(60,3), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6796 {"xsrsqrtesp", XX2(60,10), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
6797 {"xssqrtsp", XX2(60,11), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
6798 {"xxsel", XX4(60,3), XX4_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, XC6
}},
6799 {"xssubsp", XX3(60,8), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6800 {"xsmaddmsp", XX3(60,9), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6801 {"xxspltd", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6S
, DMEX
}},
6802 {"xxmrghd", XX3(60,10), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6803 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6S
}},
6804 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6805 {"xxpermdi", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, DM
}},
6806 {"xscmpgtdp", XX3(60,11), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6807 {"xsresp", XX2(60,26), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
6808 {"xsmulsp", XX3(60,16), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6809 {"xsmsubasp", XX3(60,17), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6810 {"xxmrghw", XX3(60,18), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6811 {"xscmpgedp", XX3(60,19), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6812 {"xsdivsp", XX3(60,24), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6813 {"xsmsubmsp", XX3(60,25), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6814 {"xxperm", XX3(60,26), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6815 {"xsadddp", XX3(60,32), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6816 {"xsmaddadp", XX3(60,33), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6817 {"xscmpudp", XX3(60,35), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
6818 {"xscvdpuxws", XX2(60,72), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6819 {"xsrdpi", XX2(60,73), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6820 {"xsrsqrtedp", XX2(60,74), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6821 {"xssqrtdp", XX2(60,75), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6822 {"xssubdp", XX3(60,40), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6823 {"xsmaddmdp", XX3(60,41), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6824 {"xscmpodp", XX3(60,43), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
6825 {"xscvdpsxws", XX2(60,88), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6826 {"xsrdpiz", XX2(60,89), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6827 {"xsredp", XX2(60,90), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6828 {"xsmuldp", XX3(60,48), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6829 {"xsmsubadp", XX3(60,49), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6830 {"xxmrglw", XX3(60,50), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6831 {"xsrdpip", XX2(60,105), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6832 {"xstsqrtdp", XX2(60,106), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
6833 {"xsrdpic", XX2(60,107), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6834 {"xsdivdp", XX3(60,56), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6835 {"xsmsubmdp", XX3(60,57), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6836 {"xxpermr", XX3(60,58), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6837 {"xscmpexpdp", XX3(60,59), XX3BF_MASK
, PPCVSX3
, PPCVLE
, {BF
, XA6
, XB6
}},
6838 {"xsrdpim", XX2(60,121), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6839 {"xstdivdp", XX3(60,61), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
6840 {"xvaddsp", XX3(60,64), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6841 {"xvmaddasp", XX3(60,65), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6842 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6843 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6844 {"xvcvspuxws", XX2(60,136), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6845 {"xvrspi", XX2(60,137), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6846 {"xvrsqrtesp", XX2(60,138), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6847 {"xvsqrtsp", XX2(60,139), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6848 {"xvsubsp", XX3(60,72), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6849 {"xvmaddmsp", XX3(60,73), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6850 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6851 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6852 {"xvcvspsxws", XX2(60,152), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6853 {"xvrspiz", XX2(60,153), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6854 {"xvresp", XX2(60,154), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6855 {"xvmulsp", XX3(60,80), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6856 {"xvmsubasp", XX3(60,81), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6857 {"xxspltw", XX2(60,164), XX2UIM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
, UIM
}},
6858 {"xxextractuw", XX2(60,165), XX2UIM4_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, UIMM4
}},
6859 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6860 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6861 {"xvcvuxwsp", XX2(60,168), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6862 {"xvrspip", XX2(60,169), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6863 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
6864 {"xvrspic", XX2(60,171), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6865 {"xvdivsp", XX3(60,88), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6866 {"xvmsubmsp", XX3(60,89), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6867 {"xxspltib", X(60,360), XX1_MASK
|3<<19, PPCVSX3
, PPCVLE
, {XT6
, IMM8
}},
6868 {"xxinsertw", XX2(60,181), XX2UIM4_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, UIMM4
}},
6869 {"xvcvsxwsp", XX2(60,184), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6870 {"xvrspim", XX2(60,185), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6871 {"xvtdivsp", XX3(60,93), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
6872 {"xvadddp", XX3(60,96), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6873 {"xvmaddadp", XX3(60,97), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6874 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6875 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6876 {"xvcvdpuxws", XX2(60,200), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6877 {"xvrdpi", XX2(60,201), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6878 {"xvrsqrtedp", XX2(60,202), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6879 {"xvsqrtdp", XX2(60,203), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6880 {"xvsubdp", XX3(60,104), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6881 {"xvmaddmdp", XX3(60,105), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6882 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6883 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6884 {"xvcvdpsxws", XX2(60,216), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6885 {"xvrdpiz", XX2(60,217), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6886 {"xvredp", XX2(60,218), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6887 {"xvmuldp", XX3(60,112), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6888 {"xvmsubadp", XX3(60,113), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6889 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6890 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6891 {"xvcvuxwdp", XX2(60,232), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6892 {"xvrdpip", XX2(60,233), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6893 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
6894 {"xvrdpic", XX2(60,235), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6895 {"xvdivdp", XX3(60,120), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6896 {"xvmsubmdp", XX3(60,121), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6897 {"xvcvsxwdp", XX2(60,248), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6898 {"xvrdpim", XX2(60,249), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6899 {"xvtdivdp", XX3(60,125), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
6900 {"xsmaxcdp", XX3(60,128), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6901 {"xsnmaddasp", XX3(60,129), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6902 {"xxland", XX3(60,130), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6903 {"xscvdpsp", XX2(60,265), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6904 {"xscvdpspn", XX2(60,267), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
6905 {"xsmincdp", XX3(60,136), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6906 {"xsnmaddmsp", XX3(60,137), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6907 {"xxlandc", XX3(60,138), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6908 {"xsrsp", XX2(60,281), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
6909 {"xsmaxjdp", XX3(60,144), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6910 {"xsnmsubasp", XX3(60,145), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6911 {"xxlor", XX3(60,146), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6912 {"xscvuxdsp", XX2(60,296), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
6913 {"xststdcsp", XX2(60,298), XX2BFD_MASK
, PPCVSX3
, PPCVLE
, {BF
, XB6
, DCMX
}},
6914 {"xsminjdp", XX3(60,152), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6915 {"xsnmsubmsp", XX3(60,153), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6916 {"xxlxor", XX3(60,154), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6917 {"xscvsxdsp", XX2(60,312), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
6918 {"xsmaxdp", XX3(60,160), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6919 {"xsnmaddadp", XX3(60,161), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6920 {"xxlnor", XX3(60,162), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6921 {"xscvdpuxds", XX2(60,328), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6922 {"xscvspdp", XX2(60,329), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6923 {"xscvspdpn", XX2(60,331), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
6924 {"xsmindp", XX3(60,168), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6925 {"xsnmaddmdp", XX3(60,169), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6926 {"xxlorc", XX3(60,170), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6927 {"xscvdpsxds", XX2(60,344), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6928 {"xsabsdp", XX2(60,345), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6929 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK
|1, PPCVSX3
, PPCVLE
, {RT
, XB6
}},
6930 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK
|1, PPCVSX3
, PPCVLE
, {RT
, XB6
}},
6931 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6932 {"xscvdphp", XX2VA(60,347,17),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6933 {"xscpsgndp", XX3(60,176), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6934 {"xsnmsubadp", XX3(60,177), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6935 {"xxlnand", XX3(60,178), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6936 {"xscvuxddp", XX2(60,360), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6937 {"xsnabsdp", XX2(60,361), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6938 {"xststdcdp", XX2(60,362), XX2BFD_MASK
, PPCVSX3
, PPCVLE
, {BF
, XB6
, DCMX
}},
6939 {"xsnmsubmdp", XX3(60,185), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6940 {"xxleqv", XX3(60,186), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
6941 {"xscvsxddp", XX2(60,376), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6942 {"xsnegdp", XX2(60,377), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6943 {"xvmaxsp", XX3(60,192), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6944 {"xvnmaddasp", XX3(60,193), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6945 {"xvcvspuxds", XX2(60,392), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6946 {"xvcvdpsp", XX2(60,393), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6947 {"xvminsp", XX3(60,200), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6948 {"xvnmaddmsp", XX3(60,201), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6949 {"xvcvspsxds", XX2(60,408), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6950 {"xvabssp", XX2(60,409), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6951 {"xvmovsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6S
}},
6952 {"xvcpsgnsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6953 {"xvnmsubasp", XX3(60,209), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6954 {"xvcvuxdsp", XX2(60,424), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6955 {"xvnabssp", XX2(60,425), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6956 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, DCMXS
}},
6957 {"xviexpsp", XX3(60,216), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6958 {"xvnmsubmsp", XX3(60,217), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6959 {"xvcvsxdsp", XX2(60,440), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6960 {"xvnegsp", XX2(60,441), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6961 {"xvmaxdp", XX3(60,224), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6962 {"xvnmaddadp", XX3(60,225), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6963 {"xvcvdpuxds", XX2(60,456), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6964 {"xvcvspdp", XX2(60,457), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6965 {"xsiexpdp", X(60,918), XX1_MASK
, PPCVSX3
, PPCVLE
, {XT6
, RA
, RB
}},
6966 {"xvmindp", XX3(60,232), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6967 {"xvnmaddmdp", XX3(60,233), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6968 {"xvcvdpsxds", XX2(60,472), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6969 {"xvabsdp", XX2(60,473), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6970 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6971 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6972 {"xxbrh", XX2VA(60,475,7),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6973 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6974 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6975 {"xxbrw", XX2VA(60,475,15),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6976 {"xxbrd", XX2VA(60,475,23),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6977 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6978 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6979 {"xxbrq", XX2VA(60,475,31),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
6980 {"xvmovdp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6S
}},
6981 {"xvcpsgndp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6982 {"xvnmsubadp", XX3(60,241), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6983 {"xvcvuxddp", XX2(60,488), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6984 {"xvnabsdp", XX2(60,489), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6985 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, DCMXS
}},
6986 {"xviexpdp", XX3(60,248), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
6987 {"xvnmsubmdp", XX3(60,249), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
6988 {"xvcvsxddp", XX2(60,504), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6989 {"xvnegdp", XX2(60,505), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
6991 {"psq_st", OP(60), OP_MASK
, PPCPS
, PPCVLE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
6992 {"stfq", OP(60), OP_MASK
, POWER2
, PPCVLE
, {FRS
, D
, RA
}},
6994 {"lxv", DQX(61,1), DQX_MASK
, PPCVSX3
, PPCVLE
, {XTQ6
, DQ
, RA0
}},
6995 {"stxv", DQX(61,5), DQX_MASK
, PPCVSX3
, PPCVLE
, {XSQ6
, DQ
, RA0
}},
6996 {"stxsd", DSO(61,2), DS_MASK
, PPCVSX3
, PPCVLE
, {VS
, DS
, RA0
}},
6997 {"stxssp", DSO(61,3), DS_MASK
, PPCVSX3
, PPCVLE
, {VS
, DS
, RA0
}},
6998 {"stfdp", OP(61), OP_MASK
|Q_MASK
, POWER6
, POWER7
|PPCVLE
, {FRSp
, DS
, RA0
}},
6999 {"psq_stu", OP(61), OP_MASK
, PPCPS
, PPCVLE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
7000 {"stfqu", OP(61), OP_MASK
, POWER2
, PPCVLE
, {FRS
, D
, RA
}},
7002 {"std", DSO(62,0), DS_MASK
, PPC64
, PPCVLE
, {RS
, DS
, RA0
}},
7003 {"stdu", DSO(62,1), DS_MASK
, PPC64
, PPCVLE
, {RS
, DS
, RAS
}},
7004 {"stq", DSO(62,2), DS_MASK
|Q_MASK
, POWER4
, PPC476
|PPCVLE
, {RSQ
, DS
, RA0
}},
7006 {"fcmpu", X(63,0), XBF_MASK
, COM
, PPCEFS
|PPCVLE
, {BF
, FRA
, FRB
}},
7008 {"daddq", XRC(63,2,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7009 {"daddq.", XRC(63,2,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7011 {"dquaq", ZRC(63,3,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
, RMC
}},
7012 {"dquaq.", ZRC(63,3,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
, RMC
}},
7014 {"xsaddqp", XRC(63,4,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7015 {"xsaddqpo", XRC(63,4,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7017 {"xsrqpi", ZRC(63,5,0), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
7018 {"xsrqpix", ZRC(63,5,1), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
7020 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FRT
, FRA
, FRB
}},
7021 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FRT
, FRA
, FRB
}},
7023 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7024 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7026 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7027 {"fcir", XRC(63,14,0), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7028 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7029 {"fcir.", XRC(63,14,1), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7031 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7032 {"fcirz", XRC(63,15,0), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7033 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7034 {"fcirz.", XRC(63,15,1), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7036 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7037 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7038 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7039 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7041 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7042 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7043 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7044 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7046 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7047 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7048 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7049 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7051 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, TITAN
|PPCVLE
, {FRT
, FRB
}},
7052 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, TITAN
|PPCVLE
, {FRT
, FRB
}},
7054 {"fsel", A(63,23,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7055 {"fsel.", A(63,23,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7057 {"fre", A(63,24,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7058 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7059 {"fre.", A(63,24,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7060 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7062 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
7063 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, PPCVLE
|PPCVLE
, {FRT
, FRA
, FRC
}},
7064 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
7065 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, PPCVLE
|PPCVLE
, {FRT
, FRA
, FRC
}},
7067 {"frsqrte", A(63,26,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7068 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7069 {"frsqrte.", A(63,26,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7070 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7072 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7073 {"fms", A(63,28,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7074 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7075 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7077 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7078 {"fma", A(63,29,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7079 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7080 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7082 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7083 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7084 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7085 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7087 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7088 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7089 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7090 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7092 {"fcmpo", X(63,32), XBF_MASK
, COM
, PPCEFS
|PPCVLE
, {BF
, FRA
, FRB
}},
7094 {"dmulq", XRC(63,34,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7095 {"dmulq.", XRC(63,34,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7097 {"drrndq", ZRC(63,35,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
, RMC
}},
7098 {"drrndq.", ZRC(63,35,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
, RMC
}},
7100 {"xsmulqp", XRC(63,36,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7101 {"xsmulqpo", XRC(63,36,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7103 {"xsrqpxp", Z(63,37), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
7105 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7106 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7108 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7109 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7111 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, PPCVLE
, {BF
, BFA
}},
7113 {"dscliq", ZRC(63,66,0), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7114 {"dscliq.", ZRC(63,66,1), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7116 {"dquaiq", ZRC(63,67,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {TE
, FRTp
, FRBp
, RMC
}},
7117 {"dquaiq.", ZRC(63,67,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {TE
, FRTp
, FRBp
, RMC
}},
7119 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7120 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7122 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7123 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7125 {"dscriq", ZRC(63,98,0), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7126 {"dscriq.", ZRC(63,98,1), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7128 {"drintxq", ZRC(63,99,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7129 {"drintxq.", ZRC(63,99,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7131 {"xscpsgnqp", X(63,100), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7133 {"ftdiv", X(63,128), XBF_MASK
, POWER7
, PPCVLE
, {BF
, FRA
, FRB
}},
7135 {"dcmpoq", X(63,130), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
7137 {"xscmpoqp", X(63,132), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
7139 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCVLE
, {BFF
, U
, W
}},
7140 {"mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
|PPCVLE
, {BFF
, U
}},
7141 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCVLE
, {BFF
, U
, W
}},
7142 {"mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
|PPCVLE
, {BFF
, U
}},
7144 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7145 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7147 {"fctiwu", XRC(63,142,0), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7148 {"fctiwu.", XRC(63,142,1), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7149 {"fctiwuz", XRC(63,143,0), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7150 {"fctiwuz.", XRC(63,143,1), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7152 {"ftsqrt", X(63,160), XBF_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {BF
, FRB
}},
7154 {"dtstexq", X(63,162), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
7156 {"xscmpexpqp", X(63,164), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
7158 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, DCM
}},
7159 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, DGM
}},
7161 {"drintnq", ZRC(63,227,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7162 {"drintnq.", ZRC(63,227,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7164 {"dctqpq", XRC(63,258,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7165 {"dctqpq.", XRC(63,258,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7167 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7168 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7170 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7171 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7173 {"ddedpdq", XRC(63,322,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {SP
, FRTp
, FRBp
}},
7174 {"ddedpdq.", XRC(63,322,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {SP
, FRTp
, FRBp
}},
7176 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7177 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7179 {"xsmaddqp", XRC(63,388,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7180 {"xsmaddqpo", XRC(63,388,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7182 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7183 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7185 {"xsmsubqp", XRC(63,420,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7186 {"xsmsubqpo", XRC(63,420,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7188 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7189 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7191 {"xsnmaddqp", XRC(63,452,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7192 {"xsnmaddqpo", XRC(63,452,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7194 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7195 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7197 {"xsnmsubqp", XRC(63,484,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7198 {"xsnmsubqpo", XRC(63,484,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7200 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7201 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7203 {"dsubq", XRC(63,514,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7204 {"dsubq.", XRC(63,514,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7206 {"xssubqp", XRC(63,516,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7207 {"xssubqpo", XRC(63,516,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7209 {"ddivq", XRC(63,546,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7210 {"ddivq.", XRC(63,546,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7212 {"xsdivqp", XRC(63,548,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7213 {"xsdivqpo", XRC(63,548,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7215 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
}},
7216 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
}},
7218 {"mffsce", XMMF(63,583,0,1), XMMF_MASK
|RB_MASK
, POWER9
, PPCVLE
, {FRT
}},
7219 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK
, POWER9
, PPCVLE
, {FRT
, FRB
}},
7220 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK
|(3<<14), POWER9
, PPCVLE
, {FRT
, DRM
}},
7221 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK
, POWER9
, PPCVLE
, {FRT
, FRB
}},
7222 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK
|(7<<13), POWER9
, PPCVLE
, {FRT
, RM
}},
7223 {"mffsl", XMMF(63,583,3,0), XMMF_MASK
|RB_MASK
, POWER9
, PPCVLE
, {FRT
}},
7225 {"dcmpuq", X(63,642), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
7227 {"xscmpuqp", X(63,644), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
7229 {"dtstsfq", X(63,674), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRBp
}},
7230 {"dtstsfiq", X(63,675), X_MASK
|1<<22,POWER9
, PPCVLE
, {BF
, UIM6
, FRBp
}},
7232 {"xststdcqp", X(63,708), X_MASK
, PPCVSX3
, PPCVLE
, {BF
, VB
, DCMX
}},
7234 {"mtfsf", XFL(63,711,0), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FLM
, FRB
, XFL_L
, W
}},
7235 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
|PPCVLE
, {FLM
, FRB
}},
7236 {"mtfsf.", XFL(63,711,1), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FLM
, FRB
, XFL_L
, W
}},
7237 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
|PPCVLE
, {FLM
, FRB
}},
7239 {"drdpq", XRC(63,770,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRBp
}},
7240 {"drdpq.", XRC(63,770,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRBp
}},
7242 {"dcffixq", XRC(63,802,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7243 {"dcffixq.", XRC(63,802,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7245 {"xsabsqp", XVA(63,804,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7246 {"xsxexpqp", XVA(63,804,2), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7247 {"xsnabsqp", XVA(63,804,8), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7248 {"xsnegqp", XVA(63,804,16), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7249 {"xsxsigqp", XVA(63,804,18), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7250 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7251 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7253 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7254 {"fctid", XRC(63,814,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7255 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7256 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7258 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7259 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7260 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7261 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7263 {"denbcdq", XRC(63,834,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {S
, FRTp
, FRBp
}},
7264 {"denbcdq.", XRC(63,834,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {S
, FRTp
, FRBp
}},
7266 {"xscvqpuwz", XVA(63,836,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7267 {"xscvudqp", XVA(63,836,2), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7268 {"xscvqpswz", XVA(63,836,9), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7269 {"xscvsdqp", XVA(63,836,10), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7270 {"xscvqpudz", XVA(63,836,17), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7271 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7272 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7273 {"xscvdpqp", XVA(63,836,22), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7274 {"xscvqpsdz", XVA(63,836,25), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7276 {"fmrgow", X(63,838), X_MASK
, PPCVSX2
, PPCVLE
, {FRT
, FRA
, FRB
}},
7278 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7279 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7280 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7281 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7283 {"diexq", XRC(63,866,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
}},
7284 {"diexq.", XRC(63,866,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
}},
7286 {"xsiexpqp", X(63,868), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7288 {"fctidu", XRC(63,942,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7289 {"fctidu.", XRC(63,942,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7291 {"fctiduz", XRC(63,943,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7292 {"fctiduz.", XRC(63,943,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7294 {"fmrgew", X(63,966), X_MASK
, PPCVSX2
, PPCVLE
, {FRT
, FRA
, FRB
}},
7296 {"fcfidu", XRC(63,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7297 {"fcfidu.", XRC(63,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7300 const int powerpc_num_opcodes
=
7301 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
7303 /* The VLE opcode table.
7305 The format of this opcode table is the same as the main opcode table. */
7307 const struct powerpc_opcode vle_opcodes
[] = {
7308 {"se_illegal", C(0), C_MASK
, PPCVLE
, 0, {}},
7309 {"se_isync", C(1), C_MASK
, PPCVLE
, 0, {}},
7310 {"se_sc", C(2), C_MASK
, PPCVLE
, 0, {}},
7311 {"se_blr", C_LK(2,0), C_LK_MASK
, PPCVLE
, 0, {}},
7312 {"se_blrl", C_LK(2,1), C_LK_MASK
, PPCVLE
, 0, {}},
7313 {"se_bctr", C_LK(3,0), C_LK_MASK
, PPCVLE
, 0, {}},
7314 {"se_bctrl", C_LK(3,1), C_LK_MASK
, PPCVLE
, 0, {}},
7315 {"se_rfi", C(8), C_MASK
, PPCVLE
, 0, {}},
7316 {"se_rfci", C(9), C_MASK
, PPCVLE
, 0, {}},
7317 {"se_rfdi", C(10), C_MASK
, PPCVLE
, 0, {}},
7318 {"se_rfmci", C(11), C_MASK
, PPCRFMCI
|PPCVLE
, 0, {}},
7319 {"se_rfgi", C(12), C_MASK
, PPCVLE
, 0, {}},
7320 {"se_not", SE_R(0,2), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7321 {"se_neg", SE_R(0,3), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7322 {"se_mflr", SE_R(0,8), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7323 {"se_mtlr", SE_R(0,9), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7324 {"se_mfctr", SE_R(0,10), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7325 {"se_mtctr", SE_R(0,11), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7326 {"se_extzb", SE_R(0,12), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7327 {"se_extsb", SE_R(0,13), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7328 {"se_extzh", SE_R(0,14), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7329 {"se_extsh", SE_R(0,15), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7330 {"se_mr", SE_RR(0,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7331 {"se_mtar", SE_RR(0,2), SE_RR_MASK
, PPCVLE
, 0, {ARX
, RY
}},
7332 {"se_mfar", SE_RR(0,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, ARY
}},
7333 {"se_add", SE_RR(1,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7334 {"se_mullw", SE_RR(1,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7335 {"se_sub", SE_RR(1,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7336 {"se_subf", SE_RR(1,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7337 {"se_cmp", SE_RR(3,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7338 {"se_cmpl", SE_RR(3,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7339 {"se_cmph", SE_RR(3,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7340 {"se_cmphl", SE_RR(3,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7342 /* by major opcode */
7343 {"zvaddih", VX(4, 0x200), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7344 {"zvsubifh", VX(4, 0x201), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7345 {"zvaddh", VX(4, 0x204), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7346 {"zvsubfh", VX(4, 0x205), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7347 {"zvaddsubfh", VX(4, 0x206), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7348 {"zvsubfaddh", VX(4, 0x207), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7349 {"zvaddhx", VX(4, 0x20C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7350 {"zvsubfhx", VX(4, 0x20D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7351 {"zvaddsubfhx", VX(4, 0x20E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7352 {"zvsubfaddhx", VX(4, 0x20F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7353 {"zaddwus", VX(4, 0x210), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7354 {"zsubfwus", VX(4, 0x211), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7355 {"zaddwss", VX(4, 0x212), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7356 {"zsubfwss", VX(4, 0x213), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7357 {"zvaddhus", VX(4, 0x214), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7358 {"zvsubfhus", VX(4, 0x215), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7359 {"zvaddhss", VX(4, 0x216), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7360 {"zvsubfhss", VX(4, 0x217), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7361 {"zvaddsubfhss", VX(4, 0x21A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7362 {"zvsubfaddhss", VX(4, 0x21B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7363 {"zvaddhxss", VX(4, 0x21C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7364 {"zvsubfhxss", VX(4, 0x21D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7365 {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7366 {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7367 {"zaddheuw", VX(4, 0x220), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7368 {"zsubfheuw", VX(4, 0x221), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7369 {"zaddhesw", VX(4, 0x222), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7370 {"zsubfhesw", VX(4, 0x223), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7371 {"zaddhouw", VX(4, 0x224), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7372 {"zsubfhouw", VX(4, 0x225), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7373 {"zaddhosw", VX(4, 0x226), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7374 {"zsubfhosw", VX(4, 0x227), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7375 {"zvmergehih", VX(4, 0x22C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7376 {"zvmergeloh", VX(4, 0x22D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7377 {"zvmergehiloh", VX(4, 0x22E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7378 {"zvmergelohih", VX(4, 0x22F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7379 {"zvcmpgthu", VX(4, 0x230), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7380 {"zvcmpgths", VX(4, 0x230), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7381 {"zvcmplthu", VX(4, 0x231), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7382 {"zvcmplths", VX(4, 0x231), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7383 {"zvcmpeqh", VX(4, 0x232), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7384 {"zpkswgshfrs", VX(4, 0x238), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7385 {"zpkswgswfrs", VX(4, 0x239), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7386 {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7387 {"zvpkswshfrs", VX(4, 0x23B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7388 {"zvpkswuhs", VX(4, 0x23C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7389 {"zvpkswshs", VX(4, 0x23D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7390 {"zvpkuwuhs", VX(4, 0x23E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7391 {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, SIMM
}},
7392 {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, SIMM
}},
7393 {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7394 {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7395 {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7396 {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7397 {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7398 {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7399 {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7400 {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7401 {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7402 {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7403 {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7404 {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7405 {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7406 {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7407 {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7408 {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7409 {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7410 {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7411 {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7412 {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7413 {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7414 {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7415 {"zsatsduw", VX(4, 0x260), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7416 {"zsatsdsw", VX(4, 0x261), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7417 {"zsatuduw", VX(4, 0x262), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7418 {"zvselh", VX(4, 0x264), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7419 {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK
, PPCLSP
, 0, {RD
, RA
, RB
, VX_OFF
}},
7420 {"zbrminc", VX(4, 0x268), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7421 {"zcircinc", VX(4, 0x269), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7422 {"zdivwsf", VX(4, 0x26B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7423 {"zvsrhu", VX(4, 0x270), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7424 {"zvsrhs", VX(4, 0x271), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7425 {"zvsrhiu", VX(4, 0x272), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7426 {"zvsrhis", VX(4, 0x273), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7427 {"zvslh", VX(4, 0x274), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7428 {"zvrlh", VX(4, 0x275), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7429 {"zvslhi", VX(4, 0x276), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7430 {"zvrlhi", VX(4, 0x277), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7431 {"zvslhus", VX(4, 0x278), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7432 {"zvslhss", VX(4, 0x279), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7433 {"zvslhius", VX(4, 0x27A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7434 {"zvslhiss", VX(4, 0x27B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7435 {"zslwus", VX(4, 0x27C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7436 {"zslwss", VX(4, 0x27D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7437 {"zslwius", VX(4, 0x27E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7438 {"zslwiss", VX(4, 0x27F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7439 {"zaddwgui", VX(4, 0x460), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7440 {"zsubfwgui", VX(4, 0x461), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7441 {"zaddd", VX(4, 0x462), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7442 {"zsubfd", VX(4, 0x463), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7443 {"zvaddsubfw", VX(4, 0x464), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7444 {"zvsubfaddw", VX(4, 0x465), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7445 {"zvaddw", VX(4, 0x466), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7446 {"zvsubfw", VX(4, 0x467), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7447 {"zaddwgsi", VX(4, 0x468), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7448 {"zsubfwgsi", VX(4, 0x469), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7449 {"zadddss", VX(4, 0x46A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7450 {"zsubfdss", VX(4, 0x46B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7451 {"zvaddsubfwss", VX(4, 0x46C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7452 {"zvsubfaddwss", VX(4, 0x46D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7453 {"zvaddwss", VX(4, 0x46E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7454 {"zvsubfwss", VX(4, 0x46F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7455 {"zaddwgsf", VX(4, 0x470), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7456 {"zsubfwgsf", VX(4, 0x471), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7457 {"zadddus", VX(4, 0x472), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7458 {"zsubfdus", VX(4, 0x473), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7459 {"zvaddwus", VX(4, 0x476), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7460 {"zvsubfwus", VX(4, 0x477), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7461 {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7462 {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7463 {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7464 {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7465 {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7466 {"zvdotphgwasmf", VX(4, 0x488), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7467 {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7468 {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7469 {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7470 {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7471 {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7472 {"zvmhulgwsmf", VX(4, 0x490), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7473 {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7474 {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7475 {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7476 {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7477 {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7478 {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7479 {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7480 {"zmhegwsmf", VX(4, 0x498), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7481 {"zmhegwsmfr", VX(4, 0x499), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7482 {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7483 {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7484 {"zmhegwsmfan", VX(4, 0x49C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7485 {"zmhegwsmfran", VX(4, 0x49D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7486 {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7487 {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7488 {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7489 {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7490 {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7491 {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7492 {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7493 {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7494 {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7495 {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7496 {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7497 {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7498 {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7499 {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7500 {"zmheogwsmf", VX(4, 0x4B8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7501 {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7502 {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7503 {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7504 {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7505 {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7506 {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7507 {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7508 {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7509 {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7510 {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7511 {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7512 {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7513 {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7514 {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7515 {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7516 {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7517 {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7518 {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7519 {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7520 {"zmhogwsmf", VX(4, 0x4D8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7521 {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7522 {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7523 {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7524 {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7525 {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7526 {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7527 {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7528 {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7529 {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7530 {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7531 {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7532 {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7533 {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7534 {"zmhegui", VX(4, 0x500), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7535 {"zvdotphgaui", VX(4, 0x501), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7536 {"zmheguiaa", VX(4, 0x502), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7537 {"zvdotphgauiaa", VX(4, 0x503), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7538 {"zmheguian", VX(4, 0x504), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7539 {"zvdotphgauian", VX(4, 0x505), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7540 {"zmhegsi", VX(4, 0x508), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7541 {"zvdotphgasi", VX(4, 0x509), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7542 {"zmhegsiaa", VX(4, 0x50A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7543 {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7544 {"zmhegsian", VX(4, 0x50C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7545 {"zvdotphgasian", VX(4, 0x50D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7546 {"zmhegsui", VX(4, 0x510), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7547 {"zvdotphgasui", VX(4, 0x511), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7548 {"zmhegsuiaa", VX(4, 0x512), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7549 {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7550 {"zmhegsuian", VX(4, 0x514), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7551 {"zvdotphgasuian", VX(4, 0x515), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7552 {"zmhegsmf", VX(4, 0x518), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7553 {"zvdotphgasmf", VX(4, 0x519), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7554 {"zmhegsmfaa", VX(4, 0x51A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7555 {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7556 {"zmhegsmfan", VX(4, 0x51C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7557 {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7558 {"zmheogui", VX(4, 0x520), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7559 {"zvdotphxgaui", VX(4, 0x521), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7560 {"zmheoguiaa", VX(4, 0x522), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7561 {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7562 {"zmheoguian", VX(4, 0x524), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7563 {"zvdotphxgauian", VX(4, 0x525), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7564 {"zmheogsi", VX(4, 0x528), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7565 {"zvdotphxgasi", VX(4, 0x529), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7566 {"zmheogsiaa", VX(4, 0x52A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7567 {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7568 {"zmheogsian", VX(4, 0x52C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7569 {"zvdotphxgasian", VX(4, 0x52D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7570 {"zmheogsui", VX(4, 0x530), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7571 {"zvdotphxgasui", VX(4, 0x531), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7572 {"zmheogsuiaa", VX(4, 0x532), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7573 {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7574 {"zmheogsuian", VX(4, 0x534), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7575 {"zvdotphxgasuian", VX(4, 0x535), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7576 {"zmheogsmf", VX(4, 0x538), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7577 {"zvdotphxgasmf", VX(4, 0x539), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7578 {"zmheogsmfaa", VX(4, 0x53A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7579 {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7580 {"zmheogsmfan", VX(4, 0x53C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7581 {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7582 {"zmhogui", VX(4, 0x540), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7583 {"zvdotphgsui", VX(4, 0x541), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7584 {"zmhoguiaa", VX(4, 0x542), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7585 {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7586 {"zmhoguian", VX(4, 0x544), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7587 {"zvdotphgsuian", VX(4, 0x545), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7588 {"zmhogsi", VX(4, 0x548), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7589 {"zvdotphgssi", VX(4, 0x549), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7590 {"zmhogsiaa", VX(4, 0x54A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7591 {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7592 {"zmhogsian", VX(4, 0x54C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7593 {"zvdotphgssian", VX(4, 0x54D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7594 {"zmhogsui", VX(4, 0x550), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7595 {"zvdotphgssui", VX(4, 0x551), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7596 {"zmhogsuiaa", VX(4, 0x552), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7597 {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7598 {"zmhogsuian", VX(4, 0x554), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7599 {"zvdotphgssuian", VX(4, 0x555), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7600 {"zmhogsmf", VX(4, 0x558), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7601 {"zvdotphgssmf", VX(4, 0x559), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7602 {"zmhogsmfaa", VX(4, 0x55A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7603 {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7604 {"zmhogsmfan", VX(4, 0x55C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7605 {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7606 {"zmwgui", VX(4, 0x560), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7607 {"zmwguiaa", VX(4, 0x562), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7608 {"zmwguiaas", VX(4, 0x563), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7609 {"zmwguian", VX(4, 0x564), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7610 {"zmwguians", VX(4, 0x565), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7611 {"zmwgsi", VX(4, 0x568), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7612 {"zmwgsiaa", VX(4, 0x56A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7613 {"zmwgsiaas", VX(4, 0x56B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7614 {"zmwgsian", VX(4, 0x56C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7615 {"zmwgsians", VX(4, 0x56D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7616 {"zmwgsui", VX(4, 0x570), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7617 {"zmwgsuiaa", VX(4, 0x572), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7618 {"zmwgsuiaas", VX(4, 0x573), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7619 {"zmwgsuian", VX(4, 0x574), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7620 {"zmwgsuians", VX(4, 0x575), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7621 {"zmwgsmf", VX(4, 0x578), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7622 {"zmwgsmfr", VX(4, 0x579), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7623 {"zmwgsmfaa", VX(4, 0x57A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7624 {"zmwgsmfraa", VX(4, 0x57B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7625 {"zmwgsmfan", VX(4, 0x57C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7626 {"zmwgsmfran", VX(4, 0x57D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7627 {"zvmhului", VX(4, 0x580), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7628 {"zvmhuluiaa", VX(4, 0x582), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7629 {"zvmhuluiaas", VX(4, 0x583), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7630 {"zvmhuluian", VX(4, 0x584), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7631 {"zvmhuluians", VX(4, 0x585), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7632 {"zvmhuluianp", VX(4, 0x586), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7633 {"zvmhuluianps", VX(4, 0x587), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7634 {"zvmhulsi", VX(4, 0x588), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7635 {"zvmhulsiaa", VX(4, 0x58A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7636 {"zvmhulsiaas", VX(4, 0x58B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7637 {"zvmhulsian", VX(4, 0x58C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7638 {"zvmhulsians", VX(4, 0x58D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7639 {"zvmhulsianp", VX(4, 0x58E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7640 {"zvmhulsianps", VX(4, 0x58F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7641 {"zvmhulsui", VX(4, 0x590), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7642 {"zvmhulsuiaa", VX(4, 0x592), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7643 {"zvmhulsuiaas", VX(4, 0x593), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7644 {"zvmhulsuian", VX(4, 0x594), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7645 {"zvmhulsuians", VX(4, 0x595), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7646 {"zvmhulsuianp", VX(4, 0x596), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7647 {"zvmhulsuianps", VX(4, 0x597), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7648 {"zvmhulsf", VX(4, 0x598), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7649 {"zvmhulsfr", VX(4, 0x599), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7650 {"zvmhulsfaas", VX(4, 0x59A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7651 {"zvmhulsfraas", VX(4, 0x59B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7652 {"zvmhulsfans", VX(4, 0x59C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7653 {"zvmhulsfrans", VX(4, 0x59D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7654 {"zvmhulsfanps", VX(4, 0x59E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7655 {"zvmhulsfranps", VX(4, 0x59F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7656 {"zvmhllui", VX(4, 0x5A0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7657 {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7658 {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7659 {"zvmhlluian", VX(4, 0x5A4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7660 {"zvmhlluians", VX(4, 0x5A5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7661 {"zvmhlluianp", VX(4, 0x5A6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7662 {"zvmhlluianps", VX(4, 0x5A7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7663 {"zvmhllsi", VX(4, 0x5A8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7664 {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7665 {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7666 {"zvmhllsian", VX(4, 0x5AC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7667 {"zvmhllsians", VX(4, 0x5AD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7668 {"zvmhllsianp", VX(4, 0x5AE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7669 {"zvmhllsianps", VX(4, 0x5AF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7670 {"zvmhllsui", VX(4, 0x5B0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7671 {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7672 {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7673 {"zvmhllsuian", VX(4, 0x5B4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7674 {"zvmhllsuians", VX(4, 0x5B5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7675 {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7676 {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7677 {"zvmhllsf", VX(4, 0x5B8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7678 {"zvmhllsfr", VX(4, 0x5B9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7679 {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7680 {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7681 {"zvmhllsfans", VX(4, 0x5BC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7682 {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7683 {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7684 {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7685 {"zvmhuuui", VX(4, 0x5C0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7686 {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7687 {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7688 {"zvmhuuuian", VX(4, 0x5C4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7689 {"zvmhuuuians", VX(4, 0x5C5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7690 {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7691 {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7692 {"zvmhuusi", VX(4, 0x5C8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7693 {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7694 {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7695 {"zvmhuusian", VX(4, 0x5CC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7696 {"zvmhuusians", VX(4, 0x5CD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7697 {"zvmhuusianp", VX(4, 0x5CE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7698 {"zvmhuusianps", VX(4, 0x5CF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7699 {"zvmhuusui", VX(4, 0x5D0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7700 {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7701 {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7702 {"zvmhuusuian", VX(4, 0x5D4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7703 {"zvmhuusuians", VX(4, 0x5D5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7704 {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7705 {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7706 {"zvmhuusf", VX(4, 0x5D8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7707 {"zvmhuusfr", VX(4, 0x5D9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7708 {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7709 {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7710 {"zvmhuusfans", VX(4, 0x5DC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7711 {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7712 {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7713 {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7714 {"zvmhxlui", VX(4, 0x5E0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7715 {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7716 {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7717 {"zvmhxluian", VX(4, 0x5E4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7718 {"zvmhxluians", VX(4, 0x5E5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7719 {"zvmhxluianp", VX(4, 0x5E6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7720 {"zvmhxluianps", VX(4, 0x5E7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7721 {"zvmhxlsi", VX(4, 0x5E8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7722 {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7723 {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7724 {"zvmhxlsian", VX(4, 0x5EC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7725 {"zvmhxlsians", VX(4, 0x5ED), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7726 {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7727 {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7728 {"zvmhxlsui", VX(4, 0x5F0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7729 {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7730 {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7731 {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7732 {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7733 {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7734 {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7735 {"zvmhxlsf", VX(4, 0x5F8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7736 {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7737 {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7738 {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7739 {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7740 {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7741 {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7742 {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7743 {"zmheui", VX(4, 0x600), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7744 {"zmheuiaa", VX(4, 0x602), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7745 {"zmheuiaas", VX(4, 0x603), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7746 {"zmheuian", VX(4, 0x604), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7747 {"zmheuians", VX(4, 0x605), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7748 {"zmhesi", VX(4, 0x608), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7749 {"zmhesiaa", VX(4, 0x60A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7750 {"zmhesiaas", VX(4, 0x60B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7751 {"zmhesian", VX(4, 0x60C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7752 {"zmhesians", VX(4, 0x60D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7753 {"zmhesui", VX(4, 0x610), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7754 {"zmhesuiaa", VX(4, 0x612), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7755 {"zmhesuiaas", VX(4, 0x613), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7756 {"zmhesuian", VX(4, 0x614), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7757 {"zmhesuians", VX(4, 0x615), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7758 {"zmhesf", VX(4, 0x618), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7759 {"zmhesfr", VX(4, 0x619), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7760 {"zmhesfaas", VX(4, 0x61A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7761 {"zmhesfraas", VX(4, 0x61B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7762 {"zmhesfans", VX(4, 0x61C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7763 {"zmhesfrans", VX(4, 0x61D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7764 {"zmheoui", VX(4, 0x620), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7765 {"zmheouiaa", VX(4, 0x622), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7766 {"zmheouiaas", VX(4, 0x623), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7767 {"zmheouian", VX(4, 0x624), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7768 {"zmheouians", VX(4, 0x625), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7769 {"zmheosi", VX(4, 0x628), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7770 {"zmheosiaa", VX(4, 0x62A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7771 {"zmheosiaas", VX(4, 0x62B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7772 {"zmheosian", VX(4, 0x62C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7773 {"zmheosians", VX(4, 0x62D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7774 {"zmheosui", VX(4, 0x630), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7775 {"zmheosuiaa", VX(4, 0x632), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7776 {"zmheosuiaas", VX(4, 0x633), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7777 {"zmheosuian", VX(4, 0x634), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7778 {"zmheosuians", VX(4, 0x635), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7779 {"zmheosf", VX(4, 0x638), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7780 {"zmheosfr", VX(4, 0x639), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7781 {"zmheosfaas", VX(4, 0x63A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7782 {"zmheosfraas", VX(4, 0x63B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7783 {"zmheosfans", VX(4, 0x63C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7784 {"zmheosfrans", VX(4, 0x63D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7785 {"zmhoui", VX(4, 0x640), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7786 {"zmhouiaa", VX(4, 0x642), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7787 {"zmhouiaas", VX(4, 0x643), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7788 {"zmhouian", VX(4, 0x644), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7789 {"zmhouians", VX(4, 0x645), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7790 {"zmhosi", VX(4, 0x648), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7791 {"zmhosiaa", VX(4, 0x64A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7792 {"zmhosiaas", VX(4, 0x64B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7793 {"zmhosian", VX(4, 0x64C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7794 {"zmhosians", VX(4, 0x64D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7795 {"zmhosui", VX(4, 0x650), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7796 {"zmhosuiaa", VX(4, 0x652), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7797 {"zmhosuiaas", VX(4, 0x653), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7798 {"zmhosuian", VX(4, 0x654), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7799 {"zmhosuians", VX(4, 0x655), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7800 {"zmhosf", VX(4, 0x658), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7801 {"zmhosfr", VX(4, 0x659), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7802 {"zmhosfaas", VX(4, 0x65A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7803 {"zmhosfraas", VX(4, 0x65B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7804 {"zmhosfans", VX(4, 0x65C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7805 {"zmhosfrans", VX(4, 0x65D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7806 {"zvmhuih", VX(4, 0x660), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7807 {"zvmhuihs", VX(4, 0x661), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7808 {"zvmhuiaah", VX(4, 0x662), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7809 {"zvmhuiaahs", VX(4, 0x663), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7810 {"zvmhuianh", VX(4, 0x664), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7811 {"zvmhuianhs", VX(4, 0x665), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7812 {"zvmhsihs", VX(4, 0x669), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7813 {"zvmhsiaahs", VX(4, 0x66B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7814 {"zvmhsianhs", VX(4, 0x66D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7815 {"zvmhsuihs", VX(4, 0x671), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7816 {"zvmhsuiaahs", VX(4, 0x673), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7817 {"zvmhsuianhs", VX(4, 0x675), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7818 {"zvmhsfh", VX(4, 0x678), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7819 {"zvmhsfrh", VX(4, 0x679), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7820 {"zvmhsfaahs", VX(4, 0x67A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7821 {"zvmhsfraahs", VX(4, 0x67B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7822 {"zvmhsfanhs", VX(4, 0x67C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7823 {"zvmhsfranhs", VX(4, 0x67D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7824 {"zvdotphaui", VX(4, 0x680), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7825 {"zvdotphauis", VX(4, 0x681), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7826 {"zvdotphauiaa", VX(4, 0x682), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7827 {"zvdotphauiaas", VX(4, 0x683), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7828 {"zvdotphauian", VX(4, 0x684), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7829 {"zvdotphauians", VX(4, 0x685), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7830 {"zvdotphasi", VX(4, 0x688), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7831 {"zvdotphasis", VX(4, 0x689), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7832 {"zvdotphasiaa", VX(4, 0x68A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7833 {"zvdotphasiaas", VX(4, 0x68B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7834 {"zvdotphasian", VX(4, 0x68C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7835 {"zvdotphasians", VX(4, 0x68D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7836 {"zvdotphasui", VX(4, 0x690), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7837 {"zvdotphasuis", VX(4, 0x691), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7838 {"zvdotphasuiaa", VX(4, 0x692), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7839 {"zvdotphasuiaas", VX(4, 0x693), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7840 {"zvdotphasuian", VX(4, 0x694), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7841 {"zvdotphasuians", VX(4, 0x695), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7842 {"zvdotphasfs", VX(4, 0x698), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7843 {"zvdotphasfrs", VX(4, 0x699), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7844 {"zvdotphasfaas", VX(4, 0x69A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7845 {"zvdotphasfraas", VX(4, 0x69B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7846 {"zvdotphasfans", VX(4, 0x69C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7847 {"zvdotphasfrans", VX(4, 0x69D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7848 {"zvdotphxaui", VX(4, 0x6A0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7849 {"zvdotphxauis", VX(4, 0x6A1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7850 {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7851 {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7852 {"zvdotphxauian", VX(4, 0x6A4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7853 {"zvdotphxauians", VX(4, 0x6A5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7854 {"zvdotphxasi", VX(4, 0x6A8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7855 {"zvdotphxasis", VX(4, 0x6A9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7856 {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7857 {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7858 {"zvdotphxasian", VX(4, 0x6AC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7859 {"zvdotphxasians", VX(4, 0x6AD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7860 {"zvdotphxasui", VX(4, 0x6B0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7861 {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7862 {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7863 {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7864 {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7865 {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7866 {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7867 {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7868 {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7869 {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7870 {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7871 {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7872 {"zvdotphsui", VX(4, 0x6C0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7873 {"zvdotphsuis", VX(4, 0x6C1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7874 {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7875 {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7876 {"zvdotphsuian", VX(4, 0x6C4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7877 {"zvdotphsuians", VX(4, 0x6C5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7878 {"zvdotphssi", VX(4, 0x6C8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7879 {"zvdotphssis", VX(4, 0x6C9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7880 {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7881 {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7882 {"zvdotphssian", VX(4, 0x6CC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7883 {"zvdotphssians", VX(4, 0x6CD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7884 {"zvdotphssui", VX(4, 0x6D0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7885 {"zvdotphssuis", VX(4, 0x6D1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7886 {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7887 {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7888 {"zvdotphssuian", VX(4, 0x6D4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7889 {"zvdotphssuians", VX(4, 0x6D5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7890 {"zvdotphssfs", VX(4, 0x6D8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7891 {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7892 {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7893 {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7894 {"zvdotphssfans", VX(4, 0x6DC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7895 {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7896 {"zmwluis", VX(4, 0x6E1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7897 {"zmwluiaa", VX(4, 0x6E2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7898 {"zmwluiaas", VX(4, 0x6E3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7899 {"zmwluian", VX(4, 0x6E4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7900 {"zmwluians", VX(4, 0x6E5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7901 {"zmwlsis", VX(4, 0x6E9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7902 {"zmwlsiaas", VX(4, 0x6EB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7903 {"zmwlsians", VX(4, 0x6ED), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7904 {"zmwlsuis", VX(4, 0x6F1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7905 {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7906 {"zmwlsuians", VX(4, 0x6F5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7907 {"zmwsf", VX(4, 0x6F8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7908 {"zmwsfr", VX(4, 0x6F9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7909 {"zmwsfaas", VX(4, 0x6FA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7910 {"zmwsfraas", VX(4, 0x6FB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7911 {"zmwsfans", VX(4, 0x6FC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7912 {"zmwsfrans", VX(4, 0x6FD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7913 {"zlddx", VX(4, 0x300), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7914 {"zldd", VX(4, 0x301), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
7915 {"zldwx", VX(4, 0x302), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7916 {"zldw", VX(4, 0x303), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
7917 {"zldhx", VX(4, 0x304), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7918 {"zldh", VX(4, 0x305), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
7919 {"zlwgsfdx", VX(4, 0x308), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7920 {"zlwgsfd", VX(4, 0x309), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
7921 {"zlwwosdx", VX(4, 0x30A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7922 {"zlwwosd", VX(4, 0x30B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
7923 {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7924 {"zlwhsplatwd", VX(4, 0x30D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
7925 {"zlwhsplatdx", VX(4, 0x30E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7926 {"zlwhsplatd", VX(4, 0x30F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
7927 {"zlwhgwsfdx", VX(4, 0x310), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7928 {"zlwhgwsfd", VX(4, 0x311), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
7929 {"zlwhedx", VX(4, 0x312), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7930 {"zlwhed", VX(4, 0x313), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
7931 {"zlwhosdx", VX(4, 0x314), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7932 {"zlwhosd", VX(4, 0x315), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
7933 {"zlwhoudx", VX(4, 0x316), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7934 {"zlwhoud", VX(4, 0x317), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
7935 {"zlwhx", VX(4, 0x318), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7936 {"zlwh", VX(4, 0x319), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4
, RA
}},
7937 {"zlwwx", VX(4, 0x31A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7938 {"zlww", VX(4, 0x31B), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4
, RA
}},
7939 {"zlhgwsfx", VX(4, 0x31C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7940 {"zlhgwsf", VX(4, 0x31D), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
7941 {"zlhhsplatx", VX(4, 0x31E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7942 {"zlhhsplat", VX(4, 0x31F), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
7943 {"zstddx", VX(4, 0x320), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
7944 {"zstdd", VX(4, 0x321), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
7945 {"zstdwx", VX(4, 0x322), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
7946 {"zstdw", VX(4, 0x323), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
7947 {"zstdhx", VX(4, 0x324), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
7948 {"zstdh", VX(4, 0x325), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
7949 {"zstwhedx", VX(4, 0x328), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
7950 {"zstwhed", VX(4, 0x329), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4
, RA
}},
7951 {"zstwhodx", VX(4, 0x32A), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
7952 {"zstwhod", VX(4, 0x32B), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4
, RA
}},
7953 {"zlhhex", VX(4, 0x330), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7954 {"zlhhe", VX(4, 0x331), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
7955 {"zlhhosx", VX(4, 0x332), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7956 {"zlhhos", VX(4, 0x333), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
7957 {"zlhhoux", VX(4, 0x334), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7958 {"zlhhou", VX(4, 0x335), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
7959 {"zsthex", VX(4, 0x338), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
7960 {"zsthe", VX(4, 0x339), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2
, RA
}},
7961 {"zsthox", VX(4, 0x33A), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
7962 {"zstho", VX(4, 0x33B), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2
, RA
}},
7963 {"zstwhx", VX(4, 0x33C), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
7964 {"zstwh", VX(4, 0x33D), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4
, RA
}},
7965 {"zstwwx", VX(4, 0x33E), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
7966 {"zstww", VX(4, 0x33F), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4
, RA
}},
7967 {"zlddmx", VX(4, 0x340), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7968 {"zlddu", VX(4, 0x341), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
7969 {"zldwmx", VX(4, 0x342), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7970 {"zldwu", VX(4, 0x343), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
7971 {"zldhmx", VX(4, 0x344), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7972 {"zldhu", VX(4, 0x345), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
7973 {"zlwgsfdmx", VX(4, 0x348), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7974 {"zlwgsfdu", VX(4, 0x349), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
7975 {"zlwwosdmx", VX(4, 0x34A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7976 {"zlwwosdu", VX(4, 0x34B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
7977 {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7978 {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
7979 {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7980 {"zlwhsplatdu", VX(4, 0x34F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
7981 {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7982 {"zlwhgwsfdu", VX(4, 0x351), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
7983 {"zlwhedmx", VX(4, 0x352), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7984 {"zlwhedu", VX(4, 0x353), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
7985 {"zlwhosdmx", VX(4, 0x354), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7986 {"zlwhosdu", VX(4, 0x355), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
7987 {"zlwhoudmx", VX(4, 0x356), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7988 {"zlwhoudu", VX(4, 0x357), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
7989 {"zlwhmx", VX(4, 0x358), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7990 {"zlwhu", VX(4, 0x359), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
7991 {"zlwwmx", VX(4, 0x35A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7992 {"zlwwu", VX(4, 0x35B), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
7993 {"zlhgwsfmx", VX(4, 0x35C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7994 {"zlhgwsfu", VX(4, 0x35D), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
7995 {"zlhhsplatmx", VX(4, 0x35E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7996 {"zlhhsplatu", VX(4, 0x35F), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
7997 {"zstddmx", VX(4, 0x360), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
7998 {"zstddu", VX(4, 0x361), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
7999 {"zstdwmx", VX(4, 0x362), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8000 {"zstdwu", VX(4, 0x363), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8_EX0
, RA
}},
8001 {"zstdhmx", VX(4, 0x364), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8002 {"zstdhu", VX(4, 0x365), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8_EX0
, RA
}},
8003 {"zstwhedmx", VX(4, 0x368), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8004 {"zstwhedu", VX(4, 0x369), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4_EX0
, RA
}},
8005 {"zstwhodmx", VX(4, 0x36A), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8006 {"zstwhodu", VX(4, 0x36B), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4_EX0
, RA
}},
8007 {"zlhhemx", VX(4, 0x370), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8008 {"zlhheu", VX(4, 0x371), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8009 {"zlhhosmx", VX(4, 0x372), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8010 {"zlhhosu", VX(4, 0x373), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8011 {"zlhhoumx", VX(4, 0x374), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8012 {"zlhhouu", VX(4, 0x375), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8013 {"zsthemx", VX(4, 0x378), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8014 {"zstheu", VX(4, 0x379), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
8015 {"zsthomx", VX(4, 0x37A), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8016 {"zsthou", VX(4, 0x37B), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
8017 {"zstwhmx", VX(4, 0x37C), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8018 {"zstwhu", VX(4, 0x37D), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
8019 {"zstwwmx", VX(4, 0x37E), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8020 {"zstwwu", VX(4, 0x37F), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
8022 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8023 {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8024 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8025 {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8026 {"e_addi", SCI8(6,16), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8027 {"e_subi", SCI8(6,16), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
8028 {"e_addi.", SCI8(6,17), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8029 {"e_addic", SCI8(6,18), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8030 {"e_subic", SCI8(6,18), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
8031 {"e_addic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8032 {"e_subic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
8033 {"e_mulli", SCI8(6,20), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8034 {"e_subfic", SCI8(6,22), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8035 {"e_subfic.", SCI8(6,23), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8036 {"e_andi", SCI8(6,24), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8037 {"e_andi.", SCI8(6,25), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8038 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE
, 0, {0}},
8039 {"e_ori", SCI8(6,26), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8040 {"e_ori.", SCI8(6,27), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8041 {"e_xori", SCI8(6,28), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8042 {"e_xori.", SCI8(6,29), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8043 {"e_lbzu", OPVUP(6,0), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8044 {"e_lhau", OPVUP(6,3), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8045 {"e_lhzu", OPVUP(6,1), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8046 {"e_lmw", OPVUP(6,8), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8047 {"e_lwzu", OPVUP(6,2), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8048 {"e_stbu", OPVUP(6,4), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8049 {"e_sthu", OPVUP(6,5), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8050 {"e_stwu", OPVUP(6,6), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8051 {"e_stmw", OPVUP(6,9), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8052 {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8053 {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8054 {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8055 {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8056 {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8057 {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8058 {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8059 {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8060 {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8061 {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8062 {"e_add16i", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, RA
, SI
}},
8063 {"e_la", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8064 {"e_sub16i", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, RA
, NSI
}},
8066 {"se_addi", SE_IM5(8,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8067 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8068 {"se_subi", SE_IM5(9,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8069 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8070 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8071 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8072 {"se_andi", SE_IM5(11,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8074 {"e_lbz", OP(12), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8075 {"e_stb", OP(13), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8076 {"e_lha", OP(14), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8078 {"se_srw", SE_RR(16,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8079 {"se_sraw", SE_RR(16,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8080 {"se_slw", SE_RR(16,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8081 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE
, 0, {0}},
8082 {"se_or", SE_RR(17,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8083 {"se_andc", SE_RR(17,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8084 {"se_and", SE_RR(17,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8085 {"se_and.", SE_RR(17,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8086 {"se_li", IM7(9), IM7_MASK
, PPCVLE
, 0, {RX
, UI7
}},
8088 {"e_lwz", OP(20), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8089 {"e_stw", OP(21), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8090 {"e_lhz", OP(22), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8091 {"e_sth", OP(23), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8093 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8094 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8095 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8096 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8097 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8098 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8099 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8101 {"e_lis", I16L(28,28), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8102 {"e_and2is.", I16L(28,29), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8103 {"e_or2is", I16L(28,26), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8104 {"e_and2i.", I16L(28,25), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8105 {"e_or2i", I16L(28,24), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8106 {"e_cmphl16i", IA16(28,23), IA16_MASK
, PPCVLE
, 0, {RA
, VLEUIMM
}},
8107 {"e_cmph16i", IA16(28,22), IA16_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8108 {"e_cmpl16i", I16A(28,21), I16A_MASK
, PPCVLE
, 0, {RA
, VLEUIMM
}},
8109 {"e_mull2i", I16A(28,20), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8110 {"e_cmp16i", IA16(28,19), IA16_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8111 {"e_sub2is", I16A(28,18), I16A_MASK
, PPCVLE
, 0, {RA
, VLENSIMM
}},
8112 {"e_add2is", I16A(28,18), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8113 {"e_sub2i.", I16A(28,17), I16A_MASK
, PPCVLE
, 0, {RA
, VLENSIMM
}},
8114 {"e_add2i.", I16A(28,17), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8115 {"e_li", LI20(28,0), LI20_MASK
, PPCVLE
, 0, {RT
, IMM20
}},
8116 {"e_rlwimi", M(29,0), M_MASK
, PPCVLE
, 0, {RA
, RS
, SH
, MB
, ME
}},
8117 {"e_rlwinm", M(29,1), M_MASK
, PPCVLE
, 0, {RA
, RT
, SH
, MBE
, ME
}},
8118 {"e_b", BD24(30,0,0), BD24_MASK
, PPCVLE
, 0, {B24
}},
8119 {"e_bl", BD24(30,0,1), BD24_MASK
, PPCVLE
, 0, {B24
}},
8120 {"e_bdnz", EBD15(30,8,BO32DNZ
,0), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8121 {"e_bdnzl", EBD15(30,8,BO32DNZ
,1), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8122 {"e_bdz", EBD15(30,8,BO32DZ
,0), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8123 {"e_bdzl", EBD15(30,8,BO32DZ
,1), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8124 {"e_bge", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8125 {"e_bgel", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8126 {"e_bnl", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8127 {"e_bnll", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8128 {"e_blt", EBD15BI(30,8,BO32T
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8129 {"e_bltl", EBD15BI(30,8,BO32T
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8130 {"e_bgt", EBD15BI(30,8,BO32T
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8131 {"e_bgtl", EBD15BI(30,8,BO32T
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8132 {"e_ble", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8133 {"e_blel", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8134 {"e_bng", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8135 {"e_bngl", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8136 {"e_bne", EBD15BI(30,8,BO32F
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8137 {"e_bnel", EBD15BI(30,8,BO32F
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8138 {"e_beq", EBD15BI(30,8,BO32T
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8139 {"e_beql", EBD15BI(30,8,BO32T
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8140 {"e_bso", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8141 {"e_bsol", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8142 {"e_bun", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8143 {"e_bunl", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8144 {"e_bns", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8145 {"e_bnsl", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8146 {"e_bnu", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8147 {"e_bnul", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8148 {"e_bc", BD15(30,8,0), BD15_MASK
, PPCVLE
, 0, {BO32
, BI32
, B15
}},
8149 {"e_bcl", BD15(30,8,1), BD15_MASK
, PPCVLE
, 0, {BO32
, BI32
, B15
}},
8151 {"e_bf", EBD15(30,8,BO32F
,0), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8152 {"e_bfl", EBD15(30,8,BO32F
,1), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8153 {"e_bt", EBD15(30,8,BO32T
,0), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8154 {"e_btl", EBD15(30,8,BO32T
,1), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8156 {"e_cmph", X(31,14), X_MASK
, PPCVLE
, 0, {CRD
, RA
, RB
}},
8157 {"e_sc", X(31,36), XRTRA_MASK
, PPCVLE
, 0, {ELEV
}},
8158 {"e_cmphl", X(31,46), X_MASK
, PPCVLE
, 0, {CRD
, RA
, RB
}},
8159 {"e_crandc", XL(31,129), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8160 {"e_crnand", XL(31,225), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8161 {"e_crnot", XL(31,33), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BBA
}},
8162 {"e_crnor", XL(31,33), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8163 {"e_crclr", XL(31,193), XL_MASK
, PPCVLE
, 0, {BT
, BAT
, BBA
}},
8164 {"e_crxor", XL(31,193), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8165 {"e_mcrf", XL(31,16), XL_MASK
, PPCVLE
, 0, {CRD
, CR
}},
8166 {"e_slwi", EX(31,112), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8167 {"e_slwi.", EX(31,113), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8169 {"e_crand", XL(31,257), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8171 {"e_rlw", EX(31,560), EX_MASK
, PPCVLE
, 0, {RA
, RS
, RB
}},
8172 {"e_rlw.", EX(31,561), EX_MASK
, PPCVLE
, 0, {RA
, RS
, RB
}},
8174 {"e_crset", XL(31,289), XL_MASK
, PPCVLE
, 0, {BT
, BAT
, BBA
}},
8175 {"e_creqv", XL(31,289), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8177 {"e_rlwi", EX(31,624), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8178 {"e_rlwi.", EX(31,625), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8180 {"e_crorc", XL(31,417), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8182 {"e_crmove", XL(31,449), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BBA
}},
8183 {"e_cror", XL(31,449), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8185 {"mtmas1", XSPR(31,467,625), XSPR_MASK
, PPCVLE
, 0, {RS
}},
8187 {"e_srwi", EX(31,1136), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8188 {"e_srwi.", EX(31,1137), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8190 {"se_lbz", SD4(8), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SD
, RX
}},
8192 {"se_stb", SD4(9), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SD
, RX
}},
8194 {"se_lhz", SD4(10), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDH
, RX
}},
8196 {"se_sth", SD4(11), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDH
, RX
}},
8198 {"se_lwz", SD4(12), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDW
, RX
}},
8200 {"se_stw", SD4(13), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDW
, RX
}},
8202 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8203 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8204 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8205 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8206 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8207 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8208 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8209 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK
, PPCVLE
, 0, {BI16
, B8
}},
8210 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8211 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8212 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8213 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8214 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8215 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK
, PPCVLE
, 0, {BI16
, B8
}},
8216 {"se_bc", BD8IO(28), BD8IO_MASK
, PPCVLE
, 0, {BO16
, BI16
, B8
}},
8217 {"se_b", BD8(58,0,0), BD8_MASK
, PPCVLE
, 0, {B8
}},
8218 {"se_bl", BD8(58,0,1), BD8_MASK
, PPCVLE
, 0, {B8
}},
8221 const int vle_num_opcodes
=
8222 sizeof (vle_opcodes
) / sizeof (vle_opcodes
[0]);
8224 /* The macro table. This is only used by the assembler. */
8226 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
8227 when x=0; 32-x when x is between 1 and 31; are negative if x is
8228 negative; and are 32 or more otherwise. This is what you want
8229 when, for instance, you are emulating a right shift by a
8230 rotate-left-and-mask, because the underlying instructions support
8231 shifts of size 0 but not shifts of size 32. By comparison, when
8232 extracting x bits from some word you want to use just 32-x, because
8233 the underlying instructions don't support extracting 0 bits but do
8234 support extracting the whole word (32 bits in this case). */
8236 const struct powerpc_macro powerpc_macros
[] = {
8237 {"extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1"},
8238 {"extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1"},
8239 {"extrdi", 4, PPC64
, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
8240 {"extrdi.", 4, PPC64
, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
8241 {"insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3"},
8242 {"insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
8243 {"rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
8244 {"rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
8245 {"sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)"},
8246 {"sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)"},
8247 {"srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
8248 {"srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
8249 {"clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)"},
8250 {"clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)"},
8251 {"clrlsldi", 4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)"},
8252 {"clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)"},
8254 {"extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1"},
8255 {"extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1"},
8256 {"extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8257 {"extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8258 {"inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8259 {"inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8260 {"insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8261 {"insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8262 {"rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8263 {"rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8264 {"slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)"},
8265 {"sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)"},
8266 {"slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)"},
8267 {"sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)"},
8268 {"srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8269 {"sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8270 {"srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8271 {"sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8272 {"clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)"},
8273 {"clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)"},
8274 {"clrlslwi", 4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
8275 {"clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
8277 {"e_extlwi", 4, PPCVLE
, "e_rlwinm %0,%1,%3,0,(%2)-1"},
8278 {"e_extrwi", 4, PPCVLE
, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8279 {"e_inslwi", 4, PPCVLE
, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8280 {"e_insrwi", 4, PPCVLE
, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8281 {"e_rotlwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31"},
8282 {"e_rotrwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8283 {"e_slwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31-(%2)"},
8284 {"e_srwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8285 {"e_clrlwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,%2,31"},
8286 {"e_clrrwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,0,31-(%2)"},
8287 {"e_clrlslwi",4, PPCVLE
, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
8290 const int powerpc_num_macros
=
8291 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);