opcodes/tic80-opc.c

   1 /* Opcode table for TI TMS320C80 (MVP).
   2    Copyright 1996 Free Software Foundation, Inc.
   3
   4 This file is part of GDB, GAS, and the GNU binutils.
   5
   6 GDB, GAS, and the GNU binutils are free software; you can redistribute
   7 them and/or modify them under the terms of the GNU General Public
   8 License as published by the Free Software Foundation; either version
   9 1, or (at your option) any later version.
  10
  11 GDB, GAS, and the GNU binutils are distributed in the hope that they
  12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  14 the GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this file; see the file COPYING.  If not, write to the Free
  18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include <stdio.h>
  21 #include "ansidecl.h"
  22 #include "opcode/tic80.h"
  23
  24 /* This file holds the TMS320C80 (MVP) opcode table.  The table is
  25    strictly constant data, so the compiler should be able to put it in
  26    the .text section.
  27
  28    This file also holds the operand table.  All knowledge about
  29    inserting operands into instructions and vice-versa is kept in this
  30    file.  */
  31
  32 \f
  33 /* The operands table.  The fields are:
  34
  35         bits, shift, insertion function, extraction function, flags
  36  */
  37
  38 const struct tic80_operand tic80_operands[] =
  39 {
  40
  41   /* The zero index is used to indicate the end of the list of operands.  */
  42
  43 #define UNUSED (0)
  44   { 0, 0, 0, 0, 0 },
  45
  46   /* Short signed immediate value in bits 14-0. */
  47
  48 #define SSI (UNUSED + 1)
  49   { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  50
  51   /* Short unsigned immediate value in bits 14-0 */
  52
  53 #define SUI (SSI + 1)
  54   { 15, 0, NULL, NULL, 0 },
  55
  56   /* Short unsigned bitfield in bits 14-0.  We distinguish this
  57      from a regular unsigned immediate value only for the convenience
  58      of the disassembler and the user. */
  59
  60 #define SUBF (SUI + 1)
  61   { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  62
  63   /* Long signed immediate in following 32 bit word */
  64
  65 #define LSI (SUBF + 1)
  66   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  67
  68   /* Long unsigned immediate in following 32 bit word */
  69
  70 #define LUI (LSI + 1)
  71   { 32, 0, NULL, NULL, 0 },
  72
  73   /* Long unsigned bitfield in following 32 bit word.  We distinguish
  74      this from a regular unsigned immediate value only for the
  75      convenience of the disassembler and the user. */
  76
  77 #define LUBF (LUI + 1)
  78   { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  79
  80   /* Register in bits 4-0 */
  81
  82 #define REG0 (LUBF + 1)
  83   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
  84
  85   /* Register in bits 26-22 */
  86
  87 #define REG22 (REG0 + 1)
  88   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
  89
  90   /* Register in bits 31-27 */
  91
  92 #define REG27 (REG22 + 1)
  93   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
  94
  95   /* Short signed offset in bits 14-0 */
  96
  97 #define SSOFF (REG27 + 1)
  98   { 15, 0, NULL, NULL, TIC80_OPERAND_RELATIVE | TIC80_OPERAND_SIGNED },
  99
 100   /* Long signed offset in following 32 bit word */
 101
 102 #define LSOFF (SSOFF + 1)
 103   {32, 0, NULL, NULL, TIC80_OPERAND_RELATIVE | TIC80_OPERAND_SIGNED },
 104
 105   /* BITNUM in bits 31-27 */
 106
 107 #define BITNUM (LSOFF + 1)
 108   { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
 109
 110   /* Condition code in bits 31-27 */
 111
 112 #define CC (BITNUM + 1)
 113   { 5, 27, NULL, NULL, TIC80_OPERAND_CC },
 114
 115   /* Control register number in bits 14-0 */
 116
 117 #define SICR (CC + 1)
 118   { 15, 0, NULL, NULL, TIC80_OPERAND_CR },
 119
 120   /* Control register number in next 32 bit word */
 121
 122 #define LICR (SICR + 1)
 123   { 32, 0, NULL, NULL, TIC80_OPERAND_CR },
 124
 125 };
 126
 127 const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
 128
 129 \f
 130 /* Macros used to generate entries for the opcodes table. */
 131
 132 #define FIXME 0
 133
 134 /* Short-Immediate Format Instructions */
 135 #define OP_SI(x)        (((x) & 0x7F) << 15)
 136 #define MASK_SI         OP_SI(0x7F)
 137 #define MASK_SI_M       OP_SI(0x7B)     /* Short-Immediate with embedded M bit */
 138
 139 /* Long-Immediate Format Instructions */
 140 #define OP_LI(x)        (((x) & 0x3FF) << 12)
 141 #define MASK_LI         OP_LI(0x3FF)
 142 #define MASK_LI_M       OP_LI(0x3F7)    /* Long-Immediate with embedded M bit */
 143
 144 /* Register Format Instructions */
 145 #define OP_REG(x)       OP_LI(x)        /* For readability */
 146 #define MASK_REG        MASK_LI         /* For readability */
 147 #define MASK_REG_M      MASK_LI_M       /* For readability */
 148
 149 const struct tic80_opcode tic80_opcodes[] = {
 150
 151   /* The "nop" instruction is really "rdcr 0,r0".  We put it first so that this
 152      specific bit pattern will get dissembled as a nop rather than an rdcr. The
 153      mask of all ones ensures that this will happen. */
 154
 155   {"nop",       OP_SI(0x4),     ~0,             0,              {0}                     },
 156
 157   /* The "br" instruction is really "bbz target,r0,31".  We put it first so that
 158      this specific bit pattern will get disassembled as a br rather than bbz. */
 159
 160   {"br",        OP_SI(0x48),    0xFFFF8000,     0,              {SSOFF}                 },
 161   {"br",        OP_LI(0x391),   0xFFFFF000,     0,              {LSOFF}                 },
 162   {"br",        OP_REG(0x390),  0xFFFFF000,     0,              {REG0}                  },
 163
 164   {"br.a",      OP_SI(0x49),    0xFFFF8000,     0,              {SSOFF}                 },
 165   {"br.a",      OP_LI(0x393),   0xFFFFF000,     0,              {LSOFF}                 },
 166   {"br.a",      OP_REG(0x392),  0xFFFFF000,     0,              {REG0}                  },
 167
 168   /* Signed integer ADD */
 169
 170   {"add",       OP_SI(0x58),    MASK_SI,        FMT_SI,         {SSI, REG22, REG27}     },
 171   {"add",       OP_LI(0x3B1),   MASK_LI,        FMT_LI,         {LSI, REG22, REG27}     },
 172   {"add",       OP_REG(0x3B0),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 173
 174   /* Unsigned integer ADD */
 175
 176   {"addu",      OP_SI(0x59),    MASK_SI,        FMT_SI,         {SSI, REG22, REG27}     },
 177   {"addu",      OP_LI(0x3B3),   MASK_LI,        FMT_LI,         {LSI, REG22, REG27}     },
 178   {"addu",      OP_REG(0x3B2),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 179
 180   /* Bitwise AND */
 181
 182   {"and",       OP_SI(0x11),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 183   {"and",       OP_LI(0x323),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 184   {"and",       OP_REG(0x322),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 185
 186   {"and.tt",    OP_SI(0x11),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 187   {"and.tt",    OP_LI(0x323),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 188   {"and.tt",    OP_REG(0x322),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 189
 190   /* Bitwise AND with ones complement of both sources */
 191
 192   {"and.ff",    OP_SI(0x18),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 193   {"and.ff",    OP_LI(0x331),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 194   {"and.ff",    OP_REG(0x330),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 195
 196   /* Bitwise AND with ones complement of source 1 */
 197
 198   {"and.ft",    OP_SI(0x14),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 199   {"and.ft",    OP_LI(0x329),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 200   {"and.ft",    OP_REG(0x328),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 201
 202   /* Bitwise AND with ones complement of source 2 */
 203
 204   {"and.tf",    OP_SI(0x12),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 205   {"and.tf",    OP_LI(0x325),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 206   {"and.tf",    OP_REG(0x324),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 207
 208   /* Branch Bit One - nonannulled */
 209
 210   {"bbo",       OP_SI(0x4A),    MASK_SI,        FMT_SI,         {SSOFF, REG22, BITNUM}  },
 211   {"bbo",       OP_LI(0x395),   MASK_LI,        FMT_LI,         {LSOFF, REG22, BITNUM}  },
 212   {"bbo",       OP_REG(0x394),  MASK_REG,       FMT_REG,        {REG0, REG22, BITNUM}   },
 213
 214   /* Branch Bit One - annulled */
 215
 216   {"bbo.a",     OP_SI(0x4B),    MASK_SI,        FMT_SI,         {SSOFF, REG22, BITNUM}  },
 217   {"bbo.a",     OP_LI(0x397),   MASK_LI,        FMT_LI,         {LSOFF, REG22, BITNUM}  },
 218   {"bbo.a",     OP_REG(0x396),  MASK_REG,       FMT_REG,        {REG0, REG22, BITNUM}   },
 219
 220   /* Branch Bit Zero - nonannulled */
 221
 222   {"bbz",       OP_SI(0x48),    MASK_SI,        FMT_SI,         {SSOFF, REG22, BITNUM}  },
 223   {"bbz",       OP_LI(0x391),   MASK_LI,        FMT_LI,         {LSOFF, REG22, BITNUM}  },
 224   {"bbz",       OP_REG(0x390),  MASK_REG,       FMT_REG,        {REG0, REG22, BITNUM}   },
 225
 226   /* Branch Bit Zero - annulled */
 227
 228   {"bbz.a",     OP_SI(0x49),    MASK_SI,        FMT_SI,         {SSOFF, REG22, BITNUM}  },
 229   {"bbz.a",     OP_LI(0x393),   MASK_LI,        FMT_LI,         {LSOFF, REG22, BITNUM}  },
 230   {"bbz.a",     OP_REG(0x392),  MASK_REG,       FMT_REG,        {REG0, REG22, BITNUM}   },
 231
 232   /* Branch Conditional - nonannulled */
 233
 234   {"bcnd",      OP_SI(0x4C),    MASK_SI,        FMT_SI,         {SSOFF, REG22, CC}      },
 235   {"bcnd",      OP_LI(0x399),   MASK_LI,        FMT_LI,         {LSOFF, REG22, CC}      },
 236   {"bcnd",      OP_REG(0x398),  MASK_REG,       FMT_REG,        {REG0, REG22, CC}       },
 237
 238   /* Branch Conditional - annulled */
 239
 240   {"bcnd.a",    OP_SI(0x4D),    MASK_SI,        FMT_SI,         {SSOFF, REG22, CC}      },
 241   {"bcnd.a",    OP_LI(0x39B),   MASK_LI,        FMT_LI,         {LSOFF, REG22, CC}      },
 242   {"bcnd.a",    OP_REG(0x39A),  MASK_REG,       FMT_REG,        {REG0, REG22, CC}       },
 243
 244   /* Branch Control Register */
 245
 246   {"brcr",      OP_SI(0x6),     MASK_SI,        FMT_SI,         {SICR}                  },
 247   {"brcr",      OP_LI(0x30D),   MASK_LI,        FMT_LI,         {LICR}                  },
 248   {"brcr",      OP_REG(0x30C),  MASK_REG,       FMT_REG,        {REG0}                  },
 249
 250   /* WORK IN PROGRESS BELOW THIS POINT */
 251
 252   {"cmnd",      OP_LI(0x305),   MASK_LI,        FMT_LI,         FIXME},
 253   {"cmnd",      OP_REG(0x304),  MASK_REG,       FMT_REG,        FIXME},
 254   {"cmnd",      OP_SI(0x2),     MASK_SI,        FMT_SI,         FIXME},
 255   {"illop0",    OP_SI(0),       MASK_SI,        FMT_SI,         FIXME},
 256   {"ld",        OP_LI(0x345),   MASK_LI_M,      FMT_LI,         FIXME},
 257   {"ld",        OP_REG(0x344),  MASK_REG_M,     FMT_REG,        FIXME},
 258   {"ld",        OP_SI(0x22),    MASK_SI_M,      FMT_SI,         FIXME},
 259   {"ld.b",      OP_LI(0x341),   MASK_LI_M,      FMT_LI,         FIXME},
 260   {"ld.b",      OP_REG(0x340),  MASK_REG_M,     FMT_REG,        FIXME},
 261   {"ld.b",      OP_SI(0x20),    MASK_SI_M,      FMT_SI,         FIXME},
 262   {"ld.d",      OP_LI(0x347),   MASK_LI_M,      FMT_LI,         FIXME},
 263   {"ld.d",      OP_REG(0x346),  MASK_REG_M,     FMT_REG,        FIXME},
 264   {"ld.d",      OP_SI(0x23),    MASK_SI_M,      FMT_SI,         FIXME},
 265   {"ld.h",      OP_LI(0x343),   MASK_LI_M,      FMT_LI,         FIXME},
 266   {"ld.h",      OP_REG(0x342),  MASK_REG_M,     FMT_REG,        FIXME},
 267   {"ld.h",      OP_SI(0x21),    MASK_SI_M,      FMT_SI,         FIXME},
 268   {"ld.u",      OP_LI(0x355),   MASK_LI_M,      FMT_LI,         FIXME},
 269   {"ld.u",      OP_REG(0x354),  MASK_REG_M,     FMT_REG,        FIXME},
 270   {"ld.u",      OP_SI(0x2A),    MASK_SI_M,      FMT_SI,         FIXME},
 271   {"ld.ub",     OP_LI(0x351),   MASK_LI_M,      FMT_LI,         FIXME},
 272   {"ld.ub",     OP_REG(0x350),  MASK_REG_M,     FMT_REG,        FIXME},
 273   {"ld.ub",     OP_SI(0x28),    MASK_SI_M,      FMT_SI,         FIXME},
 274   {"ld.ud",     OP_LI(0x357),   MASK_LI_M,      FMT_LI,         FIXME},
 275   {"ld.ud",     OP_REG(0x356),  MASK_REG_M,     FMT_REG,        FIXME},
 276   {"ld.ud",     OP_SI(0x2B),    MASK_SI_M,      FMT_SI,         FIXME},
 277   {"ld.uh",     OP_LI(0x353),   MASK_LI_M,      FMT_LI,         FIXME},
 278   {"ld.uh",     OP_REG(0x352),  MASK_REG_M,     FMT_REG,        FIXME},
 279   {"ld.uh",     OP_SI(0x29),    MASK_SI_M,      FMT_SI,         FIXME},
 280   {"or.ff",     OP_LI(0x33D),   MASK_LI,        FMT_LI,         FIXME},
 281   {"or.ff",     OP_REG(0x33C),  MASK_REG,       FMT_REG,        FIXME},
 282   {"or.ff",     OP_SI(0x1E),    MASK_SI,        FMT_SI,         FIXME},
 283   {"or.ft",     OP_LI(0x33B),   MASK_LI,        FMT_LI,         FIXME},
 284   {"or.ft",     OP_REG(0x33A),  MASK_REG,       FMT_REG,        FIXME},
 285   {"or.ft",     OP_SI(0x1D),    MASK_SI,        FMT_SI,         FIXME},
 286   {"or.tf",     OP_LI(0x337),   MASK_LI,        FMT_LI,         FIXME},
 287   {"or.tf",     OP_REG(0x336),  MASK_REG,       FMT_REG,        FIXME},
 288   {"or.tf",     OP_SI(0x1B),    MASK_SI,        FMT_SI,         FIXME},
 289   {"or.tt",     OP_LI(0x32F),   MASK_LI,        FMT_LI,         FIXME},
 290   {"or.tt",     OP_REG(0x32E),  MASK_REG,       FMT_REG,        FIXME},
 291   {"or.tt",     OP_SI(0x17),    MASK_SI,        FMT_SI,         FIXME},
 292   {"rdcr",      OP_LI(0x309),   MASK_LI,        FMT_LI,         FIXME},
 293   {"rdcr",      OP_REG(0x308),  MASK_REG,       FMT_REG,        FIXME},
 294   {"rdcr",      OP_SI(0x4),     MASK_SI,        FMT_SI,         FIXME},
 295   {"shift.dm",  OP_REG(0x312),  MASK_REG,       FMT_REG,        FIXME},
 296   {"shift.dm",  OP_SI(0x9),     MASK_SI,        FMT_SI,         FIXME},
 297   {"shift.ds",  OP_REG(0x314),  MASK_REG,       FMT_REG,        FIXME},
 298   {"shift.ds",  OP_SI(0xA),     MASK_SI,        FMT_SI,         FIXME},
 299   {"shift.dz",  OP_REG(0x310),  MASK_REG,       FMT_REG,        FIXME},
 300   {"shift.dz",  OP_SI(0x8),     MASK_SI,        FMT_SI,         FIXME},
 301   {"shift.em",  OP_REG(0x318),  MASK_REG,       FMT_REG,        FIXME},
 302   {"shift.em",  OP_SI(0xC),     MASK_SI,        FMT_SI,         FIXME},
 303   {"shift.es",  OP_REG(0x31A),  MASK_REG,       FMT_REG,        FIXME},
 304   {"shift.es",  OP_SI(0xD),     MASK_SI,        FMT_SI,         FIXME},
 305   {"shift.ez",  OP_REG(0x316),  MASK_REG,       FMT_REG,        FIXME},
 306   {"shift.ez",  OP_SI(0xB),     MASK_SI,        FMT_SI,         FIXME},
 307   {"shift.im",  OP_REG(0x31E),  MASK_REG,       FMT_REG,        FIXME},
 308   {"shift.im",  OP_SI(0xF),     MASK_SI,        FMT_SI,         FIXME},
 309   {"shift.iz",  OP_REG(0x31C),  MASK_REG,       FMT_REG,        FIXME},
 310   {"shift.iz",  OP_SI(0xE),     MASK_SI,        FMT_SI,         FIXME},
 311   {"st",        OP_LI(0x365),   MASK_LI_M,      FMT_LI,         FIXME},
 312   {"st",        OP_REG(0x364),  MASK_REG_M,     FMT_REG,        FIXME},
 313   {"st",        OP_SI(0x32),    MASK_SI_M,      FMT_SI,         FIXME},
 314   {"st.b",      OP_LI(0x361),   MASK_LI_M,      FMT_LI,         FIXME},
 315   {"st.b",      OP_REG(0x360),  MASK_REG_M,     FMT_REG,        FIXME},
 316   {"st.b",      OP_SI(0x30),    MASK_SI_M,      FMT_SI,         FIXME},
 317   {"st.d",      OP_LI(0x367),   MASK_LI_M,      FMT_LI,         FIXME},
 318   {"st.d",      OP_REG(0x366),  MASK_REG_M,     FMT_REG,        FIXME},
 319   {"st.d",      OP_SI(0x33),    MASK_SI_M,      FMT_SI,         FIXME},
 320   {"st.h",      OP_LI(0x363),   MASK_LI_M,      FMT_LI,         FIXME},
 321   {"st.h",      OP_REG(0x362),  MASK_REG_M,     FMT_REG,        FIXME},
 322   {"st.h",      OP_SI(0x31),    MASK_SI_M,      FMT_SI,         FIXME},
 323   {"swcr",      OP_LI(0x30B),   MASK_LI,        FMT_LI,         FIXME},
 324   {"swcr",      OP_REG(0x30A),  MASK_REG,       FMT_REG,        FIXME},
 325   {"swcr",      OP_SI(0x5),     MASK_SI,        FMT_SI,         FIXME},
 326   {"trap",      OP_LI(0x303),   MASK_LI,        FMT_LI,         FIXME},
 327   {"trap",      OP_REG(0x302),  MASK_REG,       FMT_REG,        FIXME},
 328   {"trap",      OP_SI(0x1),     MASK_SI,        FMT_SI,         FIXME},
 329   {"xnor",      OP_LI(0x333),   MASK_LI,        FMT_LI,         FIXME},
 330   {"xnor",      OP_REG(0x332),  MASK_REG,       FMT_REG,        FIXME},
 331   {"xnor",      OP_SI(0x19),    MASK_SI,        FMT_SI,         FIXME},
 332   {"xor",       OP_LI(0x32D),   MASK_LI,        FMT_LI,         FIXME},
 333   {"xor",       OP_REG(0x32C),  MASK_REG,       FMT_REG,        FIXME},
 334   {"xor",       OP_SI(0x16),    MASK_SI,        FMT_SI,         FIXME},
 335
 336 };
 337
 338 const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
 339