opcodes/tic80-opc.c

   1 /* Opcode table for TI TMS320C80 (MVP).
   2    Copyright 1996 Free Software Foundation, Inc.
   3
   4 This file is part of GDB, GAS, and the GNU binutils.
   5
   6 GDB, GAS, and the GNU binutils are free software; you can redistribute
   7 them and/or modify them under the terms of the GNU General Public
   8 License as published by the Free Software Foundation; either version
   9 1, or (at your option) any later version.
  10
  11 GDB, GAS, and the GNU binutils are distributed in the hope that they
  12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  14 the GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this file; see the file COPYING.  If not, write to the Free
  18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include <stdio.h>
  21 #include "ansidecl.h"
  22 #include "opcode/tic80.h"
  23
  24 /* This file holds the TMS320C80 (MVP) opcode table.  The table is
  25    strictly constant data, so the compiler should be able to put it in
  26    the .text section.
  27
  28    This file also holds the operand table.  All knowledge about
  29    inserting operands into instructions and vice-versa is kept in this
  30    file.  */
  31
  32 \f
  33 /* The operands table.  The fields are:
  34
  35         bits, shift, insertion function, extraction function, flags
  36  */
  37
  38 const struct tic80_operand tic80_operands[] =
  39 {
  40
  41   /* The zero index is used to indicate the end of the list of operands.  */
  42
  43 #define UNUSED (0)
  44   { 0, 0, 0, 0, 0 },
  45
  46   /* Short signed immediate value in bits 14-0. */
  47
  48 #define SSI (UNUSED + 1)
  49   { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  50
  51   /* Short unsigned immediate value in bits 14-0 */
  52
  53 #define SUI (SSI + 1)
  54   { 15, 0, NULL, NULL, 0 },
  55
  56   /* Short unsigned bitfield in bits 14-0.  We distinguish this
  57      from a regular unsigned immediate value only for the convenience
  58      of the disassembler and the user. */
  59
  60 #define SUBF (SUI + 1)
  61   { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  62
  63   /* Long signed immediate in following 32 bit word */
  64
  65 #define LSI (SUBF + 1)
  66   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  67
  68   /* Long unsigned immediate in following 32 bit word */
  69
  70 #define LUI (LSI + 1)
  71   { 32, 0, NULL, NULL, 0 },
  72
  73   /* Long unsigned bitfield in following 32 bit word.  We distinguish
  74      this from a regular unsigned immediate value only for the
  75      convenience of the disassembler and the user. */
  76
  77 #define LUBF (LUI + 1)
  78   { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  79
  80   /* Register in bits 4-0 */
  81
  82 #define REG_0 (LUBF + 1)
  83   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
  84
  85   /* Register in bits 26-22 */
  86
  87 #define REG_22 (REG_0 + 1)
  88   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
  89
  90   /* Register in bits 31-27 */
  91
  92 #define REG_DEST (REG_22 + 1)
  93   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
  94
  95   /* Short signed offset in bits 14-0 */
  96
  97 #define OFF_SS (REG_DEST + 1)
  98   { 15, 0, NULL, NULL, TIC80_OPERAND_RELATIVE | TIC80_OPERAND_SIGNED },
  99
 100   /* Long signed offset in following 32 bit word */
 101
 102 #define OFF_SL (OFF_SS + 1)
 103   {32, 0, NULL, NULL, TIC80_OPERAND_RELATIVE | TIC80_OPERAND_SIGNED },
 104
 105   /* BITNUM in bits 31-27 */
 106
 107 #define BITNUM (OFF_SL + 1)
 108   { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
 109
 110   /* Condition code in bits 31-27 */
 111
 112 #define CC (BITNUM + 1)
 113   { 5, 27, NULL, NULL, TIC80_OPERAND_CC },
 114
 115   /* Control register number in bits 14-0 */
 116
 117 #define CR_SI (CC + 1)
 118   { 15, 0, NULL, NULL, TIC80_OPERAND_CR },
 119
 120   /* Control register number in next 32 bit word */
 121
 122 #define CR_LI (CR_SI + 1)
 123   { 32, 0, NULL, NULL, TIC80_OPERAND_CR },
 124
 125   /* A base register in bits 26-22, enclosed in parens, with optional ":m"
 126      flag in bit 17 (short immediate instructions only) */
 127
 128 #define REG_BASE_M_SI (CR_LI + 1)
 129   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
 130
 131   /* A base register in bits 26-22, enclosed in parens, with optional ":m"
 132    flag in bit 15 (long immediate and register instructions only) */
 133
 134 #define REG_BASE_M_LI (REG_BASE_M_SI + 1)
 135   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
 136
 137   /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */
 138
 139 #define REG_SCALED (REG_BASE_M_LI + 1)
 140   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
 141
 142   /* Long signed immediate in following 32 bit word, with optional ":s" modifier
 143      flag in bit 11 */
 144
 145 #define LSI_SCALED (REG_SCALED + 1)
 146   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
 147 };
 148
 149 const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
 150
 151 \f
 152 /* Macros used to generate entries for the opcodes table. */
 153
 154 #define FIXME 0
 155
 156 /* Short-Immediate Format Instructions - basic opcode */
 157 #define OP_SI(x)        (((x) & 0x7F) << 15)
 158 #define MASK_SI         OP_SI(0x7F)
 159
 160 /* Long-Immediate Format Instructions - basic opcode */
 161 #define OP_LI(x)        (((x) & 0x3FF) << 12)
 162 #define MASK_LI         OP_LI(0x3FF)
 163
 164 /* Register Format Instructions - basic opcode */
 165 #define OP_REG(x)       OP_LI(x)        /* For readability */
 166 #define MASK_REG        MASK_LI         /* For readability */
 167
 168 /* The 'F' bit at bit 27 */
 169 #define F(x)            ((x) << 27)
 170
 171 /* The 'E' bit at bit 27 */
 172 #define E(x)            ((x) << 27)
 173
 174 /* The 'M' bit at bit 15 in register and long immediate opcodes */
 175 #define M_REG(x)        ((x) << 15)
 176 #define M_LI(x)         ((x) << 15)
 177
 178 /* The 'M' bit at bit 17 in short immediate opcodes */
 179 #define M_SI(x)         ((x) << 17)
 180
 181 /* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
 182 #define SZ_REG(x)       ((x) << 13)
 183 #define SZ_LI(x)        ((x) << 13)
 184
 185 /* The 'SZ' field at bits 16-15 in short immediate opcodes */
 186 #define SZ_SI(x)        ((x) << 15)
 187
 188 /* The 'D' (direct external memory access) bit at bit 10 in long immediate
 189    and register opcodes. */
 190 #define D(x)            ((x) << 10)
 191
 192 /* The 'S' (scale offset by data size) bit at bit 11 in long immediate
 193    and register opcodes. */
 194 #define S(x)            ((x) << 11)
 195
 196 \f
 197 const struct tic80_opcode tic80_opcodes[] = {
 198
 199   /* The "nop" instruction is really "rdcr 0,r0".  We put it first so that this
 200      specific bit pattern will get disassembled as a nop rather than an rdcr. The
 201      mask of all ones ensures that this will happen. */
 202
 203   {"nop",       OP_SI(0x4),     ~0,             0,              {0}                     },
 204
 205   /* The "br" instruction is really "bbz target,r0,31".  We put it first so that
 206      this specific bit pattern will get disassembled as a br rather than bbz. */
 207
 208   {"br",        OP_SI(0x48),    0xFFFF8000,     0,              {OFF_SS}                        },
 209   {"br",        OP_LI(0x391),   0xFFFFF000,     0,              {OFF_SL}                        },
 210   {"br",        OP_REG(0x390),  0xFFFFF000,     0,              {REG_0}                 },
 211
 212   {"br.a",      OP_SI(0x49),    0xFFFF8000,     0,              {OFF_SS}                        },
 213   {"br.a",      OP_LI(0x393),   0xFFFFF000,     0,              {OFF_SL}                        },
 214   {"br.a",      OP_REG(0x392),  0xFFFFF000,     0,              {REG_0}                 },
 215
 216   /* Signed integer ADD */
 217
 218   {"add",       OP_SI(0x58),    MASK_SI,        FMT_SI,         {SSI, REG_22, REG_DEST} },
 219   {"add",       OP_LI(0x3B1),   MASK_LI,        FMT_LI,         {LSI, REG_22, REG_DEST} },
 220   {"add",       OP_REG(0x3B0),  MASK_REG,       FMT_REG,        {REG_0, REG_22, REG_DEST}       },
 221
 222   /* Unsigned integer ADD */
 223
 224   {"addu",      OP_SI(0x59),    MASK_SI,        FMT_SI,         {SSI, REG_22, REG_DEST} },
 225   {"addu",      OP_LI(0x3B3),   MASK_LI,        FMT_LI,         {LSI, REG_22, REG_DEST} },
 226   {"addu",      OP_REG(0x3B2),  MASK_REG,       FMT_REG,        {REG_0, REG_22, REG_DEST}       },
 227
 228   /* Bitwise AND */
 229
 230   {"and",       OP_SI(0x11),    MASK_SI,        FMT_SI,         {SUBF, REG_22, REG_DEST}        },
 231   {"and",       OP_LI(0x323),   MASK_LI,        FMT_LI,         {LUBF, REG_22, REG_DEST}        },
 232   {"and",       OP_REG(0x322),  MASK_REG,       FMT_REG,        {REG_0, REG_22, REG_DEST}       },
 233
 234   {"and.tt",    OP_SI(0x11),    MASK_SI,        FMT_SI,         {SUBF, REG_22, REG_DEST}        },
 235   {"and.tt",    OP_LI(0x323),   MASK_LI,        FMT_LI,         {LUBF, REG_22, REG_DEST}        },
 236   {"and.tt",    OP_REG(0x322),  MASK_REG,       FMT_REG,        {REG_0, REG_22, REG_DEST}       },
 237
 238   /* Bitwise AND with ones complement of both sources */
 239
 240   {"and.ff",    OP_SI(0x18),    MASK_SI,        FMT_SI,         {SUBF, REG_22, REG_DEST}        },
 241   {"and.ff",    OP_LI(0x331),   MASK_LI,        FMT_LI,         {LUBF, REG_22, REG_DEST}        },
 242   {"and.ff",    OP_REG(0x330),  MASK_REG,       FMT_REG,        {REG_0, REG_22, REG_DEST}       },
 243
 244   /* Bitwise AND with ones complement of source 1 */
 245
 246   {"and.ft",    OP_SI(0x14),    MASK_SI,        FMT_SI,         {SUBF, REG_22, REG_DEST}        },
 247   {"and.ft",    OP_LI(0x329),   MASK_LI,        FMT_LI,         {LUBF, REG_22, REG_DEST}        },
 248   {"and.ft",    OP_REG(0x328),  MASK_REG,       FMT_REG,        {REG_0, REG_22, REG_DEST}       },
 249
 250   /* Bitwise AND with ones complement of source 2 */
 251
 252   {"and.tf",    OP_SI(0x12),    MASK_SI,        FMT_SI,         {SUBF, REG_22, REG_DEST}        },
 253   {"and.tf",    OP_LI(0x325),   MASK_LI,        FMT_LI,         {LUBF, REG_22, REG_DEST}        },
 254   {"and.tf",    OP_REG(0x324),  MASK_REG,       FMT_REG,        {REG_0, REG_22, REG_DEST}       },
 255
 256   /* Branch Bit One - nonannulled */
 257
 258   {"bbo",       OP_SI(0x4A),    MASK_SI,        FMT_SI,         {OFF_SS, REG_22, BITNUM}        },
 259   {"bbo",       OP_LI(0x395),   MASK_LI,        FMT_LI,         {OFF_SL, REG_22, BITNUM}        },
 260   {"bbo",       OP_REG(0x394),  MASK_REG,       FMT_REG,        {REG_0, REG_22, BITNUM} },
 261
 262   /* Branch Bit One - annulled */
 263
 264   {"bbo.a",     OP_SI(0x4B),    MASK_SI,        FMT_SI,         {OFF_SS, REG_22, BITNUM}        },
 265   {"bbo.a",     OP_LI(0x397),   MASK_LI,        FMT_LI,         {OFF_SL, REG_22, BITNUM}        },
 266   {"bbo.a",     OP_REG(0x396),  MASK_REG,       FMT_REG,        {REG_0, REG_22, BITNUM} },
 267
 268   /* Branch Bit Zero - nonannulled */
 269
 270   {"bbz",       OP_SI(0x48),    MASK_SI,        FMT_SI,         {OFF_SS, REG_22, BITNUM}        },
 271   {"bbz",       OP_LI(0x391),   MASK_LI,        FMT_LI,         {OFF_SL, REG_22, BITNUM}        },
 272   {"bbz",       OP_REG(0x390),  MASK_REG,       FMT_REG,        {REG_0, REG_22, BITNUM} },
 273
 274   /* Branch Bit Zero - annulled */
 275
 276   {"bbz.a",     OP_SI(0x49),    MASK_SI,        FMT_SI,         {OFF_SS, REG_22, BITNUM}        },
 277   {"bbz.a",     OP_LI(0x393),   MASK_LI,        FMT_LI,         {OFF_SL, REG_22, BITNUM}        },
 278   {"bbz.a",     OP_REG(0x392),  MASK_REG,       FMT_REG,        {REG_0, REG_22, BITNUM} },
 279
 280   /* Branch Conditional - nonannulled */
 281
 282   {"bcnd",      OP_SI(0x4C),    MASK_SI,        FMT_SI,         {OFF_SS, REG_22, CC}    },
 283   {"bcnd",      OP_LI(0x399),   MASK_LI,        FMT_LI,         {OFF_SL, REG_22, CC}    },
 284   {"bcnd",      OP_REG(0x398),  MASK_REG,       FMT_REG,        {REG_0, REG_22, CC}     },
 285
 286   /* Branch Conditional - annulled */
 287
 288   {"bcnd.a",    OP_SI(0x4D),    MASK_SI,        FMT_SI,         {OFF_SS, REG_22, CC}    },
 289   {"bcnd.a",    OP_LI(0x39B),   MASK_LI,        FMT_LI,         {OFF_SL, REG_22, CC}    },
 290   {"bcnd.a",    OP_REG(0x39A),  MASK_REG,       FMT_REG,        {REG_0, REG_22, CC}     },
 291
 292   /* Branch Control Register */
 293
 294   {"brcr",      OP_SI(0x6),     MASK_SI,        FMT_SI,         {CR_SI}                 },
 295   {"brcr",      OP_LI(0x30D),   MASK_LI,        FMT_LI,         {CR_LI}                 },
 296   {"brcr",      OP_REG(0x30C),  MASK_REG,       FMT_REG,        {REG_0}                 },
 297
 298   /* Branch and save return - nonannulled */
 299
 300   {"bsr",       OP_SI(0x40),    MASK_SI,        FMT_SI,         {OFF_SS, REG_DEST}      },
 301   {"bsr",       OP_LI(0x381),   MASK_LI,        FMT_LI,         {OFF_SL, REG_DEST}      },
 302   {"bsr",       OP_REG(0x380),  MASK_REG,       FMT_REG,        {REG_0, REG_DEST}       },
 303
 304   /* Branch and save return - annulled */
 305
 306   {"bsr.a",     OP_SI(0x41),    MASK_SI,        FMT_SI,         {OFF_SS, REG_DEST}      },
 307   {"bsr.a",     OP_LI(0x383),   MASK_LI,        FMT_LI,         {OFF_SL, REG_DEST}      },
 308   {"bsr.a",     OP_REG(0x382),  MASK_REG,       FMT_REG,        {REG_0, REG_DEST}       },
 309
 310   /* Send command */
 311
 312   {"cmnd",      OP_SI(0x2),     MASK_SI,        FMT_SI,         {SUI}                   },
 313   {"cmnd",      OP_LI(0x305),   MASK_LI,        FMT_LI,         {LUI}                   },
 314   {"cmnd",      OP_REG(0x304),  MASK_REG,       FMT_REG,        {REG_0}                 },
 315
 316   /* Integer compare */
 317
 318   {"cmp",       OP_SI(0x50),    MASK_SI,        FMT_SI,         {SSI, REG_22, REG_DEST}         },
 319   {"cmp",       OP_LI(0x3A1),   MASK_LI,        FMT_LI,         {LSI, REG_22, REG_DEST}         },
 320   {"cmp",       OP_REG(0x3A0),  MASK_REG,       FMT_REG,        {REG_0, REG_22, REG_DEST}       },
 321
 322   /* Flush data cache subblock - don't clear subblock preset flag */
 323
 324   {"dcachec",   OP_SI(0x38),    F(1) | (MASK_SI & ~M_SI(1)),                    FMT_SI, {SSI, REG_BASE_M_SI}    },
 325   {"dcachec",   OP_LI(0x371),   F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1),      FMT_LI, {LSI, REG_BASE_M_LI}    },
 326   {"dcachec",   OP_REG(0x370),  F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),    FMT_REG, {REG_0, REG_BASE_M_LI} },
 327
 328   /* Flush data cache subblock - clear subblock preset flag */
 329
 330   {"dcachef",   OP_SI(0x38) | F(1),     F(1) | (MASK_SI & ~M_SI(1)),                    FMT_SI, {SSI, REG_BASE_M_SI}    },
 331   {"dcachef",   OP_LI(0x371) | F(1),    F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1),      FMT_LI, {LSI, REG_BASE_M_LI}    },
 332   {"dcachef",   OP_REG(0x370) | F(1),   F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),    FMT_REG, {REG_0, REG_BASE_M_LI} },
 333
 334   /* Direct load signed data into register */
 335
 336   {"dld.b",     OP_LI(0x341) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   FMT_LI,         {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 337   {"dld.b",     OP_REG(0x340) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  FMT_REG,        {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 338
 339   {"dld.h",     OP_LI(0x343) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   FMT_LI,         {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 340   {"dld.h",     OP_REG(0x342) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  FMT_REG,        {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 341
 342   {"dld",       OP_LI(0x345) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   FMT_LI,         {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 343   {"dld",       OP_REG(0x344) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  FMT_REG,        {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 344
 345   {"dld.d",     OP_LI(0x347) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   FMT_LI,         {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 346   {"dld.d",     OP_REG(0x346) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  FMT_REG,        {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 347
 348   /* Direct load unsigned data into register */
 349
 350   {"dld.ub",    OP_LI(0x351) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   FMT_LI,         {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 351   {"dld.ub",    OP_REG(0x350) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  FMT_REG,        {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 352
 353   {"dld.uh",    OP_LI(0x353) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   FMT_LI,         {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 354   {"dld.uh",    OP_REG(0x352) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  FMT_REG,        {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 355
 356   /* Direct store data into memory */
 357
 358   {"dst.b",     OP_LI(0x361) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   FMT_LI,         {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 359   {"dst.b",     OP_REG(0x360) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  FMT_REG,        {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 360
 361   {"dst.h",     OP_LI(0x363) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   FMT_LI,         {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 362   {"dst.h",     OP_REG(0x362) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  FMT_REG,        {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 363
 364   {"dst",       OP_LI(0x365) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   FMT_LI,         {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 365   {"dst",       OP_REG(0x364) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  FMT_REG,        {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 366
 367   {"dst.d",     OP_LI(0x367) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   FMT_LI,         {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 368   {"dst.d",     OP_REG(0x366) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  FMT_REG,        {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 369
 370   /* Emulation stop */
 371
 372   {"estop",     OP_LI(0x3FC),   MASK_LI,        FMT_LI,         {0}     },
 373
 374   /* Emulation trap */
 375
 376   {"etrap",     OP_SI(0x1) | E(1),      MASK_SI | E(1),         FMT_SI,         {SUI}   },
 377   {"etrap",     OP_LI(0x303) | E(1),    MASK_LI | E(1),         FMT_LI,         {LUI}   },
 378   {"etrap",     OP_REG(0x302) | E(1),   MASK_REG | E(1),        FMT_REG,        {REG_0} },
 379
 380   /* WORK IN PROGRESS BELOW THIS POINT */
 381
 382   {"illop0",    OP_SI(0),       MASK_SI,        FMT_SI,         FIXME},
 383
 384   {"ld",        OP_LI(0x345),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 385   {"ld",        OP_REG(0x344),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 386   {"ld",        OP_SI(0x22),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 387   {"ld.b",      OP_LI(0x341),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 388   {"ld.b",      OP_REG(0x340),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 389   {"ld.b",      OP_SI(0x20),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 390   {"ld.d",      OP_LI(0x347),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 391   {"ld.d",      OP_REG(0x346),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 392   {"ld.d",      OP_SI(0x23),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 393   {"ld.h",      OP_LI(0x343),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 394   {"ld.h",      OP_REG(0x342),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 395   {"ld.h",      OP_SI(0x21),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 396   {"ld.u",      OP_LI(0x355),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 397   {"ld.u",      OP_REG(0x354),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 398   {"ld.u",      OP_SI(0x2A),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 399   {"ld.ub",     OP_LI(0x351),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 400   {"ld.ub",     OP_REG(0x350),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 401   {"ld.ub",     OP_SI(0x28),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 402   {"ld.ud",     OP_LI(0x357),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 403   {"ld.ud",     OP_REG(0x356),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 404   {"ld.ud",     OP_SI(0x2B),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 405   {"ld.uh",     OP_LI(0x353),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 406   {"ld.uh",     OP_REG(0x352),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 407   {"ld.uh",     OP_SI(0x29),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 408   {"or.ff",     OP_LI(0x33D),   MASK_LI,        FMT_LI,         FIXME},
 409   {"or.ff",     OP_REG(0x33C),  MASK_REG,       FMT_REG,        FIXME},
 410   {"or.ff",     OP_SI(0x1E),    MASK_SI,        FMT_SI,         FIXME},
 411   {"or.ft",     OP_LI(0x33B),   MASK_LI,        FMT_LI,         FIXME},
 412   {"or.ft",     OP_REG(0x33A),  MASK_REG,       FMT_REG,        FIXME},
 413   {"or.ft",     OP_SI(0x1D),    MASK_SI,        FMT_SI,         FIXME},
 414   {"or.tf",     OP_LI(0x337),   MASK_LI,        FMT_LI,         FIXME},
 415   {"or.tf",     OP_REG(0x336),  MASK_REG,       FMT_REG,        FIXME},
 416   {"or.tf",     OP_SI(0x1B),    MASK_SI,        FMT_SI,         FIXME},
 417   {"or.tt",     OP_LI(0x32F),   MASK_LI,        FMT_LI,         FIXME},
 418   {"or.tt",     OP_REG(0x32E),  MASK_REG,       FMT_REG,        FIXME},
 419   {"or.tt",     OP_SI(0x17),    MASK_SI,        FMT_SI,         FIXME},
 420   {"rdcr",      OP_LI(0x309),   MASK_LI,        FMT_LI,         FIXME},
 421   {"rdcr",      OP_REG(0x308),  MASK_REG,       FMT_REG,        FIXME},
 422   {"rdcr",      OP_SI(0x4),     MASK_SI,        FMT_SI,         FIXME},
 423   {"shift.dm",  OP_REG(0x312),  MASK_REG,       FMT_REG,        FIXME},
 424   {"shift.dm",  OP_SI(0x9),     MASK_SI,        FMT_SI,         FIXME},
 425   {"shift.ds",  OP_REG(0x314),  MASK_REG,       FMT_REG,        FIXME},
 426   {"shift.ds",  OP_SI(0xA),     MASK_SI,        FMT_SI,         FIXME},
 427   {"shift.dz",  OP_REG(0x310),  MASK_REG,       FMT_REG,        FIXME},
 428   {"shift.dz",  OP_SI(0x8),     MASK_SI,        FMT_SI,         FIXME},
 429   {"shift.em",  OP_REG(0x318),  MASK_REG,       FMT_REG,        FIXME},
 430   {"shift.em",  OP_SI(0xC),     MASK_SI,        FMT_SI,         FIXME},
 431   {"shift.es",  OP_REG(0x31A),  MASK_REG,       FMT_REG,        FIXME},
 432   {"shift.es",  OP_SI(0xD),     MASK_SI,        FMT_SI,         FIXME},
 433   {"shift.ez",  OP_REG(0x316),  MASK_REG,       FMT_REG,        FIXME},
 434   {"shift.ez",  OP_SI(0xB),     MASK_SI,        FMT_SI,         FIXME},
 435   {"shift.im",  OP_REG(0x31E),  MASK_REG,       FMT_REG,        FIXME},
 436   {"shift.im",  OP_SI(0xF),     MASK_SI,        FMT_SI,         FIXME},
 437   {"shift.iz",  OP_REG(0x31C),  MASK_REG,       FMT_REG,        FIXME},
 438   {"shift.iz",  OP_SI(0xE),     MASK_SI,        FMT_SI,         FIXME},
 439   {"st",        OP_LI(0x365),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 440   {"st",        OP_REG(0x364),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 441   {"st",        OP_SI(0x32),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 442   {"st.b",      OP_LI(0x361),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 443   {"st.b",      OP_REG(0x360),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 444   {"st.b",      OP_SI(0x30),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 445   {"st.d",      OP_LI(0x367),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 446   {"st.d",      OP_REG(0x366),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 447   {"st.d",      OP_SI(0x33),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 448   {"st.h",      OP_LI(0x363),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 449   {"st.h",      OP_REG(0x362),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 450   {"st.h",      OP_SI(0x31),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 451   {"swcr",      OP_LI(0x30B),   MASK_LI,        FMT_LI,         FIXME},
 452   {"swcr",      OP_REG(0x30A),  MASK_REG,       FMT_REG,        FIXME},
 453   {"swcr",      OP_SI(0x5),     MASK_SI,        FMT_SI,         FIXME},
 454   {"trap",      OP_LI(0x303),   MASK_LI,        FMT_LI,         FIXME},
 455   {"trap",      OP_REG(0x302),  MASK_REG,       FMT_REG,        FIXME},
 456   {"trap",      OP_SI(0x1),     MASK_SI,        FMT_SI,         FIXME},
 457   {"xnor",      OP_LI(0x333),   MASK_LI,        FMT_LI,         FIXME},
 458   {"xnor",      OP_REG(0x332),  MASK_REG,       FMT_REG,        FIXME},
 459   {"xnor",      OP_SI(0x19),    MASK_SI,        FMT_SI,         FIXME},
 460   {"xor",       OP_LI(0x32D),   MASK_LI,        FMT_LI,         FIXME},
 461   {"xor",       OP_REG(0x32C),  MASK_REG,       FMT_REG,        FIXME},
 462   {"xor",       OP_SI(0x16),    MASK_SI,        FMT_SI,         FIXME},
 463
 464 };
 465
 466 const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
 467