opcodes/tic80-opc.c

   1 /* Opcode table for TI TMS320C80 (MVP).
   2    Copyright 1996 Free Software Foundation, Inc.
   3
   4 This file is part of GDB, GAS, and the GNU binutils.
   5
   6 GDB, GAS, and the GNU binutils are free software; you can redistribute
   7 them and/or modify them under the terms of the GNU General Public
   8 License as published by the Free Software Foundation; either version
   9 1, or (at your option) any later version.
  10
  11 GDB, GAS, and the GNU binutils are distributed in the hope that they
  12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  14 the GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this file; see the file COPYING.  If not, write to the Free
  18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include <stdio.h>
  21 #include "ansidecl.h"
  22 #include "opcode/tic80.h"
  23
  24 /* This file holds the TMS320C80 (MVP) opcode table.  The table is
  25    strictly constant data, so the compiler should be able to put it in
  26    the .text section.
  27
  28    This file also holds the operand table.  All knowledge about
  29    inserting operands into instructions and vice-versa is kept in this
  30    file.  */
  31
  32 \f
  33 /* The operands table.  The fields are:
  34
  35         bits, shift, insertion function, extraction function, flags
  36  */
  37
  38 const struct tic80_operand tic80_operands[] =
  39 {
  40
  41   /* The zero index is used to indicate the end of the list of operands.  */
  42
  43 #define UNUSED (0)
  44   { 0, 0, 0, 0, 0 },
  45
  46   /* Short signed immediate value in bits 14-0. */
  47
  48 #define SSI (UNUSED + 1)
  49   { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  50
  51   /* Short unsigned immediate value in bits 14-0 */
  52
  53 #define SUI (SSI + 1)
  54   { 15, 0, NULL, NULL, 0 },
  55
  56   /* Short unsigned bitfield in bits 14-0.  We distinguish this
  57      from a regular unsigned immediate value only for the convenience
  58      of the disassembler and the user. */
  59
  60 #define SUBF (SUI + 1)
  61   { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  62
  63   /* Long signed immediate in following 32 bit word */
  64
  65 #define LSI (SUBF + 1)
  66   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  67
  68   /* Long unsigned immediate in following 32 bit word */
  69
  70 #define LUI (LSI + 1)
  71   { 32, 0, NULL, NULL, 0 },
  72
  73   /* Long unsigned bitfield in following 32 bit word.  We distinguish
  74      this from a regular unsigned immediate value only for the
  75      convenience of the disassembler and the user. */
  76
  77 #define LUBF (LUI + 1)
  78   { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  79
  80   /* Single precision floating point immediate in following 32 bit
  81      word. */
  82
  83 #define SPFI (LUBF + 1)
  84   { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
  85
  86   /* Register in bits 4-0 */
  87
  88 #define REG_0 (SPFI + 1)
  89   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
  90
  91   /* Register in bits 26-22 */
  92
  93 #define REG_22 (REG_0 + 1)
  94   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
  95
  96   /* Register in bits 31-27 */
  97
  98 #define REG_DEST (REG_22 + 1)
  99   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
 100
 101   /* Short signed PC word offset in bits 14-0 */
 102
 103 #define OFF_SS_PC (REG_DEST + 1)
 104   { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
 105
 106   /* Long signed PC word offset in following 32 bit word */
 107
 108 #define OFF_SL_PC (OFF_SS_PC + 1)
 109   {32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
 110
 111   /* Short signed base relative byte offset in bits 14-0 */
 112
 113 #define OFF_SS_BR (OFF_SL_PC + 1)
 114   { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
 115
 116   /* Long signed base relative byte offset in following 32 bit word */
 117
 118 #define OFF_SL_BR (OFF_SS_BR + 1)
 119   {32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
 120
 121   /* BITNUM in bits 31-27 */
 122
 123 #define BITNUM (OFF_SL_BR + 1)
 124   { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
 125
 126   /* Condition code in bits 31-27 */
 127
 128 #define CC (BITNUM + 1)
 129   { 5, 27, NULL, NULL, TIC80_OPERAND_CC },
 130
 131   /* Control register number in bits 14-0 */
 132
 133 #define CR_SI (CC + 1)
 134   { 15, 0, NULL, NULL, TIC80_OPERAND_CR },
 135
 136   /* Control register number in next 32 bit word */
 137
 138 #define CR_LI (CR_SI + 1)
 139   { 32, 0, NULL, NULL, TIC80_OPERAND_CR },
 140
 141   /* A base register in bits 26-22, enclosed in parens */
 142
 143 #define REG_BASE (CR_LI + 1)
 144   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS },
 145
 146   /* A base register in bits 26-22, enclosed in parens, with optional ":m"
 147      flag in bit 17 (short immediate instructions only) */
 148
 149 #define REG_BASE_M_SI (REG_BASE + 1)
 150   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
 151
 152   /* A base register in bits 26-22, enclosed in parens, with optional ":m"
 153    flag in bit 15 (long immediate and register instructions only) */
 154
 155 #define REG_BASE_M_LI (REG_BASE_M_SI + 1)
 156   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
 157
 158   /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */
 159
 160 #define REG_SCALED (REG_BASE_M_LI + 1)
 161   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
 162
 163   /* Long signed immediate in following 32 bit word, with optional ":s" modifier
 164      flag in bit 11 */
 165
 166 #define LSI_SCALED (REG_SCALED + 1)
 167   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
 168
 169   /* Unsigned immediate in bits 4-0, used only for shift instructions */
 170
 171 #define ROTATE (LSI_SCALED + 1)
 172   { 5, 0, NULL, NULL, 0 },
 173
 174   /* Unsigned immediate in bits 9-5, used only for shift instructions */
 175 #define ENDMASK (ROTATE + 1)
 176   { 5, 5, NULL, NULL, 0 },
 177
 178 };
 179
 180 const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
 181
 182 \f
 183 /* Macros used to generate entries for the opcodes table. */
 184
 185 #define FIXME 0
 186
 187 /* Short-Immediate Format Instructions - basic opcode */
 188 #define OP_SI(x)        (((x) & 0x7F) << 15)
 189 #define MASK_SI         OP_SI(0x7F)
 190
 191 /* Long-Immediate Format Instructions - basic opcode */
 192 #define OP_LI(x)        (((x) & 0x3FF) << 12)
 193 #define MASK_LI         OP_LI(0x3FF)
 194
 195 /* Register Format Instructions - basic opcode */
 196 #define OP_REG(x)       OP_LI(x)        /* For readability */
 197 #define MASK_REG        MASK_LI         /* For readability */
 198
 199 /* The 'n' bit at bit 10 */
 200 #define n(x)            ((x) << 10)
 201
 202 /* The 'i' bit at bit 11 */
 203 #define i(x)            ((x) << 11)
 204
 205 /* The 'F' bit at bit 27 */
 206 #define F(x)            ((x) << 27)
 207
 208 /* The 'E' bit at bit 27 */
 209 #define E(x)            ((x) << 27)
 210
 211 /* The 'M' bit at bit 15 in register and long immediate opcodes */
 212 #define M_REG(x)        ((x) << 15)
 213 #define M_LI(x)         ((x) << 15)
 214
 215 /* The 'M' bit at bit 17 in short immediate opcodes */
 216 #define M_SI(x)         ((x) << 17)
 217
 218 /* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
 219 #define SZ_REG(x)       ((x) << 13)
 220 #define SZ_LI(x)        ((x) << 13)
 221
 222 /* The 'SZ' field at bits 16-15 in short immediate opcodes */
 223 #define SZ_SI(x)        ((x) << 15)
 224
 225 /* The 'D' (direct external memory access) bit at bit 10 in long immediate
 226    and register opcodes. */
 227 #define D(x)            ((x) << 10)
 228
 229 /* The 'S' (scale offset by data size) bit at bit 11 in long immediate
 230    and register opcodes. */
 231 #define S(x)            ((x) << 11)
 232
 233 /* The 'PD' field at bits 10-9 in floating point instructions */
 234 #define PD(x)           ((x) << 9)
 235
 236 /* The 'P2' field at bits 8-7 in floating point instructions */
 237 #define P2(x)           ((x) << 7)
 238
 239 /* The 'P1' field at bits 6-5 in floating point instructions */
 240 #define P1(x)           ((x) << 5)
 241
 242 /* The 'a' field at bit 16 in vector instructions */
 243 #define V_a1(x)         ((x) << 16)
 244
 245 /* The 'a' field at bit 11 in vector instructions */
 246 #define V_a0(x)         ((x) << 11)
 247
 248 /* The 'm' field at bit 10 in vector instructions */
 249 #define V_m(x)          ((x) << 10)
 250
 251 /* The 'S' field at bit 9 in vector instructions */
 252 #define V_S(x)          ((x) << 9)
 253
 254 /* The 'Z' field at bit 8 in vector instructions */
 255 #define V_Z(x)          ((x) << 8)
 256
 257 /* The 'p' field at bit 6 in vector instructions */
 258 #define V_p(x)          ((x) << 6)
 259
 260 /* The opcode field at bits 21-17 for vector instructions */
 261 #define OP_V(x)         ((x) << 17)
 262 #define MASK_V          OP_V(0x1F)
 263
 264 \f
 265 /* The opcode table.  Formatted for better readability on a wide screen. */
 266
 267 const struct tic80_opcode tic80_opcodes[] = {
 268
 269   /* The "nop" instruction is really "rdcr 0,r0".  We put it first so that this
 270      specific bit pattern will get disassembled as a nop rather than an rdcr. The
 271      mask of all ones ensures that this will happen. */
 272
 273   {"nop",       OP_SI(0x4),     ~0,             0,              {0}                     },
 274
 275   /* The "br" instruction is really "bbz target,r0,31".  We put it first so that
 276      this specific bit pattern will get disassembled as a br rather than bbz. */
 277
 278   {"br",        OP_SI(0x48),    0xFFFF8000,     0,      {OFF_SS_PC}                     },
 279   {"br",        OP_REG(0x390),  0xFFFFF000,     0,      {REG_0}                 },
 280   {"br",        OP_LI(0x391),   0xFFFFF000,     0,      {OFF_SL_PC}                     },
 281
 282   {"br.a",      OP_SI(0x49),    0xFFFF8000,     0,      {OFF_SS_PC}                     },
 283   {"br.a",      OP_REG(0x392),  0xFFFFF000,     0,      {REG_0}                 },
 284   {"br.a",      OP_LI(0x393),   0xFFFFF000,     0,      {OFF_SL_PC}                     },
 285
 286   /* Signed integer ADD */
 287
 288   {"add",       OP_SI(0x58),    MASK_SI,        0,      {SSI, REG_22, REG_DEST} },
 289   {"add",       OP_REG(0x3B0),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 290   {"add",       OP_LI(0x3B1),   MASK_LI,        0,      {LSI, REG_22, REG_DEST} },
 291
 292   /* Unsigned integer ADD */
 293
 294   {"addu",      OP_SI(0x59),    MASK_SI,        0,      {SSI, REG_22, REG_DEST} },
 295   {"addu",      OP_REG(0x3B2),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 296   {"addu",      OP_LI(0x3B3),   MASK_LI,        0,      {LSI, REG_22, REG_DEST} },
 297
 298   /* Bitwise AND */
 299
 300   {"and",       OP_SI(0x11),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 301   {"and.tt",    OP_SI(0x11),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 302
 303   {"and",       OP_REG(0x322),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 304   {"and.tt",    OP_REG(0x322),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 305
 306   {"and",       OP_LI(0x323),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 307   {"and.tt",    OP_LI(0x323),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 308
 309   /* Bitwise AND with ones complement of both sources */
 310
 311   {"and.ff",    OP_SI(0x18),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 312   {"and.ff",    OP_REG(0x330),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 313   {"and.ff",    OP_LI(0x331),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 314
 315   /* Bitwise AND with ones complement of source 1 */
 316
 317   {"and.ft",    OP_SI(0x14),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 318   {"and.ft",    OP_REG(0x328),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 319   {"and.ft",    OP_LI(0x329),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 320
 321   /* Bitwise AND with ones complement of source 2 */
 322
 323   {"and.tf",    OP_SI(0x12),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 324   {"and.tf",    OP_REG(0x324),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 325   {"and.tf",    OP_LI(0x325),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 326
 327   /* Branch Bit One - nonannulled */
 328
 329   {"bbo",       OP_SI(0x4A),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 330   {"bbo",       OP_REG(0x394),  MASK_REG,       0,      {REG_0, REG_22, BITNUM} },
 331   {"bbo",       OP_LI(0x395),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 332
 333   /* Branch Bit One - annulled */
 334
 335   {"bbo.a",     OP_SI(0x4B),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 336   {"bbo.a",     OP_REG(0x396),  MASK_REG,       0,      {REG_0, REG_22, BITNUM} },
 337   {"bbo.a",     OP_LI(0x397),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 338
 339   /* Branch Bit Zero - nonannulled */
 340
 341   {"bbz",       OP_SI(0x48),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 342   {"bbz",       OP_REG(0x390),  MASK_REG,       0,      {REG_0, REG_22, BITNUM} },
 343   {"bbz",       OP_LI(0x391),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 344
 345   /* Branch Bit Zero - annulled */
 346
 347   {"bbz.a",     OP_SI(0x49),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 348   {"bbz.a",     OP_REG(0x392),  MASK_REG,       0,      {REG_0, REG_22, BITNUM} },
 349   {"bbz.a",     OP_LI(0x393),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 350
 351   /* Branch Conditional - nonannulled */
 352
 353   {"bcnd",      OP_SI(0x4C),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },
 354   {"bcnd",      OP_REG(0x398),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 355   {"bcnd",      OP_LI(0x399),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
 356
 357   /* Branch Conditional - annulled */
 358
 359   {"bcnd.a",    OP_SI(0x4D),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },
 360   {"bcnd.a",    OP_REG(0x39A),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 361   {"bcnd.a",    OP_LI(0x39B),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
 362
 363   /* Branch Control Register */
 364
 365   {"brcr",      OP_SI(0x6),     MASK_SI,        0,      {CR_SI}                 },
 366   {"brcr",      OP_REG(0x30C),  MASK_REG,       0,      {REG_0}                 },
 367   {"brcr",      OP_LI(0x30D),   MASK_LI,        0,      {CR_LI}                 },
 368
 369   /* Branch and save return - nonannulled */
 370
 371   {"bsr",       OP_SI(0x40),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },
 372   {"bsr",       OP_REG(0x380),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 373   {"bsr",       OP_LI(0x381),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
 374
 375   /* Branch and save return - annulled */
 376
 377   {"bsr.a",     OP_SI(0x41),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },
 378   {"bsr.a",     OP_REG(0x382),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 379   {"bsr.a",     OP_LI(0x383),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
 380
 381   /* Send command */
 382
 383   {"cmnd",      OP_SI(0x2),     MASK_SI,        0,      {SUI}                   },
 384   {"cmnd",      OP_REG(0x304),  MASK_REG,       0,      {REG_0}                 },
 385   {"cmnd",      OP_LI(0x305),   MASK_LI,        0,      {LUI}                   },
 386
 387   /* Integer compare */
 388
 389   {"cmp",       OP_SI(0x50),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
 390   {"cmp",       OP_REG(0x3A0),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 391   {"cmp",       OP_LI(0x3A1),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
 392
 393   /* Flush data cache subblock - don't clear subblock preset flag */
 394
 395   {"dcachec",   OP_SI(0x38),    F(1) | (MASK_SI & ~M_SI(1)),                    0, {SSI, REG_BASE_M_SI} },
 396   {"dcachec",   OP_REG(0x370),  F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),    0, {REG_0, REG_BASE_M_LI}       },
 397   {"dcachec",   OP_LI(0x371),   F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1),      0, {LSI, REG_BASE_M_LI} },
 398
 399   /* Flush data cache subblock - clear subblock preset flag */
 400
 401   {"dcachef",   OP_SI(0x38) | F(1),     F(1) | (MASK_SI & ~M_SI(1)),                    0, {SSI, REG_BASE_M_SI} },
 402   {"dcachef",   OP_REG(0x370) | F(1),   F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),    0, {REG_0, REG_BASE_M_LI}       },
 403   {"dcachef",   OP_LI(0x371) | F(1),    F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1),      0, {LSI, REG_BASE_M_LI} },
 404
 405   /* Direct load signed data into register */
 406
 407   {"dld.b",     OP_REG(0x340) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 408   {"dld.h",     OP_REG(0x342) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 409   {"dld",       OP_REG(0x344) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 410   {"dld.d",     OP_REG(0x346) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 411
 412   {"dld.b",     OP_LI(0x341) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 413   {"dld.h",     OP_LI(0x343) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 414   {"dld",       OP_LI(0x345) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 415   {"dld.d",     OP_LI(0x347) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 416
 417   /* Direct load unsigned data into register */
 418
 419   {"dld.ub",    OP_REG(0x350) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 420   {"dld.uh",    OP_REG(0x352) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 421
 422   {"dld.ub",    OP_LI(0x351) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 423   {"dld.uh",    OP_LI(0x353) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 424
 425   /* Direct store data into memory */
 426
 427   {"dst.b",     OP_REG(0x360) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 428   {"dst.h",     OP_REG(0x362) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 429   {"dst",       OP_REG(0x364) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 430   {"dst.d",     OP_REG(0x366) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 431
 432   {"dst.b",     OP_LI(0x361) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 433   {"dst.h",     OP_LI(0x363) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 434   {"dst",       OP_LI(0x365) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 435   {"dst.d",     OP_LI(0x367) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 436
 437   /* Emulation stop */
 438
 439   {"estop",     OP_LI(0x3FC),   MASK_LI,        0,              {0}     },
 440
 441   /* Emulation trap */
 442
 443   {"etrap",     OP_SI(0x1) | E(1),      MASK_SI | E(1),         0,      {SUI}   },
 444   {"etrap",     OP_REG(0x302) | E(1),   MASK_REG | E(1),        0,      {REG_0} },
 445   {"etrap",     OP_LI(0x303) | E(1),    MASK_LI | E(1),         0,      {LUI}   },
 446
 447   /* Floating-point addition */
 448
 449   {"fadd.sss",  OP_REG(0x3E0) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 450   {"fadd.ssd",  OP_REG(0x3E0) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 451   {"fadd.sdd",  OP_REG(0x3E0) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 452   {"fadd.dsd",  OP_REG(0x3E0) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 453   {"fadd.ddd",  OP_REG(0x3E0) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 454
 455   {"fadd.sss",  OP_LI(0x3E1) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 456   {"fadd.ssd",  OP_LI(0x3E1) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 457   {"fadd.sdd",  OP_LI(0x3E1) | PD(1) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 458
 459   /* Floating point compare */
 460
 461   {"fcmp.ss",   OP_REG(0x3EA) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 462   {"fcmp.sd",   OP_REG(0x3EA) | PD(0) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 463   {"fcmp.ds",   OP_REG(0x3EA) | PD(0) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 464   {"fcmp.dd",   OP_REG(0x3EA) | PD(0) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 465
 466   {"fcmp.ss",   OP_LI(0x3EB) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3),  0,     {SPFI, REG_22, REG_DEST}       },
 467   {"fcmp.sd",   OP_LI(0x3EB) | PD(0) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3),  0,     {SPFI, REG_22, REG_DEST}       },
 468
 469   /* Floating point divide */
 470
 471   {"fdiv.sss",  OP_REG(0x3E6) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 472   {"fdiv.ssd",  OP_REG(0x3E6) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 473   {"fdiv.sdd",  OP_REG(0x3E6) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 474   {"fdiv.dsd",  OP_REG(0x3E6) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 475   {"fdiv.ddd",  OP_REG(0x3E6) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 476
 477   {"fdiv.sss",  OP_LI(0x3E7) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 478   {"fdiv.ssd",  OP_LI(0x3E7) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 479   {"fdiv.sdd",  OP_LI(0x3E7) | PD(1) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 480
 481   /* Floating point multiply */
 482
 483   {"fmpy.sss",  OP_REG(0x3E4) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 484   {"fmpy.ssd",  OP_REG(0x3E4) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 485   {"fmpy.sdd",  OP_REG(0x3E4) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 486   {"fmpy.dsd",  OP_REG(0x3E4) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 487   {"fmpy.ddd",  OP_REG(0x3E4) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 488   {"fmpy.iii",  OP_REG(0x3E4) | PD(2) | P2(2) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 489   {"fmpy.uuu",  OP_REG(0x3E4) | PD(3) | P2(3) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 490
 491   {"fmpy.sss",  OP_LI(0x3E5) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 492   {"fmpy.ssd",  OP_LI(0x3E5) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 493   {"fmpy.sdd",  OP_LI(0x3E5) | PD(1) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 494   {"fmpy.iii",  OP_LI(0x3E5) | PD(2) | P2(2) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_22, REG_DEST}        },
 495   {"fmpy.uuu",  OP_LI(0x3E5) | PD(3) | P2(3) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LUI, REG_22, REG_DEST}        },
 496
 497   /* Convert/Round to Minus Infinity */
 498
 499   {"frndm.ss",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 500   {"frndm.sd",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 501   {"frndm.si",  OP_REG(0x3E8) | PD(2) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 502   {"frndm.su",  OP_REG(0x3E8) | PD(3) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 503   {"frndm.ds",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 504   {"frndm.dd",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 505   {"frndm.di",  OP_REG(0x3E8) | PD(2) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 506   {"frndm.du",  OP_REG(0x3E8) | PD(3) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 507   {"frndm.is",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 508   {"frndm.id",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 509   {"frndm.us",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 510   {"frndm.ud",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 511
 512   {"frndm.ss",  OP_LI(0x3E9) | PD(0) | P2(3) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 513   {"frndm.sd",  OP_LI(0x3E9) | PD(1) | P2(3) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 514   {"frndm.si",  OP_LI(0x3E9) | PD(2) | P2(3) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 515   {"frndm.su",  OP_LI(0x3E9) | PD(3) | P2(3) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 516   {"frndm.is",  OP_LI(0x3E9) | PD(0) | P2(3) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 517   {"frndm.id",  OP_LI(0x3E9) | PD(1) | P2(3) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 518   {"frndm.us",  OP_LI(0x3E9) | PD(0) | P2(3) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 519   {"frndm.ud",  OP_LI(0x3E9) | PD(1) | P2(3) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 520
 521   /* Convert/Round to Nearest */
 522
 523   {"frndn.ss",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 524   {"frndn.sd",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 525   {"frndn.si",  OP_REG(0x3E8) | PD(2) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 526   {"frndn.su",  OP_REG(0x3E8) | PD(3) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 527   {"frndn.ds",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 528   {"frndn.dd",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 529   {"frndn.di",  OP_REG(0x3E8) | PD(2) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 530   {"frndn.du",  OP_REG(0x3E8) | PD(3) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 531   {"frndn.is",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 532   {"frndn.id",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 533   {"frndn.us",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 534   {"frndn.ud",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 535
 536   {"frndn.ss",  OP_LI(0x3E9) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 537   {"frndn.sd",  OP_LI(0x3E9) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 538   {"frndn.si",  OP_LI(0x3E9) | PD(2) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 539   {"frndn.su",  OP_LI(0x3E9) | PD(3) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 540   {"frndn.is",  OP_LI(0x3E9) | PD(0) | P2(0) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 541   {"frndn.id",  OP_LI(0x3E9) | PD(1) | P2(0) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 542   {"frndn.us",  OP_LI(0x3E9) | PD(0) | P2(0) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 543   {"frndn.ud",  OP_LI(0x3E9) | PD(1) | P2(0) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 544
 545   /* Convert/Round to Positive Infinity */
 546
 547   {"frndp.ss",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 548   {"frndp.sd",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 549   {"frndp.si",  OP_REG(0x3E8) | PD(2) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 550   {"frndp.su",  OP_REG(0x3E8) | PD(3) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 551   {"frndp.ds",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 552   {"frndp.dd",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 553   {"frndp.di",  OP_REG(0x3E8) | PD(2) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 554   {"frndp.du",  OP_REG(0x3E8) | PD(3) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 555   {"frndp.is",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 556   {"frndp.id",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 557   {"frndp.us",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 558   {"frndp.ud",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 559
 560   {"frndp.ss",  OP_LI(0x3E9) | PD(0) | P2(2) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 561   {"frndp.sd",  OP_LI(0x3E9) | PD(1) | P2(2) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 562   {"frndp.si",  OP_LI(0x3E9) | PD(2) | P2(2) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 563   {"frndp.su",  OP_LI(0x3E9) | PD(3) | P2(2) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 564   {"frndp.is",  OP_LI(0x3E9) | PD(0) | P2(2) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 565   {"frndp.id",  OP_LI(0x3E9) | PD(1) | P2(2) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 566   {"frndp.us",  OP_LI(0x3E9) | PD(0) | P2(2) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 567   {"frndp.ud",  OP_LI(0x3E9) | PD(1) | P2(2) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 568
 569   /* Convert/Round to Zero */
 570
 571   {"frndz.ss",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 572   {"frndz.sd",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 573   {"frndz.si",  OP_REG(0x3E8) | PD(2) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 574   {"frndz.su",  OP_REG(0x3E8) | PD(3) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 575   {"frndz.ds",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 576   {"frndz.dd",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 577   {"frndz.di",  OP_REG(0x3E8) | PD(2) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 578   {"frndz.du",  OP_REG(0x3E8) | PD(3) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 579   {"frndz.is",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 580   {"frndz.id",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 581   {"frndz.us",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 582   {"frndz.ud",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 583
 584   {"frndz.ss",  OP_LI(0x3E9) | PD(0) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 585   {"frndz.sd",  OP_LI(0x3E9) | PD(1) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 586   {"frndz.si",  OP_LI(0x3E9) | PD(2) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 587   {"frndz.su",  OP_LI(0x3E9) | PD(3) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 588   {"frndz.is",  OP_LI(0x3E9) | PD(0) | P2(1) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 589   {"frndz.id",  OP_LI(0x3E9) | PD(1) | P2(1) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 590   {"frndz.us",  OP_LI(0x3E9) | PD(0) | P2(1) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 591   {"frndz.ud",  OP_LI(0x3E9) | PD(1) | P2(1) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 592
 593   /* Floating point square root */
 594
 595   {"fsqrt.ss",  OP_REG(0x3EE) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 596   {"fsqrt.sd",  OP_REG(0x3EE) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 597   {"fsqrt.dd",  OP_REG(0x3EE) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 598
 599   {"fsqrt.ss",  OP_LI(0x3EF) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 600   {"fsqrt.sd",  OP_LI(0x3EF) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 601
 602   /* Floating point subtraction */
 603
 604   { "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 605   { "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 606   { "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 607   { "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 608   { "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 609
 610   { "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 611   { "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 612   { "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 613
 614   /* Illegal instructions */
 615
 616   {"illop0",    OP_SI(0x0),     MASK_SI,        0,      0},
 617   {"illopF",    0x1FF << 13,    0x1FF << 13,    0,      0},
 618
 619   /* Jump and save return */
 620
 621   {"jsr",       OP_SI(0x44),    MASK_SI,        0,      {OFF_SS_BR, REG_BASE, REG_DEST} },
 622   {"jsr.a",     OP_SI(0x45),    MASK_SI,        0,      {OFF_SS_BR, REG_BASE, REG_DEST} },
 623
 624   {"jsr",       OP_REG(0x388),  MASK_REG,       0,      {REG_0, REG_BASE, REG_DEST}     },
 625   {"jsr.a",     OP_REG(0x38A),  MASK_REG,       0,      {REG_0, REG_BASE, REG_DEST}     },
 626
 627   {"jsr",       OP_LI(0x389),   MASK_LI,        0,      {OFF_SL_BR, REG_BASE, REG_DEST} },
 628   {"jsr.a",     OP_LI(0x38B),   MASK_LI,        0,      {OFF_SL_BR, REG_BASE, REG_DEST} },
 629
 630   /* Load Signed Data Into Register */
 631
 632   {"ld.b",      OP_SI(0x20),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 633   {"ld.h",      OP_SI(0x21),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 634   {"ld",        OP_SI(0x22),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 635   {"ld.d",      OP_SI(0x23),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 636
 637   {"ld.b",      OP_REG(0x340) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 638   {"ld.h",      OP_REG(0x342) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 639   {"ld",        OP_REG(0x344) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 640   {"ld.d",      OP_REG(0x346) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 641
 642   {"ld.b",      OP_LI(0x341) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 643   {"ld.h",      OP_LI(0x343) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 644   {"ld",        OP_LI(0x345) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 645   {"ld.d",      OP_LI(0x347) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 646
 647   /* Load Unsigned Data Into Register */
 648
 649   {"ld.ub",     OP_SI(0x28),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 650   {"ld.uh",     OP_SI(0x29),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 651
 652   {"ld.ub",     OP_REG(0x350) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 653   {"ld.uh",     OP_REG(0x352) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 654
 655   {"ld.ub",     OP_LI(0x351) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 656   {"ld.uh",     OP_LI(0x353) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 657
 658   /* Leftmost one */
 659
 660   {"lmo",       OP_LI(0x3F0),   MASK_LI,        0,      {REG_22, REG_DEST}      },
 661
 662   /* Bitwise logical OR */
 663
 664   {"or.ff",     OP_SI(0x1E),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 665   {"or.ft",     OP_SI(0x1D),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 666   {"or.tf",     OP_SI(0x1B),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 667   {"or.tt",     OP_SI(0x17),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 668
 669   {"or.ff",     OP_REG(0x33C),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 670   {"or.ft",     OP_REG(0x33A),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 671   {"or.tf",     OP_REG(0x336),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 672   {"or.tt",     OP_REG(0x32E),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 673
 674   {"or.ff",     OP_LI(0x33D),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 675   {"or.ft",     OP_LI(0x33B),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 676   {"or.tf",     OP_LI(0x337),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 677   {"or.tt",     OP_LI(0x32F),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 678
 679   /* Read Control Register */
 680
 681   {"rdcr",      OP_SI(0x4),     MASK_SI | (0x1F << 22),         0,      {CR_SI, REG_DEST}       },
 682   {"rdcr",      OP_REG(0x308),  MASK_REG | (0x1F << 22),        0,      {REG_0, REG_DEST}       },
 683   {"rdcr",      OP_LI(0x309),   MASK_LI | (0x1F << 22),         0,      {CR_LI, REG_DEST}       },
 684
 685   /* Rightmost one */
 686
 687   {"rmo",       OP_LI(0x3F2),   MASK_LI,        0,              {REG_22, REG_DEST}      },
 688
 689   /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions.
 690      They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */
 691
 692   {"rotl",      OP_SI(0x8) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 693   {"sl.dz",     OP_SI(0x8) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 694   {"sl.dm",     OP_SI(0x9) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 695   {"sl.ds",     OP_SI(0xA) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 696   {"sl.ez",     OP_SI(0xB) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 697   {"sl.em",     OP_SI(0xC) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 698   {"sl.es",     OP_SI(0xD) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 699   {"shl",       OP_SI(0xE) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 700   {"sl.iz",     OP_SI(0xE) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 701   {"ins",       OP_SI(0xF) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 702   {"sl.im",     OP_SI(0xF) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 703
 704   {"rotl",      OP_REG(0x310) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 705   {"sl.dz",     OP_REG(0x310) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 706   {"sl.dm",     OP_REG(0x312) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 707   {"sl.ds",     OP_REG(0x314) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 708   {"sl.ez",     OP_REG(0x316) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 709   {"sl.em",     OP_REG(0x318) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 710   {"sl.es",     OP_REG(0x31A) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 711   {"shl",       OP_REG(0x31C) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 712   {"sl.iz",     OP_REG(0x31C) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 713   {"ins",       OP_REG(0x31E) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 714   {"sl.im",     OP_REG(0x31E) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 715
 716   /* Shift Register Left With Inverted Endmask */
 717
 718   {"sli.dz",    OP_SI(0x8) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 719   {"sli.dm",    OP_SI(0x9) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 720   {"sli.ds",    OP_SI(0xA) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 721   {"sli.ez",    OP_SI(0xB) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 722   {"sli.em",    OP_SI(0xC) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 723   {"sli.es",    OP_SI(0xD) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 724   {"sli.iz",    OP_SI(0xE) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 725   {"sli.im",    OP_SI(0xF) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 726
 727   {"sli.dz",    OP_REG(0x310) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 728   {"sli.dm",    OP_REG(0x312) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 729   {"sli.ds",    OP_REG(0x314) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 730   {"sli.ez",    OP_REG(0x316) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 731   {"sli.em",    OP_REG(0x318) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 732   {"sli.es",    OP_REG(0x31A) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 733   {"sli.iz",    OP_REG(0x31C) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 734   {"sli.im",    OP_REG(0x31E) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 735
 736   /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions.
 737      They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */
 738
 739   {"rotr",      OP_SI(0x8) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 740   {"extu",      OP_SI(0x8) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 741   {"sr.dz",     OP_SI(0x8) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 742   {"sr.dm",     OP_SI(0x9) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 743   {"exts",      OP_SI(0xA) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 744   {"sr.ds",     OP_SI(0xA) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 745   {"srl",       OP_SI(0xB) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 746   {"sr.ez",     OP_SI(0xB) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 747   {"sr.em",     OP_SI(0xC) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 748   {"sra",       OP_SI(0xD) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 749   {"sr.es",     OP_SI(0xD) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 750   {"sr.iz",     OP_SI(0xE) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 751   {"sr.im",     OP_SI(0xF) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 752
 753   {"rotr",      OP_REG(0x310) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 754   {"extu",      OP_REG(0x310) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 755   {"sr.dz",     OP_REG(0x310) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 756   {"sr.dm",     OP_REG(0x312) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 757   {"exts",      OP_REG(0x314) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 758   {"sr.ds",     OP_REG(0x314) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 759   {"srl",       OP_REG(0x316) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 760   {"sr.ez",     OP_REG(0x316) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 761   {"sr.em",     OP_REG(0x318) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 762   {"sra",       OP_REG(0x31A) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 763   {"sr.es",     OP_REG(0x31A) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 764   {"sr.iz",     OP_REG(0x31C) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 765   {"sr.im",     OP_REG(0x31E) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 766
 767   /* Shift Register Right With Inverted Endmask */
 768
 769   {"sri.dz",    OP_SI(0x8) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 770   {"sri.dm",    OP_SI(0x9) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 771   {"sri.ds",    OP_SI(0xA) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 772   {"sri.ez",    OP_SI(0xB) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 773   {"sri.em",    OP_SI(0xC) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 774   {"sri.es",    OP_SI(0xD) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 775   {"sri.iz",    OP_SI(0xE) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 776   {"sri.im",    OP_SI(0xF) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 777
 778   {"sri.dz",    OP_REG(0x310) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 779   {"sri.dm",    OP_REG(0x312) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 780   {"sri.ds",    OP_REG(0x314) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 781   {"sri.ez",    OP_REG(0x316) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 782   {"sri.em",    OP_REG(0x318) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 783   {"sri.es",    OP_REG(0x31A) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 784   {"sri.iz",    OP_REG(0x31C) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 785   {"sri.im",    OP_REG(0x31E) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 786
 787   /* Store Data into Memory */
 788
 789   {"st.b",      OP_SI(0x30),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}},
 790   {"st.h",      OP_SI(0x31),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}},
 791   {"st",        OP_SI(0x32),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}},
 792   {"st.d",      OP_SI(0x33),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}},
 793
 794   {"st.b",      OP_REG(0x360) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 795   {"st.h",      OP_REG(0x362) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 796   {"st",        OP_REG(0x364) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 797   {"st.d",      OP_REG(0x366) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 798
 799   {"st.b",      OP_LI(0x361) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 800   {"st.h",      OP_LI(0x363) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 801   {"st",        OP_LI(0x365) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 802   {"st.d",      OP_LI(0x367) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 803
 804   /* Signed Integer Subtract */
 805
 806   {"sub",       OP_SI(0x5A),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
 807   {"sub",       OP_REG(0x3B4),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 808   {"sub",       OP_LI(0x3B5),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
 809
 810   /* Unsigned Integer Subtract */
 811
 812   {"subu",      OP_SI(0x5B),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
 813   {"subu",      OP_REG(0x3B6),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 814   {"subu",      OP_LI(0x3B7),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
 815
 816   /* Write Control Register
 817      Is a special form of the "swcr" instruction so comes before it in the table. */
 818
 819   {"wrcr",      OP_SI(0x5),     MASK_SI | (0x1F << 27),         0,      {CR_SI, REG_22} },
 820   {"wrcr",      OP_REG(0x30A),  MASK_REG | (0x1F << 27),        0,      {REG_0, REG_22} },
 821   {"wrcr",      OP_LI(0x30B),   MASK_LI | (0x1F << 27),         0,      {CR_LI, REG_22} },
 822
 823   /* Swap Control Register */
 824
 825   {"swcr",      OP_SI(0x5),     MASK_SI,        0,      {CR_SI, REG_22, REG_DEST}       },
 826   {"swcr",      OP_REG(0x30A),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 827   {"swcr",      OP_LI(0x30B),   MASK_LI,        0,      {CR_LI, REG_22, REG_DEST}       },
 828
 829   /* Trap */
 830
 831   {"trap",      OP_SI(0x1) | E(0),      MASK_SI | E(1),         0,      {SUI}   },
 832   {"trap",      OP_REG(0x302) | E(0),   MASK_REG | E(1),        0,      {REG_0} },
 833   {"trap",      OP_LI(0x303) | E(0),    MASK_LI | E(1),         0,      {LUI}   },
 834
 835   /* Vector Floating-Point Add */
 836
 837   {"vadd.ss",   OP_REG(0x3C0) | P2(0) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
 838   {"vadd.sd",   OP_REG(0x3C0) | P2(1) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
 839   {"vadd.dd",   OP_REG(0x3C0) | P2(1) | P1(1),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
 840
 841   {"vadd.ss",   OP_LI(0x3C1) | P2(0) | P1(0),   MASK_LI | V_a1(1) | P2(1) | P1(1),      TIC80_VECTOR,   {SPFI, REG_22, REG_22}  },
 842   {"vadd.sd",   OP_LI(0x3C1) | P2(1) | P1(0),   MASK_LI | V_a1(1) | P2(1) | P1(1),      TIC80_VECTOR,   {SPFI, REG_22, REG_22}  },
 843
 844   /* Vector Floating-Point Multiply and Add to Accumulator
 845    FIXME! This is not yet implemented.  From the documentation there appears to be no way to
 846    tell the difference between the opcodes for instructions that have register destinations
 847    and instructions that have accumulator destinations.  Further investigation is necessary.
 848    Since this isn't critical to getting a TIC80 toolchain up and running, it is defered
 849    until later. */
 850
 851   /* Vector Floating-Point Multiply
 852    Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */
 853
 854   {"vmpy.ss",   OP_REG(0x3C4) | P2(0) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
 855   {"vmpy.sd",   OP_REG(0x3C4) | P2(1) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
 856   {"vmpy.dd",   OP_REG(0x3C4) | P2(1) | P1(1),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
 857
 858   {"vmpy.ss",   OP_LI(0x3C5) | P2(0) | P1(0),   MASK_LI | V_a1(1) | P2(1) | P1(1),      TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} },
 859   {"vmpy.sd",   OP_LI(0x3C5) | P2(1) | P1(0),   MASK_LI | V_a1(1) | P2(1) | P1(1),      TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} },
 860
 861   /* Vector Floating-Point Multiply and Subtract from Accumulator
 862      FIXME: See note above for vmac instruction */
 863
 864   /* Vector Floating-Point Subtract Accumulator From Source
 865      FIXME: See note above for vmac instruction */
 866
 867   /* Vector Round With Floating-Point Input
 868      FIXME: See note above for vmac instruction */
 869
 870   /* Vector Round with Integer Input */
 871
 872   {"vrnd.is",   OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {REG_0, REG_22}},
 873   {"vrnd.us",   OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {REG_0, REG_22}},
 874   {"vrnd.id",   OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {REG_0, REG_22}},
 875   {"vrnd.ud",   OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {REG_0, REG_22}},
 876
 877   {"vrnd.is",   OP_LI (0x3CB) | P2(0) | P1(0),  MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {LSI, REG_22}},
 878   {"vrnd.us",   OP_LI (0x3CB) | P2(0) | P1(1),  MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {LUI, REG_22}},
 879   {"vrnd.id",   OP_LI (0x3CB) | P2(1) | P1(0),  MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {LSI, REG_22}},
 880   {"vrnd.ud",   OP_LI (0x3CB) | P2(1) | P1(1),  MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {LUI, REG_22}},
 881
 882   /* Vector Floating-Point Subtract */
 883
 884   {"vsub.ss",   OP_REG(0x3C2) | P2(0) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
 885   {"vsub.sd",   OP_REG(0x3C2) | P2(1) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
 886   {"vsub.dd",   OP_REG(0x3C2) | P2(1) | P1(1),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
 887
 888   {"vsub.ss",   OP_LI(0x3C3) | P2(0) | P1(0),   MASK_LI | V_a1(1) | P2(1) | P1(1),      TIC80_VECTOR,   {SPFI, REG_22, REG_22}  },
 889   {"vsub.sd",   OP_LI(0x3C3) | P2(1) | P1(0),   MASK_LI | V_a1(1) | P2(1) | P1(1),      TIC80_VECTOR,   {SPFI, REG_22, REG_22}  },
 890
 891   /* Vector Load Data Into Register - Note that the vector load/store instructions come after the other
 892    vector instructions so that the disassembler will always print the load/store instruction second for
 893    vector instructions that have two instructions in the same opcode. */
 894
 895   {"vld0.s",    OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
 896   {"vld1.s",    OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
 897   {"vld0.d",    OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
 898   {"vld1.d",    OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
 899
 900   /* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other
 901    vector instructions so that the disassembler will always print the load/store instruction second for
 902    vector instructions that have two instructions in the same opcode. */
 903
 904   {"vst.s",     OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
 905   {"vst.d",     OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
 906
 907   {"xnor",      OP_SI(0x19),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST} },
 908   {"xnor",      OP_REG(0x332),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST} },
 909   {"xnor",      OP_LI(0x333),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST} },
 910
 911   {"xor",       OP_SI(0x16),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST} },
 912   {"xor",       OP_REG(0x32C),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST} },
 913   {"xor",       OP_LI(0x32D),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST} },
 914
 915 };
 916
 917 const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
 918