opcodes/tic80-opc.c

   1 /* Opcode table for TI TMS320C80 (MVP).
   2    Copyright 1996 Free Software Foundation, Inc.
   3
   4 This file is part of GDB, GAS, and the GNU binutils.
   5
   6 GDB, GAS, and the GNU binutils are free software; you can redistribute
   7 them and/or modify them under the terms of the GNU General Public
   8 License as published by the Free Software Foundation; either version
   9 1, or (at your option) any later version.
  10
  11 GDB, GAS, and the GNU binutils are distributed in the hope that they
  12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  14 the GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this file; see the file COPYING.  If not, write to the Free
  18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include <stdio.h>
  21 #include "ansidecl.h"
  22 #include "opcode/tic80.h"
  23
  24 /* This file holds the TMS320C80 (MVP) opcode table.  The table is
  25    strictly constant data, so the compiler should be able to put it in
  26    the .text section.
  27
  28    This file also holds the operand table.  All knowledge about
  29    inserting operands into instructions and vice-versa is kept in this
  30    file.  */
  31
  32 \f
  33 /* The operands table.  The fields are:
  34
  35         bits, shift, insertion function, extraction function, flags
  36  */
  37
  38 const struct tic80_operand tic80_operands[] =
  39 {
  40
  41   /* The zero index is used to indicate the end of the list of operands.  */
  42
  43 #define UNUSED (0)
  44   { 0, 0, 0, 0, 0 },
  45
  46   /* Short signed immediate value in bits 14-0. */
  47
  48 #define SSI (UNUSED + 1)
  49   { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  50
  51   /* Short unsigned immediate value in bits 14-0 */
  52
  53 #define SUI (SSI + 1)
  54   { 15, 0, NULL, NULL, 0 },
  55
  56   /* Short unsigned bitfield in bits 14-0.  We distinguish this
  57      from a regular unsigned immediate value only for the convenience
  58      of the disassembler and the user. */
  59
  60 #define SUBF (SUI + 1)
  61   { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  62
  63   /* Long signed immediate in following 32 bit word */
  64
  65 #define LSI (SUBF + 1)
  66   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  67
  68   /* Long unsigned immediate in following 32 bit word */
  69
  70 #define LUI (LSI + 1)
  71   { 32, 0, NULL, NULL, 0 },
  72
  73   /* Long unsigned bitfield in following 32 bit word.  We distinguish
  74      this from a regular unsigned immediate value only for the
  75      convenience of the disassembler and the user. */
  76
  77 #define LUBF (LUI + 1)
  78   { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  79
  80   /* Register in bits 4-0 */
  81
  82 #define REG0 (LUBF + 1)
  83   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
  84
  85   /* Register in bits 26-22 */
  86
  87 #define REG22 (REG0 + 1)
  88   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
  89
  90   /* Register in bits 31-27 */
  91
  92 #define REG27 (REG22 + 1)
  93   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
  94
  95   /* Short signed offset in bits 14-0 */
  96
  97 #define SSOFF (REG27 + 1)
  98   { 15, 0, NULL, NULL, TIC80_OPERAND_RELATIVE | TIC80_OPERAND_SIGNED },
  99
 100   /* Long signed offset in following 32 bit word */
 101
 102 #define LSOFF (SSOFF + 1)
 103   {32, 0, NULL, NULL, TIC80_OPERAND_RELATIVE | TIC80_OPERAND_SIGNED },
 104
 105   /* BITNUM in bits 31-27 */
 106
 107 #define BITNUM (LSOFF + 1)
 108   { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
 109
 110   /* Condition code in bits 31-27 */
 111
 112 #define CC (BITNUM + 1)
 113   { 5, 27, NULL, NULL, TIC80_OPERAND_CC },
 114
 115   /* Control register number in bits 14-0 */
 116
 117 #define SICR (CC + 1)
 118   { 15, 0, NULL, NULL, TIC80_OPERAND_CR },
 119
 120   /* Control register number in next 32 bit word */
 121
 122 #define LICR (SICR + 1)
 123   { 32, 0, NULL, NULL, TIC80_OPERAND_CR },
 124
 125   /* Register in bits 26-22, enclosed in parens and with optional
 126      ":m" flag in bit 17 */
 127
 128 #define REGM_SI (LICR + 1)
 129   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
 130
 131   /* Register in bits 26-22, enclosed in parens and with optional
 132      ":m" flag in bit 15 */
 133
 134 #define REGM_LI (REGM_SI + 1)
 135   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
 136
 137 };
 138
 139 const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
 140
 141 \f
 142 /* Macros used to generate entries for the opcodes table. */
 143
 144 #define FIXME 0
 145
 146 /* Short-Immediate Format Instructions - basic opcode */
 147 #define OP_SI(x)        (((x) & 0x7F) << 15)
 148 #define MASK_SI         OP_SI(0x7F)
 149
 150 /* Long-Immediate Format Instructions - basic opcode */
 151 #define OP_LI(x)        (((x) & 0x3FF) << 12)
 152 #define MASK_LI         OP_LI(0x3FF)
 153
 154 /* Register Format Instructions - basic opcode */
 155 #define OP_REG(x)       OP_LI(x)        /* For readability */
 156 #define MASK_REG        MASK_LI         /* For readability */
 157
 158 /* The 'F' bit at bit 27 */
 159 #define F(x)            ((x) << 27)
 160
 161 /* The 'M' bit at bit 15 in register and long immediate opcodes */
 162 #define M_REG(x)        ((x) << 15)
 163 #define M_LI(x)         ((x) << 15)
 164
 165 /* The 'M' bit at bit 17 in short immediate opcodes */
 166 #define M_SI(x)         ((x) << 17)
 167
 168 /* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
 169 #define SZ_REG(x)       ((x) << 13)
 170 #define SZ_LI(x)        ((x) << 13)
 171
 172 /* The 'SZ' field at bits 16-15 in short immediate opcodes */
 173 #define SZ_SI(x)        ((x) << 15)
 174
 175 /* The 'D' (direct external memory access) bit at bit 10 in long immediate
 176    and register opcodes. */
 177 #define D(x)            ((x) << 10)
 178
 179 /* The 'S' (scale offset by data size) bit at bit 11 in long immediate
 180    and register opcodes. */
 181 #define S(x)            ((x) << 11)
 182
 183 \f
 184 const struct tic80_opcode tic80_opcodes[] = {
 185
 186   /* The "nop" instruction is really "rdcr 0,r0".  We put it first so that this
 187      specific bit pattern will get disassembled as a nop rather than an rdcr. The
 188      mask of all ones ensures that this will happen. */
 189
 190   {"nop",       OP_SI(0x4),     ~0,             0,              {0}                     },
 191
 192   /* The "br" instruction is really "bbz target,r0,31".  We put it first so that
 193      this specific bit pattern will get disassembled as a br rather than bbz. */
 194
 195   {"br",        OP_SI(0x48),    0xFFFF8000,     0,              {SSOFF}                 },
 196   {"br",        OP_LI(0x391),   0xFFFFF000,     0,              {LSOFF}                 },
 197   {"br",        OP_REG(0x390),  0xFFFFF000,     0,              {REG0}                  },
 198
 199   {"br.a",      OP_SI(0x49),    0xFFFF8000,     0,              {SSOFF}                 },
 200   {"br.a",      OP_LI(0x393),   0xFFFFF000,     0,              {LSOFF}                 },
 201   {"br.a",      OP_REG(0x392),  0xFFFFF000,     0,              {REG0}                  },
 202
 203   /* Signed integer ADD */
 204
 205   {"add",       OP_SI(0x58),    MASK_SI,        FMT_SI,         {SSI, REG22, REG27}     },
 206   {"add",       OP_LI(0x3B1),   MASK_LI,        FMT_LI,         {LSI, REG22, REG27}     },
 207   {"add",       OP_REG(0x3B0),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 208
 209   /* Unsigned integer ADD */
 210
 211   {"addu",      OP_SI(0x59),    MASK_SI,        FMT_SI,         {SSI, REG22, REG27}     },
 212   {"addu",      OP_LI(0x3B3),   MASK_LI,        FMT_LI,         {LSI, REG22, REG27}     },
 213   {"addu",      OP_REG(0x3B2),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 214
 215   /* Bitwise AND */
 216
 217   {"and",       OP_SI(0x11),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 218   {"and",       OP_LI(0x323),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 219   {"and",       OP_REG(0x322),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 220
 221   {"and.tt",    OP_SI(0x11),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 222   {"and.tt",    OP_LI(0x323),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 223   {"and.tt",    OP_REG(0x322),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 224
 225   /* Bitwise AND with ones complement of both sources */
 226
 227   {"and.ff",    OP_SI(0x18),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 228   {"and.ff",    OP_LI(0x331),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 229   {"and.ff",    OP_REG(0x330),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 230
 231   /* Bitwise AND with ones complement of source 1 */
 232
 233   {"and.ft",    OP_SI(0x14),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 234   {"and.ft",    OP_LI(0x329),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 235   {"and.ft",    OP_REG(0x328),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 236
 237   /* Bitwise AND with ones complement of source 2 */
 238
 239   {"and.tf",    OP_SI(0x12),    MASK_SI,        FMT_SI,         {SUBF, REG22, REG27}    },
 240   {"and.tf",    OP_LI(0x325),   MASK_LI,        FMT_LI,         {LUBF, REG22, REG27}    },
 241   {"and.tf",    OP_REG(0x324),  MASK_REG,       FMT_REG,        {REG0, REG22, REG27}    },
 242
 243   /* Branch Bit One - nonannulled */
 244
 245   {"bbo",       OP_SI(0x4A),    MASK_SI,        FMT_SI,         {SSOFF, REG22, BITNUM}  },
 246   {"bbo",       OP_LI(0x395),   MASK_LI,        FMT_LI,         {LSOFF, REG22, BITNUM}  },
 247   {"bbo",       OP_REG(0x394),  MASK_REG,       FMT_REG,        {REG0, REG22, BITNUM}   },
 248
 249   /* Branch Bit One - annulled */
 250
 251   {"bbo.a",     OP_SI(0x4B),    MASK_SI,        FMT_SI,         {SSOFF, REG22, BITNUM}  },
 252   {"bbo.a",     OP_LI(0x397),   MASK_LI,        FMT_LI,         {LSOFF, REG22, BITNUM}  },
 253   {"bbo.a",     OP_REG(0x396),  MASK_REG,       FMT_REG,        {REG0, REG22, BITNUM}   },
 254
 255   /* Branch Bit Zero - nonannulled */
 256
 257   {"bbz",       OP_SI(0x48),    MASK_SI,        FMT_SI,         {SSOFF, REG22, BITNUM}  },
 258   {"bbz",       OP_LI(0x391),   MASK_LI,        FMT_LI,         {LSOFF, REG22, BITNUM}  },
 259   {"bbz",       OP_REG(0x390),  MASK_REG,       FMT_REG,        {REG0, REG22, BITNUM}   },
 260
 261   /* Branch Bit Zero - annulled */
 262
 263   {"bbz.a",     OP_SI(0x49),    MASK_SI,        FMT_SI,         {SSOFF, REG22, BITNUM}  },
 264   {"bbz.a",     OP_LI(0x393),   MASK_LI,        FMT_LI,         {LSOFF, REG22, BITNUM}  },
 265   {"bbz.a",     OP_REG(0x392),  MASK_REG,       FMT_REG,        {REG0, REG22, BITNUM}   },
 266
 267   /* Branch Conditional - nonannulled */
 268
 269   {"bcnd",      OP_SI(0x4C),    MASK_SI,        FMT_SI,         {SSOFF, REG22, CC}      },
 270   {"bcnd",      OP_LI(0x399),   MASK_LI,        FMT_LI,         {LSOFF, REG22, CC}      },
 271   {"bcnd",      OP_REG(0x398),  MASK_REG,       FMT_REG,        {REG0, REG22, CC}       },
 272
 273   /* Branch Conditional - annulled */
 274
 275   {"bcnd.a",    OP_SI(0x4D),    MASK_SI,        FMT_SI,         {SSOFF, REG22, CC}      },
 276   {"bcnd.a",    OP_LI(0x39B),   MASK_LI,        FMT_LI,         {LSOFF, REG22, CC}      },
 277   {"bcnd.a",    OP_REG(0x39A),  MASK_REG,       FMT_REG,        {REG0, REG22, CC}       },
 278
 279   /* Branch Control Register */
 280
 281   {"brcr",      OP_SI(0x6),     MASK_SI,        FMT_SI,         {SICR}                  },
 282   {"brcr",      OP_LI(0x30D),   MASK_LI,        FMT_LI,         {LICR}                  },
 283   {"brcr",      OP_REG(0x30C),  MASK_REG,       FMT_REG,        {REG0}                  },
 284
 285   /* Branch and save return - nonannulled */
 286
 287   {"bsr",       OP_SI(0x40),    MASK_SI,        FMT_SI,         {SSOFF,REG27}           },
 288   {"bsr",       OP_LI(0x381),   MASK_LI,        FMT_LI,         {LSOFF,REG27}           },
 289   {"bsr",       OP_REG(0x380),  MASK_REG,       FMT_REG,        {REG0,REG27}            },
 290
 291   /* Branch and save return - annulled */
 292
 293   {"bsr.a",     OP_SI(0x41),    MASK_SI,        FMT_SI,         {SSOFF,REG27}           },
 294   {"bsr.a",     OP_LI(0x383),   MASK_LI,        FMT_LI,         {LSOFF,REG27}           },
 295   {"bsr.a",     OP_REG(0x382),  MASK_REG,       FMT_REG,        {REG0,REG27}            },
 296
 297   /* Send command */
 298
 299   {"cmnd",      OP_SI(0x2),     MASK_SI,        FMT_SI,         {SUI}                   },
 300   {"cmnd",      OP_LI(0x305),   MASK_LI,        FMT_LI,         {LUI}                   },
 301   {"cmnd",      OP_REG(0x304),  MASK_REG,       FMT_REG,        {REG0}                  },
 302
 303   /* Integer compare */
 304
 305   {"cmp",       OP_SI(0x50),    MASK_SI,        FMT_SI,         {SSI,REG22,REG27}       },
 306   {"cmp",       OP_LI(0x3A1),   MASK_LI,        FMT_LI,         {LSI,REG22,REG27}       },
 307   {"cmp",       OP_REG(0x3A0),  MASK_REG,       FMT_REG,        {REG0,REG22,REG27}      },
 308
 309   /* Flush data cache subblock - don't clear subblock preset flag */
 310
 311   {"dcachec",   OP_SI(0x38),    F(1) | (MASK_SI & ~M_SI(1)),                    FMT_SI, {SSI,REGM_SI}   },
 312   {"dcachec",   OP_LI(0x371),   F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1),      FMT_LI, {LSI,REGM_LI}   },
 313   {"dcachec",   OP_REG(0x370),  F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),    FMT_REG, {REG0,REGM_LI} },
 314
 315   /* Flush data cache subblock - clear subblock preset flag */
 316
 317   {"dcachef",   OP_SI(0x38) | F(1),     F(1) | (MASK_SI & ~M_SI(1)),                    FMT_SI, {SSI,REGM_SI}   },
 318   {"dcachef",   OP_LI(0x371) | F(1),    F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1),      FMT_LI, {LSI,REGM_LI}   },
 319   {"dcachef",   OP_REG(0x370) | F(1),   F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),    FMT_REG, {REG0,REGM_LI} },
 320
 321   /* WORK IN PROGRESS BELOW THIS POINT */
 322
 323   {"illop0",    OP_SI(0),       MASK_SI,        FMT_SI,         FIXME},
 324
 325   {"ld",        OP_LI(0x345),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 326   {"ld",        OP_REG(0x344),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 327   {"ld",        OP_SI(0x22),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 328   {"ld.b",      OP_LI(0x341),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 329   {"ld.b",      OP_REG(0x340),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 330   {"ld.b",      OP_SI(0x20),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 331   {"ld.d",      OP_LI(0x347),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 332   {"ld.d",      OP_REG(0x346),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 333   {"ld.d",      OP_SI(0x23),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 334   {"ld.h",      OP_LI(0x343),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 335   {"ld.h",      OP_REG(0x342),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 336   {"ld.h",      OP_SI(0x21),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 337   {"ld.u",      OP_LI(0x355),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 338   {"ld.u",      OP_REG(0x354),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 339   {"ld.u",      OP_SI(0x2A),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 340   {"ld.ub",     OP_LI(0x351),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 341   {"ld.ub",     OP_REG(0x350),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 342   {"ld.ub",     OP_SI(0x28),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 343   {"ld.ud",     OP_LI(0x357),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 344   {"ld.ud",     OP_REG(0x356),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 345   {"ld.ud",     OP_SI(0x2B),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 346   {"ld.uh",     OP_LI(0x353),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 347   {"ld.uh",     OP_REG(0x352),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 348   {"ld.uh",     OP_SI(0x29),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 349   {"or.ff",     OP_LI(0x33D),   MASK_LI,        FMT_LI,         FIXME},
 350   {"or.ff",     OP_REG(0x33C),  MASK_REG,       FMT_REG,        FIXME},
 351   {"or.ff",     OP_SI(0x1E),    MASK_SI,        FMT_SI,         FIXME},
 352   {"or.ft",     OP_LI(0x33B),   MASK_LI,        FMT_LI,         FIXME},
 353   {"or.ft",     OP_REG(0x33A),  MASK_REG,       FMT_REG,        FIXME},
 354   {"or.ft",     OP_SI(0x1D),    MASK_SI,        FMT_SI,         FIXME},
 355   {"or.tf",     OP_LI(0x337),   MASK_LI,        FMT_LI,         FIXME},
 356   {"or.tf",     OP_REG(0x336),  MASK_REG,       FMT_REG,        FIXME},
 357   {"or.tf",     OP_SI(0x1B),    MASK_SI,        FMT_SI,         FIXME},
 358   {"or.tt",     OP_LI(0x32F),   MASK_LI,        FMT_LI,         FIXME},
 359   {"or.tt",     OP_REG(0x32E),  MASK_REG,       FMT_REG,        FIXME},
 360   {"or.tt",     OP_SI(0x17),    MASK_SI,        FMT_SI,         FIXME},
 361   {"rdcr",      OP_LI(0x309),   MASK_LI,        FMT_LI,         FIXME},
 362   {"rdcr",      OP_REG(0x308),  MASK_REG,       FMT_REG,        FIXME},
 363   {"rdcr",      OP_SI(0x4),     MASK_SI,        FMT_SI,         FIXME},
 364   {"shift.dm",  OP_REG(0x312),  MASK_REG,       FMT_REG,        FIXME},
 365   {"shift.dm",  OP_SI(0x9),     MASK_SI,        FMT_SI,         FIXME},
 366   {"shift.ds",  OP_REG(0x314),  MASK_REG,       FMT_REG,        FIXME},
 367   {"shift.ds",  OP_SI(0xA),     MASK_SI,        FMT_SI,         FIXME},
 368   {"shift.dz",  OP_REG(0x310),  MASK_REG,       FMT_REG,        FIXME},
 369   {"shift.dz",  OP_SI(0x8),     MASK_SI,        FMT_SI,         FIXME},
 370   {"shift.em",  OP_REG(0x318),  MASK_REG,       FMT_REG,        FIXME},
 371   {"shift.em",  OP_SI(0xC),     MASK_SI,        FMT_SI,         FIXME},
 372   {"shift.es",  OP_REG(0x31A),  MASK_REG,       FMT_REG,        FIXME},
 373   {"shift.es",  OP_SI(0xD),     MASK_SI,        FMT_SI,         FIXME},
 374   {"shift.ez",  OP_REG(0x316),  MASK_REG,       FMT_REG,        FIXME},
 375   {"shift.ez",  OP_SI(0xB),     MASK_SI,        FMT_SI,         FIXME},
 376   {"shift.im",  OP_REG(0x31E),  MASK_REG,       FMT_REG,        FIXME},
 377   {"shift.im",  OP_SI(0xF),     MASK_SI,        FMT_SI,         FIXME},
 378   {"shift.iz",  OP_REG(0x31C),  MASK_REG,       FMT_REG,        FIXME},
 379   {"shift.iz",  OP_SI(0xE),     MASK_SI,        FMT_SI,         FIXME},
 380   {"st",        OP_LI(0x365),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 381   {"st",        OP_REG(0x364),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 382   {"st",        OP_SI(0x32),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 383   {"st.b",      OP_LI(0x361),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 384   {"st.b",      OP_REG(0x360),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 385   {"st.b",      OP_SI(0x30),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 386   {"st.d",      OP_LI(0x367),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 387   {"st.d",      OP_REG(0x366),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 388   {"st.d",      OP_SI(0x33),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 389   {"st.h",      OP_LI(0x363),   MASK_LI & ~M_LI(1),     FMT_LI,         FIXME},
 390   {"st.h",      OP_REG(0x362),  MASK_REG & ~M_REG(1),   FMT_REG,        FIXME},
 391   {"st.h",      OP_SI(0x31),    MASK_SI & ~M_SI(1),     FMT_SI,         FIXME},
 392   {"swcr",      OP_LI(0x30B),   MASK_LI,        FMT_LI,         FIXME},
 393   {"swcr",      OP_REG(0x30A),  MASK_REG,       FMT_REG,        FIXME},
 394   {"swcr",      OP_SI(0x5),     MASK_SI,        FMT_SI,         FIXME},
 395   {"trap",      OP_LI(0x303),   MASK_LI,        FMT_LI,         FIXME},
 396   {"trap",      OP_REG(0x302),  MASK_REG,       FMT_REG,        FIXME},
 397   {"trap",      OP_SI(0x1),     MASK_SI,        FMT_SI,         FIXME},
 398   {"xnor",      OP_LI(0x333),   MASK_LI,        FMT_LI,         FIXME},
 399   {"xnor",      OP_REG(0x332),  MASK_REG,       FMT_REG,        FIXME},
 400   {"xnor",      OP_SI(0x19),    MASK_SI,        FMT_SI,         FIXME},
 401   {"xor",       OP_LI(0x32D),   MASK_LI,        FMT_LI,         FIXME},
 402   {"xor",       OP_REG(0x32C),  MASK_REG,       FMT_REG,        FIXME},
 403   {"xor",       OP_SI(0x16),    MASK_SI,        FMT_SI,         FIXME},
 404
 405 };
 406
 407 const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
 408