opcodes/tic80-opc.c

   1 /* Opcode table for TI TMS320C80 (MVP).
   2    Copyright 1996 Free Software Foundation, Inc.
   3
   4 This file is part of GDB, GAS, and the GNU binutils.
   5
   6 GDB, GAS, and the GNU binutils are free software; you can redistribute
   7 them and/or modify them under the terms of the GNU General Public
   8 License as published by the Free Software Foundation; either version
   9 1, or (at your option) any later version.
  10
  11 GDB, GAS, and the GNU binutils are distributed in the hope that they
  12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  14 the GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this file; see the file COPYING.  If not, write to the Free
  18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include <stdio.h>
  21 #include "ansidecl.h"
  22 #include "opcode/tic80.h"
  23
  24 /* This file holds the TMS320C80 (MVP) opcode table.  The table is
  25    strictly constant data, so the compiler should be able to put it in
  26    the .text section.
  27
  28    This file also holds the operand table.  All knowledge about
  29    inserting operands into instructions and vice-versa is kept in this
  30    file.  */
  31
  32 \f
  33 /* The operands table.  The fields are:
  34
  35         bits, shift, insertion function, extraction function, flags
  36  */
  37
  38 const struct tic80_operand tic80_operands[] =
  39 {
  40
  41   /* The zero index is used to indicate the end of the list of operands.  */
  42
  43 #define UNUSED (0)
  44   { 0, 0, 0, 0, 0 },
  45
  46   /* Short signed immediate value in bits 14-0. */
  47
  48 #define SSI (UNUSED + 1)
  49   { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  50
  51   /* Short unsigned immediate value in bits 14-0 */
  52
  53 #define SUI (SSI + 1)
  54   { 15, 0, NULL, NULL, 0 },
  55
  56   /* Short unsigned bitfield in bits 14-0.  We distinguish this
  57      from a regular unsigned immediate value only for the convenience
  58      of the disassembler and the user. */
  59
  60 #define SUBF (SUI + 1)
  61   { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  62
  63   /* Long signed immediate in following 32 bit word */
  64
  65 #define LSI (SUBF + 1)
  66   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
  67
  68   /* Long unsigned immediate in following 32 bit word */
  69
  70 #define LUI (LSI + 1)
  71   { 32, 0, NULL, NULL, 0 },
  72
  73   /* Long unsigned bitfield in following 32 bit word.  We distinguish
  74      this from a regular unsigned immediate value only for the
  75      convenience of the disassembler and the user. */
  76
  77 #define LUBF (LUI + 1)
  78   { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
  79
  80   /* Single precision floating point immediate in following 32 bit
  81      word. */
  82
  83 #define SPFI (LUBF + 1)
  84   { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
  85
  86   /* Register in bits 4-0 */
  87
  88 #define REG_0 (SPFI + 1)
  89   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
  90
  91   /* Register in bits 26-22 */
  92
  93 #define REG_22 (REG_0 + 1)
  94   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
  95
  96   /* Register in bits 31-27 */
  97
  98 #define REG_DEST (REG_22 + 1)
  99   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
 100
 101   /* Short signed PC word offset in bits 14-0 */
 102
 103 #define OFF_SS_PC (REG_DEST + 1)
 104   { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
 105
 106   /* Long signed PC word offset in following 32 bit word */
 107
 108 #define OFF_SL_PC (OFF_SS_PC + 1)
 109   {32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
 110
 111   /* Short signed base relative byte offset in bits 14-0 */
 112
 113 #define OFF_SS_BR (OFF_SL_PC + 1)
 114   { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
 115
 116   /* Long signed base relative byte offset in following 32 bit word */
 117
 118 #define OFF_SL_BR (OFF_SS_BR + 1)
 119   {32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
 120
 121   /* BITNUM in bits 31-27 */
 122
 123 #define BITNUM (OFF_SL_BR + 1)
 124   { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
 125
 126   /* Condition code in bits 31-27 */
 127
 128 #define CC (BITNUM + 1)
 129   { 5, 27, NULL, NULL, TIC80_OPERAND_CC },
 130
 131   /* Control register number in bits 14-0 */
 132
 133 #define CR_SI (CC + 1)
 134   { 15, 0, NULL, NULL, TIC80_OPERAND_CR },
 135
 136   /* Control register number in next 32 bit word */
 137
 138 #define CR_LI (CR_SI + 1)
 139   { 32, 0, NULL, NULL, TIC80_OPERAND_CR },
 140
 141   /* A base register in bits 26-22, enclosed in parens */
 142
 143 #define REG_BASE (CR_LI + 1)
 144   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS },
 145
 146   /* A base register in bits 26-22, enclosed in parens, with optional ":m"
 147      flag in bit 17 (short immediate instructions only) */
 148
 149 #define REG_BASE_M_SI (REG_BASE + 1)
 150   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
 151
 152   /* A base register in bits 26-22, enclosed in parens, with optional ":m"
 153    flag in bit 15 (long immediate and register instructions only) */
 154
 155 #define REG_BASE_M_LI (REG_BASE_M_SI + 1)
 156   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
 157
 158   /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */
 159
 160 #define REG_SCALED (REG_BASE_M_LI + 1)
 161   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
 162
 163   /* Long signed immediate in following 32 bit word, with optional ":s" modifier
 164      flag in bit 11 */
 165
 166 #define LSI_SCALED (REG_SCALED + 1)
 167   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
 168
 169   /* Unsigned immediate in bits 4-0, used only for shift instructions */
 170
 171 #define ROTATE (LSI_SCALED + 1)
 172   { 5, 0, NULL, NULL, 0 },
 173
 174   /* Unsigned immediate in bits 9-5, used only for shift instructions */
 175 #define ENDMASK (ROTATE + 1)
 176   { 5, 5, NULL, NULL, 0 },
 177
 178 };
 179
 180 const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
 181
 182 \f
 183 /* Macros used to generate entries for the opcodes table. */
 184
 185 #define FIXME 0
 186
 187 /* Short-Immediate Format Instructions - basic opcode */
 188 #define OP_SI(x)        (((x) & 0x7F) << 15)
 189 #define MASK_SI         OP_SI(0x7F)
 190
 191 /* Long-Immediate Format Instructions - basic opcode */
 192 #define OP_LI(x)        (((x) & 0x3FF) << 12)
 193 #define MASK_LI         OP_LI(0x3FF)
 194
 195 /* Register Format Instructions - basic opcode */
 196 #define OP_REG(x)       OP_LI(x)        /* For readability */
 197 #define MASK_REG        MASK_LI         /* For readability */
 198
 199 /* The 'n' bit at bit 10 */
 200 #define n(x)            ((x) << 10)
 201
 202 /* The 'i' bit at bit 11 */
 203 #define i(x)            ((x) << 11)
 204
 205 /* The 'F' bit at bit 27 */
 206 #define F(x)            ((x) << 27)
 207
 208 /* The 'E' bit at bit 27 */
 209 #define E(x)            ((x) << 27)
 210
 211 /* The 'M' bit at bit 15 in register and long immediate opcodes */
 212 #define M_REG(x)        ((x) << 15)
 213 #define M_LI(x)         ((x) << 15)
 214
 215 /* The 'M' bit at bit 17 in short immediate opcodes */
 216 #define M_SI(x)         ((x) << 17)
 217
 218 /* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
 219 #define SZ_REG(x)       ((x) << 13)
 220 #define SZ_LI(x)        ((x) << 13)
 221
 222 /* The 'SZ' field at bits 16-15 in short immediate opcodes */
 223 #define SZ_SI(x)        ((x) << 15)
 224
 225 /* The 'D' (direct external memory access) bit at bit 10 in long immediate
 226    and register opcodes. */
 227 #define D(x)            ((x) << 10)
 228
 229 /* The 'S' (scale offset by data size) bit at bit 11 in long immediate
 230    and register opcodes. */
 231 #define S(x)            ((x) << 11)
 232
 233 /* The 'PD' field at bits 10-9 in floating point instructions */
 234 #define PD(x)           ((x) << 9)
 235
 236 /* The 'P2' field at bits 8-7 in floating point instructions */
 237 #define P2(x)           ((x) << 7)
 238
 239 /* The 'P1' field at bits 6-5 in floating point instructions */
 240 #define P1(x)           ((x) << 5)
 241
 242 /* The 'a' field at bit 16 in vector instructions */
 243 #define V_a(x)          ((x) << 16)
 244
 245 /* The 'm' field at bit 10 in vector instructions */
 246 #define V_m(x)          ((x) << 10)
 247
 248 /* The 'S' field at bit 9 in vector instructions */
 249 #define V_S(x)          ((x) << 9)
 250
 251 /* The 'Z' field at bit 8 in vector instructions */
 252 #define V_Z(x)          ((x) << 8)
 253
 254 /* The 'p' field at bit 6 in vector instructions */
 255 #define V_p(x)          ((x) << 6)
 256
 257 /* The opcode field at bits 21-17 for vector instructions */
 258 #define OP_V(x)         ((x) << 17)
 259 #define MASK_V          OP_V(0x1F)
 260
 261 \f
 262 /* The opcode table.  Formatted for better readability on a wide screen. */
 263
 264 const struct tic80_opcode tic80_opcodes[] = {
 265
 266   /* The "nop" instruction is really "rdcr 0,r0".  We put it first so that this
 267      specific bit pattern will get disassembled as a nop rather than an rdcr. The
 268      mask of all ones ensures that this will happen. */
 269
 270   {"nop",       OP_SI(0x4),     ~0,             0,              {0}                     },
 271
 272   /* The "br" instruction is really "bbz target,r0,31".  We put it first so that
 273      this specific bit pattern will get disassembled as a br rather than bbz. */
 274
 275   {"br",        OP_SI(0x48),    0xFFFF8000,     0,      {OFF_SS_PC}                     },
 276   {"br",        OP_REG(0x390),  0xFFFFF000,     0,      {REG_0}                 },
 277   {"br",        OP_LI(0x391),   0xFFFFF000,     0,      {OFF_SL_PC}                     },
 278
 279   {"br.a",      OP_SI(0x49),    0xFFFF8000,     0,      {OFF_SS_PC}                     },
 280   {"br.a",      OP_REG(0x392),  0xFFFFF000,     0,      {REG_0}                 },
 281   {"br.a",      OP_LI(0x393),   0xFFFFF000,     0,      {OFF_SL_PC}                     },
 282
 283   /* Signed integer ADD */
 284
 285   {"add",       OP_SI(0x58),    MASK_SI,        0,      {SSI, REG_22, REG_DEST} },
 286   {"add",       OP_REG(0x3B0),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 287   {"add",       OP_LI(0x3B1),   MASK_LI,        0,      {LSI, REG_22, REG_DEST} },
 288
 289   /* Unsigned integer ADD */
 290
 291   {"addu",      OP_SI(0x59),    MASK_SI,        0,      {SSI, REG_22, REG_DEST} },
 292   {"addu",      OP_REG(0x3B2),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 293   {"addu",      OP_LI(0x3B3),   MASK_LI,        0,      {LSI, REG_22, REG_DEST} },
 294
 295   /* Bitwise AND */
 296
 297   {"and",       OP_SI(0x11),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 298   {"and.tt",    OP_SI(0x11),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 299
 300   {"and",       OP_REG(0x322),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 301   {"and.tt",    OP_REG(0x322),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 302
 303   {"and",       OP_LI(0x323),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 304   {"and.tt",    OP_LI(0x323),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 305
 306   /* Bitwise AND with ones complement of both sources */
 307
 308   {"and.ff",    OP_SI(0x18),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 309   {"and.ff",    OP_REG(0x330),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 310   {"and.ff",    OP_LI(0x331),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 311
 312   /* Bitwise AND with ones complement of source 1 */
 313
 314   {"and.ft",    OP_SI(0x14),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 315   {"and.ft",    OP_REG(0x328),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 316   {"and.ft",    OP_LI(0x329),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 317
 318   /* Bitwise AND with ones complement of source 2 */
 319
 320   {"and.tf",    OP_SI(0x12),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 321   {"and.tf",    OP_REG(0x324),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 322   {"and.tf",    OP_LI(0x325),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 323
 324   /* Branch Bit One - nonannulled */
 325
 326   {"bbo",       OP_SI(0x4A),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 327   {"bbo",       OP_REG(0x394),  MASK_REG,       0,      {REG_0, REG_22, BITNUM} },
 328   {"bbo",       OP_LI(0x395),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 329
 330   /* Branch Bit One - annulled */
 331
 332   {"bbo.a",     OP_SI(0x4B),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 333   {"bbo.a",     OP_REG(0x396),  MASK_REG,       0,      {REG_0, REG_22, BITNUM} },
 334   {"bbo.a",     OP_LI(0x397),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 335
 336   /* Branch Bit Zero - nonannulled */
 337
 338   {"bbz",       OP_SI(0x48),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 339   {"bbz",       OP_REG(0x390),  MASK_REG,       0,      {REG_0, REG_22, BITNUM} },
 340   {"bbz",       OP_LI(0x391),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 341
 342   /* Branch Bit Zero - annulled */
 343
 344   {"bbz.a",     OP_SI(0x49),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 345   {"bbz.a",     OP_REG(0x392),  MASK_REG,       0,      {REG_0, REG_22, BITNUM} },
 346   {"bbz.a",     OP_LI(0x393),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 347
 348   /* Branch Conditional - nonannulled */
 349
 350   {"bcnd",      OP_SI(0x4C),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },
 351   {"bcnd",      OP_REG(0x398),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 352   {"bcnd",      OP_LI(0x399),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
 353
 354   /* Branch Conditional - annulled */
 355
 356   {"bcnd.a",    OP_SI(0x4D),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },
 357   {"bcnd.a",    OP_REG(0x39A),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 358   {"bcnd.a",    OP_LI(0x39B),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
 359
 360   /* Branch Control Register */
 361
 362   {"brcr",      OP_SI(0x6),     MASK_SI,        0,      {CR_SI}                 },
 363   {"brcr",      OP_REG(0x30C),  MASK_REG,       0,      {REG_0}                 },
 364   {"brcr",      OP_LI(0x30D),   MASK_LI,        0,      {CR_LI}                 },
 365
 366   /* Branch and save return - nonannulled */
 367
 368   {"bsr",       OP_SI(0x40),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },
 369   {"bsr",       OP_REG(0x380),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 370   {"bsr",       OP_LI(0x381),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
 371
 372   /* Branch and save return - annulled */
 373
 374   {"bsr.a",     OP_SI(0x41),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },
 375   {"bsr.a",     OP_REG(0x382),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 376   {"bsr.a",     OP_LI(0x383),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
 377
 378   /* Send command */
 379
 380   {"cmnd",      OP_SI(0x2),     MASK_SI,        0,      {SUI}                   },
 381   {"cmnd",      OP_REG(0x304),  MASK_REG,       0,      {REG_0}                 },
 382   {"cmnd",      OP_LI(0x305),   MASK_LI,        0,      {LUI}                   },
 383
 384   /* Integer compare */
 385
 386   {"cmp",       OP_SI(0x50),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
 387   {"cmp",       OP_REG(0x3A0),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 388   {"cmp",       OP_LI(0x3A1),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
 389
 390   /* Flush data cache subblock - don't clear subblock preset flag */
 391
 392   {"dcachec",   OP_SI(0x38),    F(1) | (MASK_SI & ~M_SI(1)),                    0, {SSI, REG_BASE_M_SI} },
 393   {"dcachec",   OP_REG(0x370),  F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),    0, {REG_0, REG_BASE_M_LI}       },
 394   {"dcachec",   OP_LI(0x371),   F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1),      0, {LSI, REG_BASE_M_LI} },
 395
 396   /* Flush data cache subblock - clear subblock preset flag */
 397
 398   {"dcachef",   OP_SI(0x38) | F(1),     F(1) | (MASK_SI & ~M_SI(1)),                    0, {SSI, REG_BASE_M_SI} },
 399   {"dcachef",   OP_REG(0x370) | F(1),   F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),    0, {REG_0, REG_BASE_M_LI}       },
 400   {"dcachef",   OP_LI(0x371) | F(1),    F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1),      0, {LSI, REG_BASE_M_LI} },
 401
 402   /* Direct load signed data into register */
 403
 404   {"dld.b",     OP_REG(0x340) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 405   {"dld.h",     OP_REG(0x342) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 406   {"dld",       OP_REG(0x344) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 407   {"dld.d",     OP_REG(0x346) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 408
 409   {"dld.b",     OP_LI(0x341) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 410   {"dld.h",     OP_LI(0x343) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 411   {"dld",       OP_LI(0x345) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 412   {"dld.d",     OP_LI(0x347) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 413
 414   /* Direct load unsigned data into register */
 415
 416   {"dld.ub",    OP_REG(0x350) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 417   {"dld.uh",    OP_REG(0x352) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 418
 419   {"dld.ub",    OP_LI(0x351) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 420   {"dld.uh",    OP_LI(0x353) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 421
 422   /* Direct store data into memory */
 423
 424   {"dst.b",     OP_REG(0x360) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 425   {"dst.h",     OP_REG(0x362) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 426   {"dst",       OP_REG(0x364) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 427   {"dst.d",     OP_REG(0x366) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 428
 429   {"dst.b",     OP_LI(0x361) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 430   {"dst.h",     OP_LI(0x363) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 431   {"dst",       OP_LI(0x365) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 432   {"dst.d",     OP_LI(0x367) | D(1),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 433
 434   /* Emulation stop */
 435
 436   {"estop",     OP_LI(0x3FC),   MASK_LI,        0,              {0}     },
 437
 438   /* Emulation trap */
 439
 440   {"etrap",     OP_SI(0x1) | E(1),      MASK_SI | E(1),         0,      {SUI}   },
 441   {"etrap",     OP_REG(0x302) | E(1),   MASK_REG | E(1),        0,      {REG_0} },
 442   {"etrap",     OP_LI(0x303) | E(1),    MASK_LI | E(1),         0,      {LUI}   },
 443
 444   /* Floating-point addition */
 445
 446   {"fadd.sss",  OP_REG(0x3E0) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 447   {"fadd.ssd",  OP_REG(0x3E0) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 448   {"fadd.sdd",  OP_REG(0x3E0) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 449   {"fadd.dsd",  OP_REG(0x3E0) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 450   {"fadd.ddd",  OP_REG(0x3E0) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 451
 452   {"fadd.sss",  OP_LI(0x3E1) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 453   {"fadd.ssd",  OP_LI(0x3E1) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 454   {"fadd.sdd",  OP_LI(0x3E1) | PD(1) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 455
 456   /* Floating point compare */
 457
 458   {"fcmp.ss",   OP_REG(0x3EA) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 459   {"fcmp.sd",   OP_REG(0x3EA) | PD(0) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 460   {"fcmp.ds",   OP_REG(0x3EA) | PD(0) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 461   {"fcmp.dd",   OP_REG(0x3EA) | PD(0) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 462
 463   {"fcmp.ss",   OP_LI(0x3EB) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3),  0,     {SPFI, REG_22, REG_DEST}       },
 464   {"fcmp.sd",   OP_LI(0x3EB) | PD(0) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3),  0,     {SPFI, REG_22, REG_DEST}       },
 465
 466   /* Floating point divide */
 467
 468   {"fdiv.sss",  OP_REG(0x3E6) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 469   {"fdiv.ssd",  OP_REG(0x3E6) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 470   {"fdiv.sdd",  OP_REG(0x3E6) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 471   {"fdiv.dsd",  OP_REG(0x3E6) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 472   {"fdiv.ddd",  OP_REG(0x3E6) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 473
 474   {"fdiv.sss",  OP_LI(0x3E7) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 475   {"fdiv.ssd",  OP_LI(0x3E7) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 476   {"fdiv.sdd",  OP_LI(0x3E7) | PD(1) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 477
 478   /* Floating point multiply */
 479
 480   {"fmpy.sss",  OP_REG(0x3E4) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 481   {"fmpy.ssd",  OP_REG(0x3E4) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 482   {"fmpy.sdd",  OP_REG(0x3E4) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 483   {"fmpy.dsd",  OP_REG(0x3E4) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 484   {"fmpy.ddd",  OP_REG(0x3E4) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 485   {"fmpy.iii",  OP_REG(0x3E4) | PD(2) | P2(2) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 486   {"fmpy.uuu",  OP_REG(0x3E4) | PD(3) | P2(3) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 487
 488   {"fmpy.sss",  OP_LI(0x3E5) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 489   {"fmpy.ssd",  OP_LI(0x3E5) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 490   {"fmpy.sdd",  OP_LI(0x3E5) | PD(1) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 491   {"fmpy.iii",  OP_LI(0x3E5) | PD(2) | P2(2) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_22, REG_DEST}        },
 492   {"fmpy.uuu",  OP_LI(0x3E5) | PD(3) | P2(3) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LUI, REG_22, REG_DEST}        },
 493
 494   /* Convert/Round to Minus Infinity */
 495
 496   {"frndm.ss",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 497   {"frndm.sd",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 498   {"frndm.si",  OP_REG(0x3E8) | PD(2) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 499   {"frndm.su",  OP_REG(0x3E8) | PD(3) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 500   {"frndm.ds",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 501   {"frndm.dd",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 502   {"frndm.di",  OP_REG(0x3E8) | PD(2) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 503   {"frndm.du",  OP_REG(0x3E8) | PD(3) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 504   {"frndm.is",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 505   {"frndm.id",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 506   {"frndm.us",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 507   {"frndm.ud",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 508
 509   {"frndm.ss",  OP_LI(0x3E9) | PD(0) | P2(3) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 510   {"frndm.sd",  OP_LI(0x3E9) | PD(1) | P2(3) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 511   {"frndm.si",  OP_LI(0x3E9) | PD(2) | P2(3) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 512   {"frndm.su",  OP_LI(0x3E9) | PD(3) | P2(3) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 513   {"frndm.is",  OP_LI(0x3E9) | PD(0) | P2(3) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 514   {"frndm.id",  OP_LI(0x3E9) | PD(1) | P2(3) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 515   {"frndm.us",  OP_LI(0x3E9) | PD(0) | P2(3) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 516   {"frndm.ud",  OP_LI(0x3E9) | PD(1) | P2(3) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 517
 518   /* Convert/Round to Nearest */
 519
 520   {"frndn.ss",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 521   {"frndn.sd",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 522   {"frndn.si",  OP_REG(0x3E8) | PD(2) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 523   {"frndn.su",  OP_REG(0x3E8) | PD(3) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 524   {"frndn.ds",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 525   {"frndn.dd",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 526   {"frndn.di",  OP_REG(0x3E8) | PD(2) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 527   {"frndn.du",  OP_REG(0x3E8) | PD(3) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 528   {"frndn.is",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 529   {"frndn.id",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 530   {"frndn.us",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 531   {"frndn.ud",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 532
 533   {"frndn.ss",  OP_LI(0x3E9) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 534   {"frndn.sd",  OP_LI(0x3E9) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 535   {"frndn.si",  OP_LI(0x3E9) | PD(2) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 536   {"frndn.su",  OP_LI(0x3E9) | PD(3) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 537   {"frndn.is",  OP_LI(0x3E9) | PD(0) | P2(0) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 538   {"frndn.id",  OP_LI(0x3E9) | PD(1) | P2(0) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 539   {"frndn.us",  OP_LI(0x3E9) | PD(0) | P2(0) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 540   {"frndn.ud",  OP_LI(0x3E9) | PD(1) | P2(0) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 541
 542   /* Convert/Round to Positive Infinity */
 543
 544   {"frndp.ss",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 545   {"frndp.sd",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 546   {"frndp.si",  OP_REG(0x3E8) | PD(2) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 547   {"frndp.su",  OP_REG(0x3E8) | PD(3) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 548   {"frndp.ds",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 549   {"frndp.dd",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 550   {"frndp.di",  OP_REG(0x3E8) | PD(2) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 551   {"frndp.du",  OP_REG(0x3E8) | PD(3) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 552   {"frndp.is",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 553   {"frndp.id",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 554   {"frndp.us",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 555   {"frndp.ud",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 556
 557   {"frndp.ss",  OP_LI(0x3E9) | PD(0) | P2(2) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 558   {"frndp.sd",  OP_LI(0x3E9) | PD(1) | P2(2) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 559   {"frndp.si",  OP_LI(0x3E9) | PD(2) | P2(2) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 560   {"frndp.su",  OP_LI(0x3E9) | PD(3) | P2(2) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 561   {"frndp.is",  OP_LI(0x3E9) | PD(0) | P2(2) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 562   {"frndp.id",  OP_LI(0x3E9) | PD(1) | P2(2) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 563   {"frndp.us",  OP_LI(0x3E9) | PD(0) | P2(2) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 564   {"frndp.ud",  OP_LI(0x3E9) | PD(1) | P2(2) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 565
 566   /* Convert/Round to Zero */
 567
 568   {"frndz.ss",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 569   {"frndz.sd",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 570   {"frndz.si",  OP_REG(0x3E8) | PD(2) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 571   {"frndz.su",  OP_REG(0x3E8) | PD(3) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 572   {"frndz.ds",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 573   {"frndz.dd",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 574   {"frndz.di",  OP_REG(0x3E8) | PD(2) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 575   {"frndz.du",  OP_REG(0x3E8) | PD(3) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 576   {"frndz.is",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 577   {"frndz.id",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 578   {"frndz.us",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 579   {"frndz.ud",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 580
 581   {"frndz.ss",  OP_LI(0x3E9) | PD(0) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 582   {"frndz.sd",  OP_LI(0x3E9) | PD(1) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 583   {"frndz.si",  OP_LI(0x3E9) | PD(2) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 584   {"frndz.su",  OP_LI(0x3E9) | PD(3) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 585   {"frndz.is",  OP_LI(0x3E9) | PD(0) | P2(1) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 586   {"frndz.id",  OP_LI(0x3E9) | PD(1) | P2(1) | P1(2),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 587   {"frndz.us",  OP_LI(0x3E9) | PD(0) | P2(1) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 588   {"frndz.ud",  OP_LI(0x3E9) | PD(1) | P2(1) | P1(3),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {LSI, REG_DEST}        },
 589
 590   /* Floating point square root */
 591
 592   {"fsqrt.ss",  OP_REG(0x3EE) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 593   {"fsqrt.sd",  OP_REG(0x3EE) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 594   {"fsqrt.dd",  OP_REG(0x3EE) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 595
 596   {"fsqrt.ss",  OP_LI(0x3EF) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 597   {"fsqrt.sd",  OP_LI(0x3EF) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_DEST}       },
 598
 599   /* Floating point subtraction */
 600
 601   { "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 602   { "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 603   { "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 604   { "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 605   { "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 606
 607   { "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 608   { "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 609   { "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0),   MASK_LI | PD(3) | P2(3) | P1(3), 0,      {SPFI, REG_22, REG_DEST}       },
 610
 611   /* Illegal instructions */
 612
 613   {"illop0",    OP_SI(0x0),     MASK_SI,        0,      0},
 614   {"illopF",    0x1FF << 13,    0x1FF << 13,    0,      0},
 615
 616   /* Jump and save return */
 617
 618   {"jsr",       OP_SI(0x44),    MASK_SI,        0,      {OFF_SS_BR, REG_BASE, REG_DEST} },
 619   {"jsr.a",     OP_SI(0x45),    MASK_SI,        0,      {OFF_SS_BR, REG_BASE, REG_DEST} },
 620
 621   {"jsr",       OP_REG(0x388),  MASK_REG,       0,      {REG_0, REG_BASE, REG_DEST}     },
 622   {"jsr.a",     OP_REG(0x38A),  MASK_REG,       0,      {REG_0, REG_BASE, REG_DEST}     },
 623
 624   {"jsr",       OP_LI(0x389),   MASK_LI,        0,      {OFF_SL_BR, REG_BASE, REG_DEST} },
 625   {"jsr.a",     OP_LI(0x38B),   MASK_LI,        0,      {OFF_SL_BR, REG_BASE, REG_DEST} },
 626
 627   /* Load Signed Data Into Register */
 628
 629   {"ld.b",      OP_SI(0x20),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 630   {"ld.h",      OP_SI(0x21),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 631   {"ld",        OP_SI(0x22),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 632   {"ld.d",      OP_SI(0x23),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 633
 634   {"ld.b",      OP_REG(0x340) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 635   {"ld.h",      OP_REG(0x342) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 636   {"ld",        OP_REG(0x344) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 637   {"ld.d",      OP_REG(0x346) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 638
 639   {"ld.b",      OP_LI(0x341) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 640   {"ld.h",      OP_LI(0x343) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 641   {"ld",        OP_LI(0x345) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 642   {"ld.d",      OP_LI(0x347) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 643
 644   /* Load Unsigned Data Into Register */
 645
 646   {"ld.ub",     OP_SI(0x28),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 647   {"ld.uh",     OP_SI(0x29),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 648
 649   {"ld.ub",     OP_REG(0x350) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 650   {"ld.uh",     OP_REG(0x352) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 651
 652   {"ld.ub",     OP_LI(0x351) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 653   {"ld.uh",     OP_LI(0x353) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 654
 655   /* Leftmost one */
 656
 657   {"lmo",       OP_LI(0x3F0),   MASK_LI,        0,      {REG_22, REG_DEST}      },
 658
 659   /* Bitwise logical OR */
 660
 661   {"or.ff",     OP_SI(0x1E),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 662   {"or.ft",     OP_SI(0x1D),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 663   {"or.tf",     OP_SI(0x1B),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 664   {"or.tt",     OP_SI(0x17),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 665
 666   {"or.ff",     OP_REG(0x33C),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 667   {"or.ft",     OP_REG(0x33A),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 668   {"or.tf",     OP_REG(0x336),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 669   {"or.tt",     OP_REG(0x32E),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 670
 671   {"or.ff",     OP_LI(0x33D),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 672   {"or.ft",     OP_LI(0x33B),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 673   {"or.tf",     OP_LI(0x337),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 674   {"or.tt",     OP_LI(0x32F),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 675
 676   /* Read Control Register */
 677
 678   {"rdcr",      OP_SI(0x4),     MASK_SI | (0x1F << 22),         0,      {CR_SI, REG_DEST}       },
 679   {"rdcr",      OP_REG(0x308),  MASK_REG | (0x1F << 22),        0,      {REG_0, REG_DEST}       },
 680   {"rdcr",      OP_LI(0x309),   MASK_LI | (0x1F << 22),         0,      {CR_LI, REG_DEST}       },
 681
 682   /* Rightmost one */
 683
 684   {"rmo",       OP_LI(0x3F2),   MASK_LI,        0,              {REG_22, REG_DEST}      },
 685
 686   /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions.
 687      They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */
 688
 689   {"rotl",      OP_SI(0x8) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 690   {"sl.dz",     OP_SI(0x8) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 691   {"sl.dm",     OP_SI(0x9) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 692   {"sl.ds",     OP_SI(0xA) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 693   {"sl.ez",     OP_SI(0xB) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 694   {"sl.em",     OP_SI(0xC) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 695   {"sl.es",     OP_SI(0xD) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 696   {"shl",       OP_SI(0xE) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 697   {"sl.iz",     OP_SI(0xE) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 698   {"ins",       OP_SI(0xF) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 699   {"sl.im",     OP_SI(0xF) | i(0) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 700
 701   {"rotl",      OP_REG(0x310) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 702   {"sl.dz",     OP_REG(0x310) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 703   {"sl.dm",     OP_REG(0x312) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 704   {"sl.ds",     OP_REG(0x314) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 705   {"sl.ez",     OP_REG(0x316) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 706   {"sl.em",     OP_REG(0x318) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 707   {"sl.es",     OP_REG(0x31A) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 708   {"shl",       OP_REG(0x31C) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 709   {"sl.iz",     OP_REG(0x31C) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 710   {"ins",       OP_REG(0x31E) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 711   {"sl.im",     OP_REG(0x31E) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 712
 713   /* Shift Register Left With Inverted Endmask */
 714
 715   {"sli.dz",    OP_SI(0x8) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 716   {"sli.dm",    OP_SI(0x9) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 717   {"sli.ds",    OP_SI(0xA) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 718   {"sli.ez",    OP_SI(0xB) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 719   {"sli.em",    OP_SI(0xC) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 720   {"sli.es",    OP_SI(0xD) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 721   {"sli.iz",    OP_SI(0xE) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 722   {"sli.im",    OP_SI(0xF) | i(1) | n(0),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 723
 724   {"sli.dz",    OP_REG(0x310) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 725   {"sli.dm",    OP_REG(0x312) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 726   {"sli.ds",    OP_REG(0x314) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 727   {"sli.ez",    OP_REG(0x316) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 728   {"sli.em",    OP_REG(0x318) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 729   {"sli.es",    OP_REG(0x31A) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 730   {"sli.iz",    OP_REG(0x31C) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 731   {"sli.im",    OP_REG(0x31E) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 732
 733   /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions.
 734      They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */
 735
 736   {"rotr",      OP_SI(0x8) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 737   {"extu",      OP_SI(0x8) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 738   {"sr.dz",     OP_SI(0x8) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 739   {"sr.dm",     OP_SI(0x9) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 740   {"exts",      OP_SI(0xA) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 741   {"sr.ds",     OP_SI(0xA) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 742   {"srl",       OP_SI(0xB) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 743   {"sr.ez",     OP_SI(0xB) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 744   {"sr.em",     OP_SI(0xC) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 745   {"sra",       OP_SI(0xD) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 746   {"sr.es",     OP_SI(0xD) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 747   {"sr.iz",     OP_SI(0xE) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 748   {"sr.im",     OP_SI(0xF) | i(0) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 749
 750   {"rotr",      OP_REG(0x310) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 751   {"extu",      OP_REG(0x310) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 752   {"sr.dz",     OP_REG(0x310) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 753   {"sr.dm",     OP_REG(0x312) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 754   {"exts",      OP_REG(0x314) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 755   {"sr.ds",     OP_REG(0x314) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 756   {"srl",       OP_REG(0x316) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 757   {"sr.ez",     OP_REG(0x316) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 758   {"sr.em",     OP_REG(0x318) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 759   {"sra",       OP_REG(0x31A) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 760   {"sr.es",     OP_REG(0x31A) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 761   {"sr.iz",     OP_REG(0x31C) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 762   {"sr.im",     OP_REG(0x31E) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 763
 764   /* Shift Register Right With Inverted Endmask */
 765
 766   {"sri.dz",    OP_SI(0x8) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 767   {"sri.dm",    OP_SI(0x9) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 768   {"sri.ds",    OP_SI(0xA) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 769   {"sri.ez",    OP_SI(0xB) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 770   {"sri.em",    OP_SI(0xC) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 771   {"sri.es",    OP_SI(0xD) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 772   {"sri.iz",    OP_SI(0xE) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 773   {"sri.im",    OP_SI(0xF) | i(1) | n(1),       MASK_SI | i(1) | n(1),  0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 774
 775   {"sri.dz",    OP_REG(0x310) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 776   {"sri.dm",    OP_REG(0x312) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 777   {"sri.ds",    OP_REG(0x314) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 778   {"sri.ez",    OP_REG(0x316) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 779   {"sri.em",    OP_REG(0x318) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 780   {"sri.es",    OP_REG(0x31A) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 781   {"sri.iz",    OP_REG(0x31C) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 782   {"sri.im",    OP_REG(0x31E) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 783
 784   /* Store Data into Memory */
 785
 786   {"st.b",      OP_SI(0x30),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}},
 787   {"st.h",      OP_SI(0x31),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}},
 788   {"st",        OP_SI(0x32),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}},
 789   {"st.d",      OP_SI(0x33),            (MASK_SI & ~M_SI(1)),           0,      {SSI, REG_BASE_M_SI, REG_DEST}},
 790
 791   {"st.b",      OP_REG(0x360) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 792   {"st.h",      OP_REG(0x362) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 793   {"st",        OP_REG(0x364) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 794   {"st.d",      OP_REG(0x366) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 795
 796   {"st.b",      OP_LI(0x361) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 797   {"st.h",      OP_LI(0x363) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 798   {"st",        OP_LI(0x365) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 799   {"st.d",      OP_LI(0x367) | D(0),    (MASK_LI & ~M_REG(1)) | D(1),   0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 800
 801   /* Signed Integer Subtract */
 802
 803   {"sub",       OP_SI(0x5A),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
 804   {"sub",       OP_REG(0x3B4),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 805   {"sub",       OP_LI(0x3B5),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
 806
 807   /* Unsigned Integer Subtract */
 808
 809   {"subu",      OP_SI(0x5B),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
 810   {"subu",      OP_REG(0x3B6),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 811   {"subu",      OP_LI(0x3B7),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
 812
 813   /* Swap Control Register */
 814
 815   {"swcr",      OP_SI(0x5),     MASK_SI,        0,      {CR_SI, REG_22, REG_DEST}       },
 816   {"swcr",      OP_REG(0x30A),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 817   {"swcr",      OP_LI(0x30B),   MASK_LI,        0,      {CR_LI, REG_22, REG_DEST}       },
 818
 819   /* Trap */
 820
 821   {"trap",      OP_SI(0x1) | E(0),      MASK_SI | E(1),         0,      {SUI}   },
 822   {"trap",      OP_REG(0x302) | E(0),   MASK_REG | E(1),        0,      {REG_0} },
 823   {"trap",      OP_LI(0x303) | E(0),    MASK_LI | E(1),         0,      {LUI}   },
 824
 825   /* Vector Floating-Point Add */
 826
 827   {"vadd.ss",   OP_REG(0x3C0) | P2(0) | P1(0),  MASK_REG | V_a(1) | P2(1) | P1(1),      TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
 828   {"vadd.sd",   OP_REG(0x3C0) | P2(1) | P1(0),  MASK_REG | V_a(1) | P2(1) | P1(1),      TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
 829   {"vadd.dd",   OP_REG(0x3C0) | P2(1) | P1(1),  MASK_REG | V_a(1) | P2(1) | P1(1),      TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
 830
 831   {"vadd.ss",   OP_LI(0x3C1) | P2(0) | P1(0),   MASK_LI | V_a(1) | P2(1) | P1(1),       TIC80_VECTOR,   {SPFI, REG_22, REG_22}  },
 832   {"vadd.sd",   OP_LI(0x3C1) | P2(1) | P1(0),   MASK_LI | V_a(1) | P2(1) | P1(1),       TIC80_VECTOR,   {SPFI, REG_22, REG_22}  },
 833
 834   /* Vector Load Data Into Register */
 835
 836   {"vld0.s",    OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
 837   {"vld1.s",    OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
 838   {"vld0.d",    OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
 839   {"vld1.d",    OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
 840
 841
 842   {"xnor",      OP_LI(0x333),   MASK_LI,        0,              FIXME},
 843   {"xnor",      OP_REG(0x332),  MASK_REG,       0,              FIXME},
 844   {"xnor",      OP_SI(0x19),    MASK_SI,        0,              FIXME},
 845   {"xor",       OP_LI(0x32D),   MASK_LI,        0,              FIXME},
 846   {"xor",       OP_REG(0x32C),  MASK_REG,       0,              FIXME},
 847   {"xor",       OP_SI(0x16),    MASK_SI,        0,              FIXME},
 848
 849 };
 850
 851 const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
 852