sim/aarch64/ChangeLog

   1 2021-05-14  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * cpustate.h: Update include path.
   4         * interp.c: Likewise.
   5
   6 2021-05-04  Mike Frysinger  <vapier@gentoo.org>
   7
   8         * configure: Regenerate.
   9
  10 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  11
  12         * config.in, configure: Regenerate.
  13
  14 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  15
  16         * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
  17         (aarch64_set_FP_double, aarch64_set_FP_long_double,
  18         aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
  19
  20 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  21
  22         * simulator.c (do_fcvtzu): Change UL to ULL.
  23
  24 2021-04-26  Mike Frysinger  <vapier@gentoo.org>
  25
  26         * aclocal.m4, config.in, configure: Regenerate.
  27
  28 2021-04-22  Tom Tromey  <tom@tromey.com>
  29
  30         * configure, config.in: Rebuild.
  31
  32 2021-04-22  Tom Tromey  <tom@tromey.com>
  33
  34         * configure: Rebuild.
  35
  36 2021-04-21  Mike Frysinger  <vapier@gentoo.org>
  37
  38         * aclocal.m4: Regenerate.
  39
  40 2021-04-21  Simon Marchi  <simon.marchi@polymtl.ca>
  41
  42         * configure: Regenerate.
  43
  44 2021-04-18  Mike Frysinger  <vapier@gentoo.org>
  45
  46         * configure: Regenerate.
  47
  48 2021-04-12  Mike Frysinger  <vapier@gentoo.org>
  49
  50         * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
  51
  52 2021-04-07  Jim Wilson  <jimw@sifive.com>
  53
  54         PR sim/27483
  55         * simulator.c (set_flags_for_add32): Compare uresult against
  56         itself.  Compare sresult against itself.
  57
  58 2021-04-02  Mike Frysinger  <vapier@gentoo.org>
  59
  60         * aclocal.m4, configure: Regenerate.
  61
  62 2021-02-28  Mike Frysinger  <vapier@gentoo.org>
  63
  64         * configure: Regenerate.
  65
  66 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
  67
  68         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
  69         * aclocal.m4, configure: Regenerate.
  70
  71 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
  72
  73         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
  74         * aclocal.m4, configure: Regenerate.
  75
  76 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
  77
  78         * configure: Regenerate.
  79
  80 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
  81
  82         * config.in, configure: Regenerate.
  83
  84 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
  85
  86         * configure: Regenerate.
  87
  88 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
  89
  90         * configure: Regenerate.
  91
  92 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
  93
  94         * configure: Regenerate.
  95
  96 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
  97
  98         PR sim/25318
  99         * simulator.c (blr): Read destination register before calling
 100         aarch64_save_LR.
 101
 102 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
 103
 104         * cpustate.c: Add 'libiberty.h' include.
 105         * interp.c: Add 'sim-assert.h' include.
 106
 107 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
 108
 109         * configure: Regenerate.
 110
 111 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
 112
 113         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
 114         registers based on structure size.
 115         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
 116         (LD1_1): Replace with call to vec_load.
 117         (vec_store): Add new M argument.  Rewrite to iterate over registers
 118         based on structure size.
 119         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
 120         (ST1_1): Replace with call to vec_store.
 121
 122 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
 123
 124         * simulator.c (do_vec_FCVTL): New.
 125         (do_vec_op1): Call do_vec_FCVTL.
 126
 127         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
 128         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
 129         (do_scalar_vec): Add calls to new functions.
 130
 131 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
 132
 133         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
 134         flag check.
 135
 136 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
 137
 138         * simulator.c (mul64hi): Shift carry left by 32.
 139         (smulh): Change signum to negate.  If negate, invert result, and add
 140         carry bit if low part of multiply result is zero.
 141
 142 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
 143
 144         * simulator.c (do_vec_SMOV_into_scalar): New.
 145         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
 146         Rewritten.
 147         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
 148         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
 149         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
 150         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
 151
 152         * simulator.c (popcount): New.
 153         (do_vec_CNT): New.
 154         (do_vec_op1): Add do_vec_CNT call.
 155
 156 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
 157
 158         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
 159         with type set to input type size.
 160         (do_vec_xtl): Change bias from 3 to 4 for byte case.
 161
 162 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
 163
 164         * simulator.c (do_vec_MLA): Rewrite switch body.
 165
 166         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
 167         2.  Move test_false if inside loop.  Fix logic for computing result
 168         stored to vd.
 169
 170         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
 171         (do_vec_LDn_single, do_vec_STn_single): New.
 172         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
 173         loop over nregs using new var n.  Add n times size to address in loop.
 174         Add n to vd in loop.
 175         (do_vec_load_store): Add comment for instruction bit 24.  New var
 176         single to hold instruction bit 24.  Add new code to use single.  Move
 177         ldnr support inside single if statements.  Fix ldnr register counts
 178         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 179
 180 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 181
 182         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 183
 184 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 185
 186         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 187         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 188         case 3, call HALT_UNALLOC unconditionally.
 189         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 190         i + 2.  Delete if on bias, change index to i + bias * X.
 191
 192 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 193
 194         * simulator.c (do_vec_UZP): Rewrite.
 195
 196 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 197
 198         * cpustate.c: Include math.h.
 199         (aarch64_set_FP_float): Use signbit to check for signed zero.
 200         (aarch64_set_FP_double): Likewise.
 201         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 202         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 203         args same size as third arg.
 204         (fmaxnm): Use isnan instead of fpclassify.
 205         (fminnm, dmaxnm, dminnm): Likewise.
 206         (do_vec_MLS): Reverse order of subtraction operands.
 207         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 208         aarch64_get_FP_float to get source register contents.
 209         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 210         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 211         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 212         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 213         raise_exception calls.
 214
 215 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 216
 217         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 218         Add comment to document NaN issue.
 219         (set_flags_for_double_compare): Likewise.
 220
 221 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 222
 223         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 224         (set_flags_for_add64): Replace with a modified copy of
 225         set_flags_for_sub64.
 226
 227 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 228
 229         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 230         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 231
 232 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 233
 234         * simulator.c (fsturs): Switch use of rn and st variables.
 235         (fsturd, fsturq): Likewise
 236
 237 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 238
 239         * interp.c: Include bfd.h.
 240         (symcount, symtab, aarch64_get_sym_value): Delete.
 241         (remove_useless_symbols): Change count type to long.
 242         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 243         and symtab local variables.
 244         (sim_create_inferior): Delete storage.  Replace symbol code
 245         with a call to trace_load_symbols.
 246         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 247         includes.
 248         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 249         trace_sym_value.
 250         * memory.h: Delete bfd.h include.
 251         (mem_add_blk): Delete unused prototype.
 252         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 253         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 254         (aarch64_get_sym_value): Delete.
 255
 256 2016-08-12  Nick Clifton  <nickc@redhat.com>
 257
 258         * simulator.c (aarch64_step): Revert pervious delta.
 259         (aarch64_run): Call sim_events_tick after each
 260         instruction is simulated, and if necessary call
 261         sim_events_process.
 262         * simulator.h: Revert previous delta.
 263
 264 2016-08-11  Nick Clifton  <nickc@redhat.com>
 265
 266         * interp.c (sim_create_inferior): Allow for being called with a
 267         NULL abfd parameter.  If a bfd is provided, initialise the sim
 268         with that start address.
 269         * simulator.c (HALT_NYI): Just print out the numeric value of the
 270         instruction when not tracing.
 271         (aarch64_step): Change from static to global.
 272         * simulator.h: Add a prototype for aarch64_step().
 273
 274 2016-07-27  Alan Modra  <amodra@gmail.com>
 275
 276         * memory.c: Don't include libbfd.h.
 277
 278 2016-07-21  Nick Clifton  <nickc@redhat.com>
 279
 280         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 281
 282 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 283
 284         * cpustate.h: Include config.h.
 285         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 286         use anonymous structs to align members.
 287         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 288         endian_le2h_4 to read instruction from pc.
 289
 290 2016-05-06  Nick Clifton  <nickc@redhat.com>
 291
 292         * simulator.c (do_FMLA_by_element): New function.
 293         (do_vec_op2): Call it.
 294
 295 2016-04-27  Nick Clifton  <nickc@redhat.com>
 296
 297         * simulator.c: Add TRACE_DECODE statements to all emulation
 298         functions.
 299
 300 2016-03-30  Nick Clifton  <nickc@redhat.com>
 301
 302         * cpustate.c (aarch64_set_reg_s32): New function.
 303         (aarch64_set_reg_u32): New function.
 304         (aarch64_get_FP_half): Place half precision value into the correct
 305         slot of the union.
 306         (aarch64_set_FP_half): Likewise.
 307         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 308         aarch64_set_reg_u32.
 309         * memory.c (FETCH_FUNC): Cast the read value to the access type
 310         before converting it to the return type.  Rename to FETCH_FUNC64.
 311         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 312         accesses.  Use for 32-bit memory access functions.
 313         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 314         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 315         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 316         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 317         (ldrh32_abs): Store 32 bit value not 64-bits.
 318         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 319         (do_vec_MOV_immediate): Fix computation of val.
 320         (do_vec_MVNI): Likewise.
 321         (DO_VEC_WIDENING_MUL): New macro.
 322         (do_vec_mull): Use new macro.
 323         (do_vec_mul): Use new macro.
 324         (do_vec_MLA): Read values before writing.
 325         (do_vec_xtl): Likewise.
 326         (do_vec_SSHL): Select correct shift value.
 327         (do_vec_USHL): Likewise.
 328         (do_scalar_UCVTF): New function.
 329         (do_scalar_vec): Call new function.
 330         (store_pair_u64): Treat reads of SP as reads of XZR.
 331
 332 2016-03-29  Nick Clifton  <nickc@redhat.com>
 333
 334         * cpustate.c: Remove space after asterisk in function parameters.
 335         * decode.h (greg): Delete unused function.
 336         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 337         * simulator.c: Use INSTR macro in more places.
 338         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 339         Remove extraneous whitespace.
 340
 341 2016-03-23  Nick Clifton  <nickc@redhat.com>
 342
 343         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 344         register as a half precision floating point number.
 345         (aarch64_set_FP_half): New function.  Similar, but for setting
 346         a half precision register.
 347         (aarch64_get_thread_id): New function.  Returns the value of the
 348         CPU's TPIDR register.
 349         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 350         floating point control register.
 351         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 352         register.
 353         * cpustate.h: Add prototypes for new functions.
 354         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 355         * memory.c: Use unaligned core access functions for all memory
 356         reads and writes.
 357         * simulator.c (HALT_NYI): Generate an error message if tracing
 358         will not tell the user why the simulator is halting.
 359         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 360         (INSTR): New time-saver macro.
 361         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 362         offset.
 363         (fldrh_abs): New function.  Likewise for 16-bit values.
 364         (do_vec_SSHL): Allow for negative shift values.
 365         (do_vec_USHL): Likewise.
 366         (do_vec_SHL): Correct computation of shift amount.
 367         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 368         shifts and computation of shift value.
 369         (clz): New function.  Counts leading zero bits.
 370         (do_vec_CLZ): New function.  Implements CLZ (vector).
 371         (do_vec_MOV_element): Call do_vec_CLZ.
 372         (dexSimpleFPCondCompare): Implement.
 373         (do_FCVT_half_to_single): New function.  Implements one of the
 374         FCVT operations.
 375         (do_FCVT_half_to_double): New function.  Likewise.
 376         (do_FCVT_single_to_half): New function.  Likewise.
 377         (do_FCVT_double_to_half): New function.  Likewise.
 378         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 379         (do_scalar_SHL): Handle negative shifts.
 380         (do_scalar_shift): Handle SSHR.
 381         (do_scalar_USHL): New function.
 382         (do_double_add): Simplify to just performing a double precision
 383         add operation.  Move remaining code into...
 384         (do_scalar_vec): ... New function.
 385         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 386         functions.
 387         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 388         registers.
 389         (system_set): New function.
 390         (do_MSR_immediate): New function.  Stub for now.
 391         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 392         instruction.
 393         (do_SYS): New function.  Stub for now,
 394         (dexSystem): Call new functions.
 395
 396 2016-03-18  Nick Clifton  <nickc@redhat.com>
 397
 398         * cpustate.c: Remove spurious spaces from TRACE strings.
 399         Print hex equivalents of floats and doubles.
 400         Check element number against array size when accessing vector
 401         registers.
 402         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 403         element index.
 404         (SET_VEC_ELEMENT): Likewise.
 405         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 406
 407         * memory.c: Trace memory reads when --trace-memory is enabled.
 408         Remove float and double load and store functions.
 409         * memory.h (aarch64_get_mem_float): Delete prototype.
 410         (aarch64_get_mem_double): Likewise.
 411         (aarch64_set_mem_float): Likewise.
 412         (aarch64_set_mem_double): Likewise.
 413         * simulator (IS_SET): Always return either 0 or 1.
 414         (IS_CLEAR): Likewise.
 415         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 416         and doubles using 64-bit memory accesses.
 417         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 418         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 419         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 420         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 421         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 422         (do_vec_MUL_by_element): New function.
 423         (do_vec_op2): Call do_vec_MUL_by_element.
 424         (do_scalar_NEG): New function.
 425         (do_double_add): Call do_scalar_NEG.
 426
 427 2016-03-03  Nick Clifton  <nickc@redhat.com>
 428
 429         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 430         (CondCompare): Swap interpretation of bit 30.
 431         (DO_ADDP): Delete macro.
 432         (do_vec_ADDP): Copy source registers before starting to update
 433         destination register.
 434         (do_vec_FADDP): Likewise.
 435         (do_vec_load_store): Fix computation of sizeof_operation.
 436         (rbit64): Fix type of constant.
 437         (aarch64_step): When displaying insn value, display all 32 bits.
 438
 439 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 440
 441         * config.in, configure: Regenerate.
 442
 443 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 444
 445         * configure: Regenerate.
 446
 447 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 448
 449         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 450         * configure: Regenerate.
 451
 452 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 453
 454         * configure: Regenerate.
 455
 456 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 457
 458         * configure: Regenerate.
 459
 460 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 461
 462         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 463         * configure: Regenerate.
 464
 465 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 466
 467         * configure: Regenerate.
 468
 469 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 470
 471         * configure: Regenerate.
 472
 473 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 474
 475         * config.in, configure: Regenerate.
 476
 477 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 478
 479         * interp.c (sim_create_inferior): Mark argv and env const.
 480         (sim_open): Mark argv const.
 481
 482 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 483
 484         * interp.c: Delete dis-asm.h include.
 485         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 486         (sim_create_inferior): Delete disassemble init logic.
 487         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 488         (sim_open): Delete sim_add_option_table call.
 489         * memory.c (mem_error): Delete disas check.
 490         * simulator.c: Delete dis-asm.h include.
 491         (disas): Delete.
 492         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 493         (HALT_NYI): Likewise.
 494         (handle_halt): Delete disas call.
 495         (aarch64_step): Replace disas logic with TRACE_DISASM.
 496         * simulator.h: Delete dis-asm.h include.
 497         (aarch64_print_insn): Delete.
 498
 499 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 500
 501         * simulator.c (MAX, MIN): Delete.
 502         (do_vec_maxv): Change MAX to max and MIN to min.
 503         (do_vec_fminmaxV): Likewise.
 504
 505 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 506
 507         * simulator.c: Remove syscall.h include.
 508
 509 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 510
 511         * configure: Regenerate.
 512
 513 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 514
 515         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 516         * configure: Regenerate.
 517
 518 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 519
 520         * configure: Regenerate.
 521
 522 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 523
 524         * interp.c (sim_dis_read): Change private_data to application_data.
 525         (sim_create_inferior): Likewise.
 526
 527 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 528
 529         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 530
 531 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 532
 533         * config.in, configure: Regenerate.
 534
 535 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 536
 537         * interp.c (sim_create_inferior): Update comment and argv check.
 538
 539 2015-12-14  Nick Clifton  <nickc@redhat.com>
 540
 541         * simulator.c (system_get): New function.  Provides read
 542         access to the dczid system register.
 543         (do_mrs): New function - implements the MRS instruction.
 544         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 545         unimplemented system instructions.
 546
 547 2015-11-24  Nick Clifton  <nickc@redhat.com>
 548
 549         * configure.ac: New configure template.
 550         * aclocal.m4: Generate.
 551         * config.in: Generate.
 552         * configure: Generate.
 553         * cpustate.c: New file - functions for accessing AArch64 registers.
 554         * cpustate.h: New header.
 555         * decode.h: New header.
 556         * interp.c: New file - interface between GDB and simulator.
 557         * Makefile.in: New makefile template.
 558         * memory.c: New file - functions for simulating aarch64 memory
 559         accesses.
 560         * memory.h: New header.
 561         * sim-main.h: New header.
 562         * simulator.c: New file - aarch64 simulator functions.
 563         * simulator.h: New header.