sim/aarch64/ChangeLog

   1 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
   4         * aclocal.m4, configure: Regenerate.
   5
   6 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
   7
   8         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
   9         * aclocal.m4, configure: Regenerate.
  10
  11 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
  12
  13         * configure: Regenerate.
  14
  15 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
  16
  17         * config.in, configure: Regenerate.
  18
  19 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
  20
  21         * configure: Regenerate.
  22
  23 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
  24
  25         * configure: Regenerate.
  26
  27 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
  28
  29         * configure: Regenerate.
  30
  31 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
  32
  33         PR sim/25318
  34         * simulator.c (blr): Read destination register before calling
  35         aarch64_save_LR.
  36
  37 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
  38
  39         * cpustate.c: Add 'libiberty.h' include.
  40         * interp.c: Add 'sim-assert.h' include.
  41
  42 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
  43
  44         * configure: Regenerate.
  45
  46 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
  47
  48         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
  49         registers based on structure size.
  50         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
  51         (LD1_1): Replace with call to vec_load.
  52         (vec_store): Add new M argument.  Rewrite to iterate over registers
  53         based on structure size.
  54         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
  55         (ST1_1): Replace with call to vec_store.
  56
  57 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
  58
  59         * simulator.c (do_vec_FCVTL): New.
  60         (do_vec_op1): Call do_vec_FCVTL.
  61
  62         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
  63         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
  64         (do_scalar_vec): Add calls to new functions.
  65
  66 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
  67
  68         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
  69         flag check.
  70
  71 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
  72
  73         * simulator.c (mul64hi): Shift carry left by 32.
  74         (smulh): Change signum to negate.  If negate, invert result, and add
  75         carry bit if low part of multiply result is zero.
  76
  77 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
  78
  79         * simulator.c (do_vec_SMOV_into_scalar): New.
  80         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
  81         Rewritten.
  82         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
  83         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
  84         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
  85         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  86
  87         * simulator.c (popcount): New.
  88         (do_vec_CNT): New.
  89         (do_vec_op1): Add do_vec_CNT call.
  90
  91 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  92
  93         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  94         with type set to input type size.
  95         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  96
  97 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  98
  99         * simulator.c (do_vec_MLA): Rewrite switch body.
 100
 101         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
 102         2.  Move test_false if inside loop.  Fix logic for computing result
 103         stored to vd.
 104
 105         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
 106         (do_vec_LDn_single, do_vec_STn_single): New.
 107         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
 108         loop over nregs using new var n.  Add n times size to address in loop.
 109         Add n to vd in loop.
 110         (do_vec_load_store): Add comment for instruction bit 24.  New var
 111         single to hold instruction bit 24.  Add new code to use single.  Move
 112         ldnr support inside single if statements.  Fix ldnr register counts
 113         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 114
 115 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 116
 117         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 118
 119 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 120
 121         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 122         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 123         case 3, call HALT_UNALLOC unconditionally.
 124         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 125         i + 2.  Delete if on bias, change index to i + bias * X.
 126
 127 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 128
 129         * simulator.c (do_vec_UZP): Rewrite.
 130
 131 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 132
 133         * cpustate.c: Include math.h.
 134         (aarch64_set_FP_float): Use signbit to check for signed zero.
 135         (aarch64_set_FP_double): Likewise.
 136         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 137         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 138         args same size as third arg.
 139         (fmaxnm): Use isnan instead of fpclassify.
 140         (fminnm, dmaxnm, dminnm): Likewise.
 141         (do_vec_MLS): Reverse order of subtraction operands.
 142         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 143         aarch64_get_FP_float to get source register contents.
 144         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 145         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 146         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 147         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 148         raise_exception calls.
 149
 150 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 151
 152         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 153         Add comment to document NaN issue.
 154         (set_flags_for_double_compare): Likewise.
 155
 156 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 157
 158         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 159         (set_flags_for_add64): Replace with a modified copy of
 160         set_flags_for_sub64.
 161
 162 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 163
 164         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 165         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 166
 167 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 168
 169         * simulator.c (fsturs): Switch use of rn and st variables.
 170         (fsturd, fsturq): Likewise
 171
 172 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 173
 174         * interp.c: Include bfd.h.
 175         (symcount, symtab, aarch64_get_sym_value): Delete.
 176         (remove_useless_symbols): Change count type to long.
 177         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 178         and symtab local variables.
 179         (sim_create_inferior): Delete storage.  Replace symbol code
 180         with a call to trace_load_symbols.
 181         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 182         includes.
 183         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 184         trace_sym_value.
 185         * memory.h: Delete bfd.h include.
 186         (mem_add_blk): Delete unused prototype.
 187         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 188         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 189         (aarch64_get_sym_value): Delete.
 190
 191 2016-08-12  Nick Clifton  <nickc@redhat.com>
 192
 193         * simulator.c (aarch64_step): Revert pervious delta.
 194         (aarch64_run): Call sim_events_tick after each
 195         instruction is simulated, and if necessary call
 196         sim_events_process.
 197         * simulator.h: Revert previous delta.
 198
 199 2016-08-11  Nick Clifton  <nickc@redhat.com>
 200
 201         * interp.c (sim_create_inferior): Allow for being called with a
 202         NULL abfd parameter.  If a bfd is provided, initialise the sim
 203         with that start address.
 204         * simulator.c (HALT_NYI): Just print out the numeric value of the
 205         instruction when not tracing.
 206         (aarch64_step): Change from static to global.
 207         * simulator.h: Add a prototype for aarch64_step().
 208
 209 2016-07-27  Alan Modra  <amodra@gmail.com>
 210
 211         * memory.c: Don't include libbfd.h.
 212
 213 2016-07-21  Nick Clifton  <nickc@redhat.com>
 214
 215         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 216
 217 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 218
 219         * cpustate.h: Include config.h.
 220         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 221         use anonymous structs to align members.
 222         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 223         endian_le2h_4 to read instruction from pc.
 224
 225 2016-05-06  Nick Clifton  <nickc@redhat.com>
 226
 227         * simulator.c (do_FMLA_by_element): New function.
 228         (do_vec_op2): Call it.
 229
 230 2016-04-27  Nick Clifton  <nickc@redhat.com>
 231
 232         * simulator.c: Add TRACE_DECODE statements to all emulation
 233         functions.
 234
 235 2016-03-30  Nick Clifton  <nickc@redhat.com>
 236
 237         * cpustate.c (aarch64_set_reg_s32): New function.
 238         (aarch64_set_reg_u32): New function.
 239         (aarch64_get_FP_half): Place half precision value into the correct
 240         slot of the union.
 241         (aarch64_set_FP_half): Likewise.
 242         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 243         aarch64_set_reg_u32.
 244         * memory.c (FETCH_FUNC): Cast the read value to the access type
 245         before converting it to the return type.  Rename to FETCH_FUNC64.
 246         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 247         accesses.  Use for 32-bit memory access functions.
 248         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 249         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 250         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 251         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 252         (ldrh32_abs): Store 32 bit value not 64-bits.
 253         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 254         (do_vec_MOV_immediate): Fix computation of val.
 255         (do_vec_MVNI): Likewise.
 256         (DO_VEC_WIDENING_MUL): New macro.
 257         (do_vec_mull): Use new macro.
 258         (do_vec_mul): Use new macro.
 259         (do_vec_MLA): Read values before writing.
 260         (do_vec_xtl): Likewise.
 261         (do_vec_SSHL): Select correct shift value.
 262         (do_vec_USHL): Likewise.
 263         (do_scalar_UCVTF): New function.
 264         (do_scalar_vec): Call new function.
 265         (store_pair_u64): Treat reads of SP as reads of XZR.
 266
 267 2016-03-29  Nick Clifton  <nickc@redhat.com>
 268
 269         * cpustate.c: Remove space after asterisk in function parameters.
 270         * decode.h (greg): Delete unused function.
 271         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 272         * simulator.c: Use INSTR macro in more places.
 273         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 274         Remove extraneous whitespace.
 275
 276 2016-03-23  Nick Clifton  <nickc@redhat.com>
 277
 278         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 279         register as a half precision floating point number.
 280         (aarch64_set_FP_half): New function.  Similar, but for setting
 281         a half precision register.
 282         (aarch64_get_thread_id): New function.  Returns the value of the
 283         CPU's TPIDR register.
 284         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 285         floating point control register.
 286         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 287         register.
 288         * cpustate.h: Add prototypes for new functions.
 289         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 290         * memory.c: Use unaligned core access functions for all memory
 291         reads and writes.
 292         * simulator.c (HALT_NYI): Generate an error message if tracing
 293         will not tell the user why the simulator is halting.
 294         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 295         (INSTR): New time-saver macro.
 296         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 297         offset.
 298         (fldrh_abs): New function.  Likewise for 16-bit values.
 299         (do_vec_SSHL): Allow for negative shift values.
 300         (do_vec_USHL): Likewise.
 301         (do_vec_SHL): Correct computation of shift amount.
 302         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 303         shifts and computation of shift value.
 304         (clz): New function.  Counts leading zero bits.
 305         (do_vec_CLZ): New function.  Implements CLZ (vector).
 306         (do_vec_MOV_element): Call do_vec_CLZ.
 307         (dexSimpleFPCondCompare): Implement.
 308         (do_FCVT_half_to_single): New function.  Implements one of the
 309         FCVT operations.
 310         (do_FCVT_half_to_double): New function.  Likewise.
 311         (do_FCVT_single_to_half): New function.  Likewise.
 312         (do_FCVT_double_to_half): New function.  Likewise.
 313         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 314         (do_scalar_SHL): Handle negative shifts.
 315         (do_scalar_shift): Handle SSHR.
 316         (do_scalar_USHL): New function.
 317         (do_double_add): Simplify to just performing a double precision
 318         add operation.  Move remaining code into...
 319         (do_scalar_vec): ... New function.
 320         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 321         functions.
 322         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 323         registers.
 324         (system_set): New function.
 325         (do_MSR_immediate): New function.  Stub for now.
 326         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 327         instruction.
 328         (do_SYS): New function.  Stub for now,
 329         (dexSystem): Call new functions.
 330
 331 2016-03-18  Nick Clifton  <nickc@redhat.com>
 332
 333         * cpustate.c: Remove spurious spaces from TRACE strings.
 334         Print hex equivalents of floats and doubles.
 335         Check element number against array size when accessing vector
 336         registers.
 337         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 338         element index.
 339         (SET_VEC_ELEMENT): Likewise.
 340         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 341
 342         * memory.c: Trace memory reads when --trace-memory is enabled.
 343         Remove float and double load and store functions.
 344         * memory.h (aarch64_get_mem_float): Delete prototype.
 345         (aarch64_get_mem_double): Likewise.
 346         (aarch64_set_mem_float): Likewise.
 347         (aarch64_set_mem_double): Likewise.
 348         * simulator (IS_SET): Always return either 0 or 1.
 349         (IS_CLEAR): Likewise.
 350         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 351         and doubles using 64-bit memory accesses.
 352         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 353         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 354         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 355         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 356         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 357         (do_vec_MUL_by_element): New function.
 358         (do_vec_op2): Call do_vec_MUL_by_element.
 359         (do_scalar_NEG): New function.
 360         (do_double_add): Call do_scalar_NEG.
 361
 362 2016-03-03  Nick Clifton  <nickc@redhat.com>
 363
 364         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 365         (CondCompare): Swap interpretation of bit 30.
 366         (DO_ADDP): Delete macro.
 367         (do_vec_ADDP): Copy source registers before starting to update
 368         destination register.
 369         (do_vec_FADDP): Likewise.
 370         (do_vec_load_store): Fix computation of sizeof_operation.
 371         (rbit64): Fix type of constant.
 372         (aarch64_step): When displaying insn value, display all 32 bits.
 373
 374 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 375
 376         * config.in, configure: Regenerate.
 377
 378 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 379
 380         * configure: Regenerate.
 381
 382 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 383
 384         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 385         * configure: Regenerate.
 386
 387 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 388
 389         * configure: Regenerate.
 390
 391 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 392
 393         * configure: Regenerate.
 394
 395 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 396
 397         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 398         * configure: Regenerate.
 399
 400 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 401
 402         * configure: Regenerate.
 403
 404 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 405
 406         * configure: Regenerate.
 407
 408 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 409
 410         * config.in, configure: Regenerate.
 411
 412 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 413
 414         * interp.c (sim_create_inferior): Mark argv and env const.
 415         (sim_open): Mark argv const.
 416
 417 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 418
 419         * interp.c: Delete dis-asm.h include.
 420         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 421         (sim_create_inferior): Delete disassemble init logic.
 422         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 423         (sim_open): Delete sim_add_option_table call.
 424         * memory.c (mem_error): Delete disas check.
 425         * simulator.c: Delete dis-asm.h include.
 426         (disas): Delete.
 427         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 428         (HALT_NYI): Likewise.
 429         (handle_halt): Delete disas call.
 430         (aarch64_step): Replace disas logic with TRACE_DISASM.
 431         * simulator.h: Delete dis-asm.h include.
 432         (aarch64_print_insn): Delete.
 433
 434 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 435
 436         * simulator.c (MAX, MIN): Delete.
 437         (do_vec_maxv): Change MAX to max and MIN to min.
 438         (do_vec_fminmaxV): Likewise.
 439
 440 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 441
 442         * simulator.c: Remove syscall.h include.
 443
 444 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 445
 446         * configure: Regenerate.
 447
 448 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 449
 450         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 451         * configure: Regenerate.
 452
 453 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 454
 455         * configure: Regenerate.
 456
 457 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 458
 459         * interp.c (sim_dis_read): Change private_data to application_data.
 460         (sim_create_inferior): Likewise.
 461
 462 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 463
 464         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 465
 466 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 467
 468         * config.in, configure: Regenerate.
 469
 470 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 471
 472         * interp.c (sim_create_inferior): Update comment and argv check.
 473
 474 2015-12-14  Nick Clifton  <nickc@redhat.com>
 475
 476         * simulator.c (system_get): New function.  Provides read
 477         access to the dczid system register.
 478         (do_mrs): New function - implements the MRS instruction.
 479         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 480         unimplemented system instructions.
 481
 482 2015-11-24  Nick Clifton  <nickc@redhat.com>
 483
 484         * configure.ac: New configure template.
 485         * aclocal.m4: Generate.
 486         * config.in: Generate.
 487         * configure: Generate.
 488         * cpustate.c: New file - functions for accessing AArch64 registers.
 489         * cpustate.h: New header.
 490         * decode.h: New header.
 491         * interp.c: New file - interface between GDB and simulator.
 492         * Makefile.in: New makefile template.
 493         * memory.c: New file - functions for simulating aarch64 memory
 494         accesses.
 495         * memory.h: New header.
 496         * sim-main.h: New header.
 497         * simulator.c: New file - aarch64 simulator functions.
 498         * simulator.h: New header.