sim/aarch64/ChangeLog

   1 2021-06-20  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * configure.ac (SIM_AC_COMMON): Delete.
   4         * aclocal.m4, configure: Regenerate.
   5
   6 2021-06-20  Mike Frysinger  <vapier@gentoo.org>
   7
   8         * aclocal.m4: Regenerate.
   9         * configure: Regenerate.
  10
  11 2021-06-19  Mike Frysinger  <vapier@gentoo.org>
  12
  13         * aclocal.m4: Regenerate.
  14         * configure: Regenerate.
  15
  16 2021-06-19  Mike Frysinger  <vapier@gentoo.org>
  17
  18         * configure: Regenerate.
  19
  20 2021-06-18  Mike Frysinger  <vapier@gentoo.org>
  21
  22         * aclocal.m4, configure: Regenerate.
  23
  24 2021-06-18  Mike Frysinger  <vapier@gentoo.org>
  25
  26         * configure: Regenerate.
  27
  28 2021-06-18  Mike Frysinger  <vapier@gentoo.org>
  29
  30         * cpustate.c: Include sim-signal.h.
  31         * memory.c, simulator.c: Likewise.
  32
  33 2021-06-17  Mike Frysinger  <vapier@gentoo.org>
  34
  35         * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
  36         * aclocal.m4, configure: Regenerate.
  37
  38 2021-06-16  Mike Frysinger  <vapier@gentoo.org>
  39
  40         * configure: Regenerate.
  41
  42 2021-06-16  Mike Frysinger  <vapier@gentoo.org>
  43
  44         * configure: Regenerate.
  45         * config.in: Removed.
  46
  47 2021-06-15  Mike Frysinger  <vapier@gentoo.org>
  48
  49         * config.in, configure: Regenerate.
  50
  51 2021-06-14  Mike Frysinger  <vapier@gentoo.org>
  52
  53         * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
  54         * configure: Regenerate.
  55
  56 2021-06-12  Mike Frysinger  <vapier@gentoo.org>
  57
  58         * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
  59         * interp.c (sim_open): Set current_alignment.
  60
  61 2021-06-12  Mike Frysinger  <vapier@gentoo.org>
  62
  63         * aclocal.m4, config.in, configure: Regenerate.
  64
  65 2021-06-12  Mike Frysinger  <vapier@gentoo.org>
  66
  67         * config.in, configure: Regenerate.
  68
  69 2021-05-17  Mike Frysinger  <vapier@gentoo.org>
  70
  71         * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
  72
  73 2021-05-17  Mike Frysinger  <vapier@gentoo.org>
  74
  75         * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
  76         (struct sim_state): Delete.
  77
  78 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
  79
  80         * cpustate.c: Include defs.h.
  81         * interp.c: Replace config.h include with defs.h.
  82         * memory.c, simulator.c: Likewise.
  83         * cpustate.h, simulator.h: Delete config.h include.
  84
  85 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
  86
  87         * config.in, configure: Regenerate.
  88
  89 2021-05-14  Mike Frysinger  <vapier@gentoo.org>
  90
  91         * cpustate.h: Update include path.
  92         * interp.c: Likewise.
  93
  94 2021-05-04  Mike Frysinger  <vapier@gentoo.org>
  95
  96         * configure: Regenerate.
  97
  98 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  99
 100         * config.in, configure: Regenerate.
 101
 102 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
 103
 104         * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
 105         (aarch64_set_FP_double, aarch64_set_FP_long_double,
 106         aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
 107
 108 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
 109
 110         * simulator.c (do_fcvtzu): Change UL to ULL.
 111
 112 2021-04-26  Mike Frysinger  <vapier@gentoo.org>
 113
 114         * aclocal.m4, config.in, configure: Regenerate.
 115
 116 2021-04-22  Tom Tromey  <tom@tromey.com>
 117
 118         * configure, config.in: Rebuild.
 119
 120 2021-04-22  Tom Tromey  <tom@tromey.com>
 121
 122         * configure: Rebuild.
 123
 124 2021-04-21  Mike Frysinger  <vapier@gentoo.org>
 125
 126         * aclocal.m4: Regenerate.
 127
 128 2021-04-21  Simon Marchi  <simon.marchi@polymtl.ca>
 129
 130         * configure: Regenerate.
 131
 132 2021-04-18  Mike Frysinger  <vapier@gentoo.org>
 133
 134         * configure: Regenerate.
 135
 136 2021-04-12  Mike Frysinger  <vapier@gentoo.org>
 137
 138         * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
 139
 140 2021-04-07  Jim Wilson  <jimw@sifive.com>
 141
 142         PR sim/27483
 143         * simulator.c (set_flags_for_add32): Compare uresult against
 144         itself.  Compare sresult against itself.
 145
 146 2021-04-02  Mike Frysinger  <vapier@gentoo.org>
 147
 148         * aclocal.m4, configure: Regenerate.
 149
 150 2021-02-28  Mike Frysinger  <vapier@gentoo.org>
 151
 152         * configure: Regenerate.
 153
 154 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
 155
 156         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
 157         * aclocal.m4, configure: Regenerate.
 158
 159 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
 160
 161         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
 162         * aclocal.m4, configure: Regenerate.
 163
 164 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
 165
 166         * configure: Regenerate.
 167
 168 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
 169
 170         * config.in, configure: Regenerate.
 171
 172 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
 173
 174         * configure: Regenerate.
 175
 176 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
 177
 178         * configure: Regenerate.
 179
 180 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
 181
 182         * configure: Regenerate.
 183
 184 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
 185
 186         PR sim/25318
 187         * simulator.c (blr): Read destination register before calling
 188         aarch64_save_LR.
 189
 190 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
 191
 192         * cpustate.c: Add 'libiberty.h' include.
 193         * interp.c: Add 'sim-assert.h' include.
 194
 195 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
 196
 197         * configure: Regenerate.
 198
 199 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
 200
 201         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
 202         registers based on structure size.
 203         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
 204         (LD1_1): Replace with call to vec_load.
 205         (vec_store): Add new M argument.  Rewrite to iterate over registers
 206         based on structure size.
 207         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
 208         (ST1_1): Replace with call to vec_store.
 209
 210 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
 211
 212         * simulator.c (do_vec_FCVTL): New.
 213         (do_vec_op1): Call do_vec_FCVTL.
 214
 215         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
 216         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
 217         (do_scalar_vec): Add calls to new functions.
 218
 219 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
 220
 221         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
 222         flag check.
 223
 224 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
 225
 226         * simulator.c (mul64hi): Shift carry left by 32.
 227         (smulh): Change signum to negate.  If negate, invert result, and add
 228         carry bit if low part of multiply result is zero.
 229
 230 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
 231
 232         * simulator.c (do_vec_SMOV_into_scalar): New.
 233         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
 234         Rewritten.
 235         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
 236         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
 237         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
 238         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
 239
 240         * simulator.c (popcount): New.
 241         (do_vec_CNT): New.
 242         (do_vec_op1): Add do_vec_CNT call.
 243
 244 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
 245
 246         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
 247         with type set to input type size.
 248         (do_vec_xtl): Change bias from 3 to 4 for byte case.
 249
 250 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
 251
 252         * simulator.c (do_vec_MLA): Rewrite switch body.
 253
 254         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
 255         2.  Move test_false if inside loop.  Fix logic for computing result
 256         stored to vd.
 257
 258         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
 259         (do_vec_LDn_single, do_vec_STn_single): New.
 260         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
 261         loop over nregs using new var n.  Add n times size to address in loop.
 262         Add n to vd in loop.
 263         (do_vec_load_store): Add comment for instruction bit 24.  New var
 264         single to hold instruction bit 24.  Add new code to use single.  Move
 265         ldnr support inside single if statements.  Fix ldnr register counts
 266         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 267
 268 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 269
 270         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 271
 272 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 273
 274         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 275         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 276         case 3, call HALT_UNALLOC unconditionally.
 277         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 278         i + 2.  Delete if on bias, change index to i + bias * X.
 279
 280 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 281
 282         * simulator.c (do_vec_UZP): Rewrite.
 283
 284 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 285
 286         * cpustate.c: Include math.h.
 287         (aarch64_set_FP_float): Use signbit to check for signed zero.
 288         (aarch64_set_FP_double): Likewise.
 289         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 290         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 291         args same size as third arg.
 292         (fmaxnm): Use isnan instead of fpclassify.
 293         (fminnm, dmaxnm, dminnm): Likewise.
 294         (do_vec_MLS): Reverse order of subtraction operands.
 295         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 296         aarch64_get_FP_float to get source register contents.
 297         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 298         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 299         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 300         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 301         raise_exception calls.
 302
 303 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 304
 305         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 306         Add comment to document NaN issue.
 307         (set_flags_for_double_compare): Likewise.
 308
 309 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 310
 311         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 312         (set_flags_for_add64): Replace with a modified copy of
 313         set_flags_for_sub64.
 314
 315 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 316
 317         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 318         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 319
 320 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 321
 322         * simulator.c (fsturs): Switch use of rn and st variables.
 323         (fsturd, fsturq): Likewise
 324
 325 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 326
 327         * interp.c: Include bfd.h.
 328         (symcount, symtab, aarch64_get_sym_value): Delete.
 329         (remove_useless_symbols): Change count type to long.
 330         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 331         and symtab local variables.
 332         (sim_create_inferior): Delete storage.  Replace symbol code
 333         with a call to trace_load_symbols.
 334         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 335         includes.
 336         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 337         trace_sym_value.
 338         * memory.h: Delete bfd.h include.
 339         (mem_add_blk): Delete unused prototype.
 340         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 341         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 342         (aarch64_get_sym_value): Delete.
 343
 344 2016-08-12  Nick Clifton  <nickc@redhat.com>
 345
 346         * simulator.c (aarch64_step): Revert pervious delta.
 347         (aarch64_run): Call sim_events_tick after each
 348         instruction is simulated, and if necessary call
 349         sim_events_process.
 350         * simulator.h: Revert previous delta.
 351
 352 2016-08-11  Nick Clifton  <nickc@redhat.com>
 353
 354         * interp.c (sim_create_inferior): Allow for being called with a
 355         NULL abfd parameter.  If a bfd is provided, initialise the sim
 356         with that start address.
 357         * simulator.c (HALT_NYI): Just print out the numeric value of the
 358         instruction when not tracing.
 359         (aarch64_step): Change from static to global.
 360         * simulator.h: Add a prototype for aarch64_step().
 361
 362 2016-07-27  Alan Modra  <amodra@gmail.com>
 363
 364         * memory.c: Don't include libbfd.h.
 365
 366 2016-07-21  Nick Clifton  <nickc@redhat.com>
 367
 368         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 369
 370 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 371
 372         * cpustate.h: Include config.h.
 373         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 374         use anonymous structs to align members.
 375         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 376         endian_le2h_4 to read instruction from pc.
 377
 378 2016-05-06  Nick Clifton  <nickc@redhat.com>
 379
 380         * simulator.c (do_FMLA_by_element): New function.
 381         (do_vec_op2): Call it.
 382
 383 2016-04-27  Nick Clifton  <nickc@redhat.com>
 384
 385         * simulator.c: Add TRACE_DECODE statements to all emulation
 386         functions.
 387
 388 2016-03-30  Nick Clifton  <nickc@redhat.com>
 389
 390         * cpustate.c (aarch64_set_reg_s32): New function.
 391         (aarch64_set_reg_u32): New function.
 392         (aarch64_get_FP_half): Place half precision value into the correct
 393         slot of the union.
 394         (aarch64_set_FP_half): Likewise.
 395         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 396         aarch64_set_reg_u32.
 397         * memory.c (FETCH_FUNC): Cast the read value to the access type
 398         before converting it to the return type.  Rename to FETCH_FUNC64.
 399         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 400         accesses.  Use for 32-bit memory access functions.
 401         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 402         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 403         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 404         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 405         (ldrh32_abs): Store 32 bit value not 64-bits.
 406         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 407         (do_vec_MOV_immediate): Fix computation of val.
 408         (do_vec_MVNI): Likewise.
 409         (DO_VEC_WIDENING_MUL): New macro.
 410         (do_vec_mull): Use new macro.
 411         (do_vec_mul): Use new macro.
 412         (do_vec_MLA): Read values before writing.
 413         (do_vec_xtl): Likewise.
 414         (do_vec_SSHL): Select correct shift value.
 415         (do_vec_USHL): Likewise.
 416         (do_scalar_UCVTF): New function.
 417         (do_scalar_vec): Call new function.
 418         (store_pair_u64): Treat reads of SP as reads of XZR.
 419
 420 2016-03-29  Nick Clifton  <nickc@redhat.com>
 421
 422         * cpustate.c: Remove space after asterisk in function parameters.
 423         * decode.h (greg): Delete unused function.
 424         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 425         * simulator.c: Use INSTR macro in more places.
 426         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 427         Remove extraneous whitespace.
 428
 429 2016-03-23  Nick Clifton  <nickc@redhat.com>
 430
 431         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 432         register as a half precision floating point number.
 433         (aarch64_set_FP_half): New function.  Similar, but for setting
 434         a half precision register.
 435         (aarch64_get_thread_id): New function.  Returns the value of the
 436         CPU's TPIDR register.
 437         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 438         floating point control register.
 439         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 440         register.
 441         * cpustate.h: Add prototypes for new functions.
 442         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 443         * memory.c: Use unaligned core access functions for all memory
 444         reads and writes.
 445         * simulator.c (HALT_NYI): Generate an error message if tracing
 446         will not tell the user why the simulator is halting.
 447         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 448         (INSTR): New time-saver macro.
 449         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 450         offset.
 451         (fldrh_abs): New function.  Likewise for 16-bit values.
 452         (do_vec_SSHL): Allow for negative shift values.
 453         (do_vec_USHL): Likewise.
 454         (do_vec_SHL): Correct computation of shift amount.
 455         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 456         shifts and computation of shift value.
 457         (clz): New function.  Counts leading zero bits.
 458         (do_vec_CLZ): New function.  Implements CLZ (vector).
 459         (do_vec_MOV_element): Call do_vec_CLZ.
 460         (dexSimpleFPCondCompare): Implement.
 461         (do_FCVT_half_to_single): New function.  Implements one of the
 462         FCVT operations.
 463         (do_FCVT_half_to_double): New function.  Likewise.
 464         (do_FCVT_single_to_half): New function.  Likewise.
 465         (do_FCVT_double_to_half): New function.  Likewise.
 466         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 467         (do_scalar_SHL): Handle negative shifts.
 468         (do_scalar_shift): Handle SSHR.
 469         (do_scalar_USHL): New function.
 470         (do_double_add): Simplify to just performing a double precision
 471         add operation.  Move remaining code into...
 472         (do_scalar_vec): ... New function.
 473         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 474         functions.
 475         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 476         registers.
 477         (system_set): New function.
 478         (do_MSR_immediate): New function.  Stub for now.
 479         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 480         instruction.
 481         (do_SYS): New function.  Stub for now,
 482         (dexSystem): Call new functions.
 483
 484 2016-03-18  Nick Clifton  <nickc@redhat.com>
 485
 486         * cpustate.c: Remove spurious spaces from TRACE strings.
 487         Print hex equivalents of floats and doubles.
 488         Check element number against array size when accessing vector
 489         registers.
 490         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 491         element index.
 492         (SET_VEC_ELEMENT): Likewise.
 493         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 494
 495         * memory.c: Trace memory reads when --trace-memory is enabled.
 496         Remove float and double load and store functions.
 497         * memory.h (aarch64_get_mem_float): Delete prototype.
 498         (aarch64_get_mem_double): Likewise.
 499         (aarch64_set_mem_float): Likewise.
 500         (aarch64_set_mem_double): Likewise.
 501         * simulator (IS_SET): Always return either 0 or 1.
 502         (IS_CLEAR): Likewise.
 503         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 504         and doubles using 64-bit memory accesses.
 505         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 506         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 507         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 508         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 509         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 510         (do_vec_MUL_by_element): New function.
 511         (do_vec_op2): Call do_vec_MUL_by_element.
 512         (do_scalar_NEG): New function.
 513         (do_double_add): Call do_scalar_NEG.
 514
 515 2016-03-03  Nick Clifton  <nickc@redhat.com>
 516
 517         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 518         (CondCompare): Swap interpretation of bit 30.
 519         (DO_ADDP): Delete macro.
 520         (do_vec_ADDP): Copy source registers before starting to update
 521         destination register.
 522         (do_vec_FADDP): Likewise.
 523         (do_vec_load_store): Fix computation of sizeof_operation.
 524         (rbit64): Fix type of constant.
 525         (aarch64_step): When displaying insn value, display all 32 bits.
 526
 527 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 528
 529         * config.in, configure: Regenerate.
 530
 531 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 532
 533         * configure: Regenerate.
 534
 535 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 536
 537         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 538         * configure: Regenerate.
 539
 540 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 541
 542         * configure: Regenerate.
 543
 544 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 545
 546         * configure: Regenerate.
 547
 548 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 549
 550         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 551         * configure: Regenerate.
 552
 553 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 554
 555         * configure: Regenerate.
 556
 557 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 558
 559         * configure: Regenerate.
 560
 561 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 562
 563         * config.in, configure: Regenerate.
 564
 565 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 566
 567         * interp.c (sim_create_inferior): Mark argv and env const.
 568         (sim_open): Mark argv const.
 569
 570 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 571
 572         * interp.c: Delete dis-asm.h include.
 573         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 574         (sim_create_inferior): Delete disassemble init logic.
 575         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 576         (sim_open): Delete sim_add_option_table call.
 577         * memory.c (mem_error): Delete disas check.
 578         * simulator.c: Delete dis-asm.h include.
 579         (disas): Delete.
 580         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 581         (HALT_NYI): Likewise.
 582         (handle_halt): Delete disas call.
 583         (aarch64_step): Replace disas logic with TRACE_DISASM.
 584         * simulator.h: Delete dis-asm.h include.
 585         (aarch64_print_insn): Delete.
 586
 587 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 588
 589         * simulator.c (MAX, MIN): Delete.
 590         (do_vec_maxv): Change MAX to max and MIN to min.
 591         (do_vec_fminmaxV): Likewise.
 592
 593 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 594
 595         * simulator.c: Remove syscall.h include.
 596
 597 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 598
 599         * configure: Regenerate.
 600
 601 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 602
 603         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 604         * configure: Regenerate.
 605
 606 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 607
 608         * configure: Regenerate.
 609
 610 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 611
 612         * interp.c (sim_dis_read): Change private_data to application_data.
 613         (sim_create_inferior): Likewise.
 614
 615 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 616
 617         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 618
 619 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 620
 621         * config.in, configure: Regenerate.
 622
 623 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 624
 625         * interp.c (sim_create_inferior): Update comment and argv check.
 626
 627 2015-12-14  Nick Clifton  <nickc@redhat.com>
 628
 629         * simulator.c (system_get): New function.  Provides read
 630         access to the dczid system register.
 631         (do_mrs): New function - implements the MRS instruction.
 632         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 633         unimplemented system instructions.
 634
 635 2015-11-24  Nick Clifton  <nickc@redhat.com>
 636
 637         * configure.ac: New configure template.
 638         * aclocal.m4: Generate.
 639         * config.in: Generate.
 640         * configure: Generate.
 641         * cpustate.c: New file - functions for accessing AArch64 registers.
 642         * cpustate.h: New header.
 643         * decode.h: New header.
 644         * interp.c: New file - interface between GDB and simulator.
 645         * Makefile.in: New makefile template.
 646         * memory.c: New file - functions for simulating aarch64 memory
 647         accesses.
 648         * memory.h: New header.
 649         * sim-main.h: New header.
 650         * simulator.c: New file - aarch64 simulator functions.
 651         * simulator.h: New header.