sim/aarch64/ChangeLog

   1 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * cpustate.c: Include defs.h.
   4         * interp.c: Replace config.h include with defs.h.
   5         * memory.c, simulator.c: Likewise.
   6         * cpustate.h, simulator.h: Delete config.h include.
   7
   8 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
   9
  10         * config.in, configure: Regenerate.
  11
  12 2021-05-14  Mike Frysinger  <vapier@gentoo.org>
  13
  14         * cpustate.h: Update include path.
  15         * interp.c: Likewise.
  16
  17 2021-05-04  Mike Frysinger  <vapier@gentoo.org>
  18
  19         * configure: Regenerate.
  20
  21 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  22
  23         * config.in, configure: Regenerate.
  24
  25 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  26
  27         * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
  28         (aarch64_set_FP_double, aarch64_set_FP_long_double,
  29         aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
  30
  31 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  32
  33         * simulator.c (do_fcvtzu): Change UL to ULL.
  34
  35 2021-04-26  Mike Frysinger  <vapier@gentoo.org>
  36
  37         * aclocal.m4, config.in, configure: Regenerate.
  38
  39 2021-04-22  Tom Tromey  <tom@tromey.com>
  40
  41         * configure, config.in: Rebuild.
  42
  43 2021-04-22  Tom Tromey  <tom@tromey.com>
  44
  45         * configure: Rebuild.
  46
  47 2021-04-21  Mike Frysinger  <vapier@gentoo.org>
  48
  49         * aclocal.m4: Regenerate.
  50
  51 2021-04-21  Simon Marchi  <simon.marchi@polymtl.ca>
  52
  53         * configure: Regenerate.
  54
  55 2021-04-18  Mike Frysinger  <vapier@gentoo.org>
  56
  57         * configure: Regenerate.
  58
  59 2021-04-12  Mike Frysinger  <vapier@gentoo.org>
  60
  61         * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
  62
  63 2021-04-07  Jim Wilson  <jimw@sifive.com>
  64
  65         PR sim/27483
  66         * simulator.c (set_flags_for_add32): Compare uresult against
  67         itself.  Compare sresult against itself.
  68
  69 2021-04-02  Mike Frysinger  <vapier@gentoo.org>
  70
  71         * aclocal.m4, configure: Regenerate.
  72
  73 2021-02-28  Mike Frysinger  <vapier@gentoo.org>
  74
  75         * configure: Regenerate.
  76
  77 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
  78
  79         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
  80         * aclocal.m4, configure: Regenerate.
  81
  82 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
  83
  84         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
  85         * aclocal.m4, configure: Regenerate.
  86
  87 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
  88
  89         * configure: Regenerate.
  90
  91 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
  92
  93         * config.in, configure: Regenerate.
  94
  95 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
  96
  97         * configure: Regenerate.
  98
  99 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
 100
 101         * configure: Regenerate.
 102
 103 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
 104
 105         * configure: Regenerate.
 106
 107 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
 108
 109         PR sim/25318
 110         * simulator.c (blr): Read destination register before calling
 111         aarch64_save_LR.
 112
 113 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
 114
 115         * cpustate.c: Add 'libiberty.h' include.
 116         * interp.c: Add 'sim-assert.h' include.
 117
 118 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
 119
 120         * configure: Regenerate.
 121
 122 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
 123
 124         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
 125         registers based on structure size.
 126         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
 127         (LD1_1): Replace with call to vec_load.
 128         (vec_store): Add new M argument.  Rewrite to iterate over registers
 129         based on structure size.
 130         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
 131         (ST1_1): Replace with call to vec_store.
 132
 133 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
 134
 135         * simulator.c (do_vec_FCVTL): New.
 136         (do_vec_op1): Call do_vec_FCVTL.
 137
 138         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
 139         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
 140         (do_scalar_vec): Add calls to new functions.
 141
 142 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
 143
 144         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
 145         flag check.
 146
 147 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
 148
 149         * simulator.c (mul64hi): Shift carry left by 32.
 150         (smulh): Change signum to negate.  If negate, invert result, and add
 151         carry bit if low part of multiply result is zero.
 152
 153 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
 154
 155         * simulator.c (do_vec_SMOV_into_scalar): New.
 156         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
 157         Rewritten.
 158         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
 159         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
 160         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
 161         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
 162
 163         * simulator.c (popcount): New.
 164         (do_vec_CNT): New.
 165         (do_vec_op1): Add do_vec_CNT call.
 166
 167 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
 168
 169         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
 170         with type set to input type size.
 171         (do_vec_xtl): Change bias from 3 to 4 for byte case.
 172
 173 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
 174
 175         * simulator.c (do_vec_MLA): Rewrite switch body.
 176
 177         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
 178         2.  Move test_false if inside loop.  Fix logic for computing result
 179         stored to vd.
 180
 181         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
 182         (do_vec_LDn_single, do_vec_STn_single): New.
 183         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
 184         loop over nregs using new var n.  Add n times size to address in loop.
 185         Add n to vd in loop.
 186         (do_vec_load_store): Add comment for instruction bit 24.  New var
 187         single to hold instruction bit 24.  Add new code to use single.  Move
 188         ldnr support inside single if statements.  Fix ldnr register counts
 189         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 190
 191 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 192
 193         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 194
 195 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 196
 197         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 198         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 199         case 3, call HALT_UNALLOC unconditionally.
 200         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 201         i + 2.  Delete if on bias, change index to i + bias * X.
 202
 203 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 204
 205         * simulator.c (do_vec_UZP): Rewrite.
 206
 207 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 208
 209         * cpustate.c: Include math.h.
 210         (aarch64_set_FP_float): Use signbit to check for signed zero.
 211         (aarch64_set_FP_double): Likewise.
 212         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 213         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 214         args same size as third arg.
 215         (fmaxnm): Use isnan instead of fpclassify.
 216         (fminnm, dmaxnm, dminnm): Likewise.
 217         (do_vec_MLS): Reverse order of subtraction operands.
 218         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 219         aarch64_get_FP_float to get source register contents.
 220         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 221         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 222         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 223         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 224         raise_exception calls.
 225
 226 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 227
 228         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 229         Add comment to document NaN issue.
 230         (set_flags_for_double_compare): Likewise.
 231
 232 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 233
 234         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 235         (set_flags_for_add64): Replace with a modified copy of
 236         set_flags_for_sub64.
 237
 238 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 239
 240         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 241         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 242
 243 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 244
 245         * simulator.c (fsturs): Switch use of rn and st variables.
 246         (fsturd, fsturq): Likewise
 247
 248 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 249
 250         * interp.c: Include bfd.h.
 251         (symcount, symtab, aarch64_get_sym_value): Delete.
 252         (remove_useless_symbols): Change count type to long.
 253         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 254         and symtab local variables.
 255         (sim_create_inferior): Delete storage.  Replace symbol code
 256         with a call to trace_load_symbols.
 257         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 258         includes.
 259         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 260         trace_sym_value.
 261         * memory.h: Delete bfd.h include.
 262         (mem_add_blk): Delete unused prototype.
 263         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 264         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 265         (aarch64_get_sym_value): Delete.
 266
 267 2016-08-12  Nick Clifton  <nickc@redhat.com>
 268
 269         * simulator.c (aarch64_step): Revert pervious delta.
 270         (aarch64_run): Call sim_events_tick after each
 271         instruction is simulated, and if necessary call
 272         sim_events_process.
 273         * simulator.h: Revert previous delta.
 274
 275 2016-08-11  Nick Clifton  <nickc@redhat.com>
 276
 277         * interp.c (sim_create_inferior): Allow for being called with a
 278         NULL abfd parameter.  If a bfd is provided, initialise the sim
 279         with that start address.
 280         * simulator.c (HALT_NYI): Just print out the numeric value of the
 281         instruction when not tracing.
 282         (aarch64_step): Change from static to global.
 283         * simulator.h: Add a prototype for aarch64_step().
 284
 285 2016-07-27  Alan Modra  <amodra@gmail.com>
 286
 287         * memory.c: Don't include libbfd.h.
 288
 289 2016-07-21  Nick Clifton  <nickc@redhat.com>
 290
 291         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 292
 293 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 294
 295         * cpustate.h: Include config.h.
 296         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 297         use anonymous structs to align members.
 298         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 299         endian_le2h_4 to read instruction from pc.
 300
 301 2016-05-06  Nick Clifton  <nickc@redhat.com>
 302
 303         * simulator.c (do_FMLA_by_element): New function.
 304         (do_vec_op2): Call it.
 305
 306 2016-04-27  Nick Clifton  <nickc@redhat.com>
 307
 308         * simulator.c: Add TRACE_DECODE statements to all emulation
 309         functions.
 310
 311 2016-03-30  Nick Clifton  <nickc@redhat.com>
 312
 313         * cpustate.c (aarch64_set_reg_s32): New function.
 314         (aarch64_set_reg_u32): New function.
 315         (aarch64_get_FP_half): Place half precision value into the correct
 316         slot of the union.
 317         (aarch64_set_FP_half): Likewise.
 318         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 319         aarch64_set_reg_u32.
 320         * memory.c (FETCH_FUNC): Cast the read value to the access type
 321         before converting it to the return type.  Rename to FETCH_FUNC64.
 322         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 323         accesses.  Use for 32-bit memory access functions.
 324         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 325         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 326         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 327         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 328         (ldrh32_abs): Store 32 bit value not 64-bits.
 329         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 330         (do_vec_MOV_immediate): Fix computation of val.
 331         (do_vec_MVNI): Likewise.
 332         (DO_VEC_WIDENING_MUL): New macro.
 333         (do_vec_mull): Use new macro.
 334         (do_vec_mul): Use new macro.
 335         (do_vec_MLA): Read values before writing.
 336         (do_vec_xtl): Likewise.
 337         (do_vec_SSHL): Select correct shift value.
 338         (do_vec_USHL): Likewise.
 339         (do_scalar_UCVTF): New function.
 340         (do_scalar_vec): Call new function.
 341         (store_pair_u64): Treat reads of SP as reads of XZR.
 342
 343 2016-03-29  Nick Clifton  <nickc@redhat.com>
 344
 345         * cpustate.c: Remove space after asterisk in function parameters.
 346         * decode.h (greg): Delete unused function.
 347         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 348         * simulator.c: Use INSTR macro in more places.
 349         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 350         Remove extraneous whitespace.
 351
 352 2016-03-23  Nick Clifton  <nickc@redhat.com>
 353
 354         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 355         register as a half precision floating point number.
 356         (aarch64_set_FP_half): New function.  Similar, but for setting
 357         a half precision register.
 358         (aarch64_get_thread_id): New function.  Returns the value of the
 359         CPU's TPIDR register.
 360         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 361         floating point control register.
 362         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 363         register.
 364         * cpustate.h: Add prototypes for new functions.
 365         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 366         * memory.c: Use unaligned core access functions for all memory
 367         reads and writes.
 368         * simulator.c (HALT_NYI): Generate an error message if tracing
 369         will not tell the user why the simulator is halting.
 370         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 371         (INSTR): New time-saver macro.
 372         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 373         offset.
 374         (fldrh_abs): New function.  Likewise for 16-bit values.
 375         (do_vec_SSHL): Allow for negative shift values.
 376         (do_vec_USHL): Likewise.
 377         (do_vec_SHL): Correct computation of shift amount.
 378         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 379         shifts and computation of shift value.
 380         (clz): New function.  Counts leading zero bits.
 381         (do_vec_CLZ): New function.  Implements CLZ (vector).
 382         (do_vec_MOV_element): Call do_vec_CLZ.
 383         (dexSimpleFPCondCompare): Implement.
 384         (do_FCVT_half_to_single): New function.  Implements one of the
 385         FCVT operations.
 386         (do_FCVT_half_to_double): New function.  Likewise.
 387         (do_FCVT_single_to_half): New function.  Likewise.
 388         (do_FCVT_double_to_half): New function.  Likewise.
 389         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 390         (do_scalar_SHL): Handle negative shifts.
 391         (do_scalar_shift): Handle SSHR.
 392         (do_scalar_USHL): New function.
 393         (do_double_add): Simplify to just performing a double precision
 394         add operation.  Move remaining code into...
 395         (do_scalar_vec): ... New function.
 396         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 397         functions.
 398         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 399         registers.
 400         (system_set): New function.
 401         (do_MSR_immediate): New function.  Stub for now.
 402         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 403         instruction.
 404         (do_SYS): New function.  Stub for now,
 405         (dexSystem): Call new functions.
 406
 407 2016-03-18  Nick Clifton  <nickc@redhat.com>
 408
 409         * cpustate.c: Remove spurious spaces from TRACE strings.
 410         Print hex equivalents of floats and doubles.
 411         Check element number against array size when accessing vector
 412         registers.
 413         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 414         element index.
 415         (SET_VEC_ELEMENT): Likewise.
 416         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 417
 418         * memory.c: Trace memory reads when --trace-memory is enabled.
 419         Remove float and double load and store functions.
 420         * memory.h (aarch64_get_mem_float): Delete prototype.
 421         (aarch64_get_mem_double): Likewise.
 422         (aarch64_set_mem_float): Likewise.
 423         (aarch64_set_mem_double): Likewise.
 424         * simulator (IS_SET): Always return either 0 or 1.
 425         (IS_CLEAR): Likewise.
 426         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 427         and doubles using 64-bit memory accesses.
 428         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 429         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 430         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 431         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 432         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 433         (do_vec_MUL_by_element): New function.
 434         (do_vec_op2): Call do_vec_MUL_by_element.
 435         (do_scalar_NEG): New function.
 436         (do_double_add): Call do_scalar_NEG.
 437
 438 2016-03-03  Nick Clifton  <nickc@redhat.com>
 439
 440         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 441         (CondCompare): Swap interpretation of bit 30.
 442         (DO_ADDP): Delete macro.
 443         (do_vec_ADDP): Copy source registers before starting to update
 444         destination register.
 445         (do_vec_FADDP): Likewise.
 446         (do_vec_load_store): Fix computation of sizeof_operation.
 447         (rbit64): Fix type of constant.
 448         (aarch64_step): When displaying insn value, display all 32 bits.
 449
 450 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 451
 452         * config.in, configure: Regenerate.
 453
 454 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 455
 456         * configure: Regenerate.
 457
 458 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 459
 460         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 461         * configure: Regenerate.
 462
 463 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 464
 465         * configure: Regenerate.
 466
 467 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 468
 469         * configure: Regenerate.
 470
 471 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 472
 473         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 474         * configure: Regenerate.
 475
 476 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 477
 478         * configure: Regenerate.
 479
 480 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 481
 482         * configure: Regenerate.
 483
 484 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 485
 486         * config.in, configure: Regenerate.
 487
 488 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 489
 490         * interp.c (sim_create_inferior): Mark argv and env const.
 491         (sim_open): Mark argv const.
 492
 493 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 494
 495         * interp.c: Delete dis-asm.h include.
 496         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 497         (sim_create_inferior): Delete disassemble init logic.
 498         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 499         (sim_open): Delete sim_add_option_table call.
 500         * memory.c (mem_error): Delete disas check.
 501         * simulator.c: Delete dis-asm.h include.
 502         (disas): Delete.
 503         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 504         (HALT_NYI): Likewise.
 505         (handle_halt): Delete disas call.
 506         (aarch64_step): Replace disas logic with TRACE_DISASM.
 507         * simulator.h: Delete dis-asm.h include.
 508         (aarch64_print_insn): Delete.
 509
 510 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 511
 512         * simulator.c (MAX, MIN): Delete.
 513         (do_vec_maxv): Change MAX to max and MIN to min.
 514         (do_vec_fminmaxV): Likewise.
 515
 516 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 517
 518         * simulator.c: Remove syscall.h include.
 519
 520 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 521
 522         * configure: Regenerate.
 523
 524 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 525
 526         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 527         * configure: Regenerate.
 528
 529 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 530
 531         * configure: Regenerate.
 532
 533 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 534
 535         * interp.c (sim_dis_read): Change private_data to application_data.
 536         (sim_create_inferior): Likewise.
 537
 538 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 539
 540         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 541
 542 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 543
 544         * config.in, configure: Regenerate.
 545
 546 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 547
 548         * interp.c (sim_create_inferior): Update comment and argv check.
 549
 550 2015-12-14  Nick Clifton  <nickc@redhat.com>
 551
 552         * simulator.c (system_get): New function.  Provides read
 553         access to the dczid system register.
 554         (do_mrs): New function - implements the MRS instruction.
 555         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 556         unimplemented system instructions.
 557
 558 2015-11-24  Nick Clifton  <nickc@redhat.com>
 559
 560         * configure.ac: New configure template.
 561         * aclocal.m4: Generate.
 562         * config.in: Generate.
 563         * configure: Generate.
 564         * cpustate.c: New file - functions for accessing AArch64 registers.
 565         * cpustate.h: New header.
 566         * decode.h: New header.
 567         * interp.c: New file - interface between GDB and simulator.
 568         * Makefile.in: New makefile template.
 569         * memory.c: New file - functions for simulating aarch64 memory
 570         accesses.
 571         * memory.h: New header.
 572         * sim-main.h: New header.
 573         * simulator.c: New file - aarch64 simulator functions.
 574         * simulator.h: New header.