sim/aarch64/ChangeLog

   1 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * config.in, configure: Regenerate.
   4
   5 2021-05-14  Mike Frysinger  <vapier@gentoo.org>
   6
   7         * cpustate.h: Update include path.
   8         * interp.c: Likewise.
   9
  10 2021-05-04  Mike Frysinger  <vapier@gentoo.org>
  11
  12         * configure: Regenerate.
  13
  14 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  15
  16         * config.in, configure: Regenerate.
  17
  18 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  19
  20         * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
  21         (aarch64_set_FP_double, aarch64_set_FP_long_double,
  22         aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
  23
  24 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  25
  26         * simulator.c (do_fcvtzu): Change UL to ULL.
  27
  28 2021-04-26  Mike Frysinger  <vapier@gentoo.org>
  29
  30         * aclocal.m4, config.in, configure: Regenerate.
  31
  32 2021-04-22  Tom Tromey  <tom@tromey.com>
  33
  34         * configure, config.in: Rebuild.
  35
  36 2021-04-22  Tom Tromey  <tom@tromey.com>
  37
  38         * configure: Rebuild.
  39
  40 2021-04-21  Mike Frysinger  <vapier@gentoo.org>
  41
  42         * aclocal.m4: Regenerate.
  43
  44 2021-04-21  Simon Marchi  <simon.marchi@polymtl.ca>
  45
  46         * configure: Regenerate.
  47
  48 2021-04-18  Mike Frysinger  <vapier@gentoo.org>
  49
  50         * configure: Regenerate.
  51
  52 2021-04-12  Mike Frysinger  <vapier@gentoo.org>
  53
  54         * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
  55
  56 2021-04-07  Jim Wilson  <jimw@sifive.com>
  57
  58         PR sim/27483
  59         * simulator.c (set_flags_for_add32): Compare uresult against
  60         itself.  Compare sresult against itself.
  61
  62 2021-04-02  Mike Frysinger  <vapier@gentoo.org>
  63
  64         * aclocal.m4, configure: Regenerate.
  65
  66 2021-02-28  Mike Frysinger  <vapier@gentoo.org>
  67
  68         * configure: Regenerate.
  69
  70 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
  71
  72         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
  73         * aclocal.m4, configure: Regenerate.
  74
  75 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
  76
  77         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
  78         * aclocal.m4, configure: Regenerate.
  79
  80 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
  81
  82         * configure: Regenerate.
  83
  84 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
  85
  86         * config.in, configure: Regenerate.
  87
  88 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
  89
  90         * configure: Regenerate.
  91
  92 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
  93
  94         * configure: Regenerate.
  95
  96 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
  97
  98         * configure: Regenerate.
  99
 100 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
 101
 102         PR sim/25318
 103         * simulator.c (blr): Read destination register before calling
 104         aarch64_save_LR.
 105
 106 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
 107
 108         * cpustate.c: Add 'libiberty.h' include.
 109         * interp.c: Add 'sim-assert.h' include.
 110
 111 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
 112
 113         * configure: Regenerate.
 114
 115 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
 116
 117         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
 118         registers based on structure size.
 119         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
 120         (LD1_1): Replace with call to vec_load.
 121         (vec_store): Add new M argument.  Rewrite to iterate over registers
 122         based on structure size.
 123         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
 124         (ST1_1): Replace with call to vec_store.
 125
 126 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
 127
 128         * simulator.c (do_vec_FCVTL): New.
 129         (do_vec_op1): Call do_vec_FCVTL.
 130
 131         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
 132         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
 133         (do_scalar_vec): Add calls to new functions.
 134
 135 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
 136
 137         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
 138         flag check.
 139
 140 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
 141
 142         * simulator.c (mul64hi): Shift carry left by 32.
 143         (smulh): Change signum to negate.  If negate, invert result, and add
 144         carry bit if low part of multiply result is zero.
 145
 146 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
 147
 148         * simulator.c (do_vec_SMOV_into_scalar): New.
 149         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
 150         Rewritten.
 151         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
 152         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
 153         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
 154         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
 155
 156         * simulator.c (popcount): New.
 157         (do_vec_CNT): New.
 158         (do_vec_op1): Add do_vec_CNT call.
 159
 160 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
 161
 162         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
 163         with type set to input type size.
 164         (do_vec_xtl): Change bias from 3 to 4 for byte case.
 165
 166 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
 167
 168         * simulator.c (do_vec_MLA): Rewrite switch body.
 169
 170         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
 171         2.  Move test_false if inside loop.  Fix logic for computing result
 172         stored to vd.
 173
 174         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
 175         (do_vec_LDn_single, do_vec_STn_single): New.
 176         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
 177         loop over nregs using new var n.  Add n times size to address in loop.
 178         Add n to vd in loop.
 179         (do_vec_load_store): Add comment for instruction bit 24.  New var
 180         single to hold instruction bit 24.  Add new code to use single.  Move
 181         ldnr support inside single if statements.  Fix ldnr register counts
 182         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 183
 184 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 185
 186         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 187
 188 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 189
 190         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 191         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 192         case 3, call HALT_UNALLOC unconditionally.
 193         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 194         i + 2.  Delete if on bias, change index to i + bias * X.
 195
 196 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 197
 198         * simulator.c (do_vec_UZP): Rewrite.
 199
 200 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 201
 202         * cpustate.c: Include math.h.
 203         (aarch64_set_FP_float): Use signbit to check for signed zero.
 204         (aarch64_set_FP_double): Likewise.
 205         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 206         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 207         args same size as third arg.
 208         (fmaxnm): Use isnan instead of fpclassify.
 209         (fminnm, dmaxnm, dminnm): Likewise.
 210         (do_vec_MLS): Reverse order of subtraction operands.
 211         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 212         aarch64_get_FP_float to get source register contents.
 213         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 214         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 215         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 216         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 217         raise_exception calls.
 218
 219 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 220
 221         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 222         Add comment to document NaN issue.
 223         (set_flags_for_double_compare): Likewise.
 224
 225 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 226
 227         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 228         (set_flags_for_add64): Replace with a modified copy of
 229         set_flags_for_sub64.
 230
 231 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 232
 233         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 234         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 235
 236 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 237
 238         * simulator.c (fsturs): Switch use of rn and st variables.
 239         (fsturd, fsturq): Likewise
 240
 241 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 242
 243         * interp.c: Include bfd.h.
 244         (symcount, symtab, aarch64_get_sym_value): Delete.
 245         (remove_useless_symbols): Change count type to long.
 246         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 247         and symtab local variables.
 248         (sim_create_inferior): Delete storage.  Replace symbol code
 249         with a call to trace_load_symbols.
 250         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 251         includes.
 252         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 253         trace_sym_value.
 254         * memory.h: Delete bfd.h include.
 255         (mem_add_blk): Delete unused prototype.
 256         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 257         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 258         (aarch64_get_sym_value): Delete.
 259
 260 2016-08-12  Nick Clifton  <nickc@redhat.com>
 261
 262         * simulator.c (aarch64_step): Revert pervious delta.
 263         (aarch64_run): Call sim_events_tick after each
 264         instruction is simulated, and if necessary call
 265         sim_events_process.
 266         * simulator.h: Revert previous delta.
 267
 268 2016-08-11  Nick Clifton  <nickc@redhat.com>
 269
 270         * interp.c (sim_create_inferior): Allow for being called with a
 271         NULL abfd parameter.  If a bfd is provided, initialise the sim
 272         with that start address.
 273         * simulator.c (HALT_NYI): Just print out the numeric value of the
 274         instruction when not tracing.
 275         (aarch64_step): Change from static to global.
 276         * simulator.h: Add a prototype for aarch64_step().
 277
 278 2016-07-27  Alan Modra  <amodra@gmail.com>
 279
 280         * memory.c: Don't include libbfd.h.
 281
 282 2016-07-21  Nick Clifton  <nickc@redhat.com>
 283
 284         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 285
 286 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 287
 288         * cpustate.h: Include config.h.
 289         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 290         use anonymous structs to align members.
 291         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 292         endian_le2h_4 to read instruction from pc.
 293
 294 2016-05-06  Nick Clifton  <nickc@redhat.com>
 295
 296         * simulator.c (do_FMLA_by_element): New function.
 297         (do_vec_op2): Call it.
 298
 299 2016-04-27  Nick Clifton  <nickc@redhat.com>
 300
 301         * simulator.c: Add TRACE_DECODE statements to all emulation
 302         functions.
 303
 304 2016-03-30  Nick Clifton  <nickc@redhat.com>
 305
 306         * cpustate.c (aarch64_set_reg_s32): New function.
 307         (aarch64_set_reg_u32): New function.
 308         (aarch64_get_FP_half): Place half precision value into the correct
 309         slot of the union.
 310         (aarch64_set_FP_half): Likewise.
 311         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 312         aarch64_set_reg_u32.
 313         * memory.c (FETCH_FUNC): Cast the read value to the access type
 314         before converting it to the return type.  Rename to FETCH_FUNC64.
 315         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 316         accesses.  Use for 32-bit memory access functions.
 317         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 318         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 319         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 320         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 321         (ldrh32_abs): Store 32 bit value not 64-bits.
 322         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 323         (do_vec_MOV_immediate): Fix computation of val.
 324         (do_vec_MVNI): Likewise.
 325         (DO_VEC_WIDENING_MUL): New macro.
 326         (do_vec_mull): Use new macro.
 327         (do_vec_mul): Use new macro.
 328         (do_vec_MLA): Read values before writing.
 329         (do_vec_xtl): Likewise.
 330         (do_vec_SSHL): Select correct shift value.
 331         (do_vec_USHL): Likewise.
 332         (do_scalar_UCVTF): New function.
 333         (do_scalar_vec): Call new function.
 334         (store_pair_u64): Treat reads of SP as reads of XZR.
 335
 336 2016-03-29  Nick Clifton  <nickc@redhat.com>
 337
 338         * cpustate.c: Remove space after asterisk in function parameters.
 339         * decode.h (greg): Delete unused function.
 340         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 341         * simulator.c: Use INSTR macro in more places.
 342         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 343         Remove extraneous whitespace.
 344
 345 2016-03-23  Nick Clifton  <nickc@redhat.com>
 346
 347         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 348         register as a half precision floating point number.
 349         (aarch64_set_FP_half): New function.  Similar, but for setting
 350         a half precision register.
 351         (aarch64_get_thread_id): New function.  Returns the value of the
 352         CPU's TPIDR register.
 353         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 354         floating point control register.
 355         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 356         register.
 357         * cpustate.h: Add prototypes for new functions.
 358         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 359         * memory.c: Use unaligned core access functions for all memory
 360         reads and writes.
 361         * simulator.c (HALT_NYI): Generate an error message if tracing
 362         will not tell the user why the simulator is halting.
 363         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 364         (INSTR): New time-saver macro.
 365         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 366         offset.
 367         (fldrh_abs): New function.  Likewise for 16-bit values.
 368         (do_vec_SSHL): Allow for negative shift values.
 369         (do_vec_USHL): Likewise.
 370         (do_vec_SHL): Correct computation of shift amount.
 371         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 372         shifts and computation of shift value.
 373         (clz): New function.  Counts leading zero bits.
 374         (do_vec_CLZ): New function.  Implements CLZ (vector).
 375         (do_vec_MOV_element): Call do_vec_CLZ.
 376         (dexSimpleFPCondCompare): Implement.
 377         (do_FCVT_half_to_single): New function.  Implements one of the
 378         FCVT operations.
 379         (do_FCVT_half_to_double): New function.  Likewise.
 380         (do_FCVT_single_to_half): New function.  Likewise.
 381         (do_FCVT_double_to_half): New function.  Likewise.
 382         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 383         (do_scalar_SHL): Handle negative shifts.
 384         (do_scalar_shift): Handle SSHR.
 385         (do_scalar_USHL): New function.
 386         (do_double_add): Simplify to just performing a double precision
 387         add operation.  Move remaining code into...
 388         (do_scalar_vec): ... New function.
 389         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 390         functions.
 391         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 392         registers.
 393         (system_set): New function.
 394         (do_MSR_immediate): New function.  Stub for now.
 395         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 396         instruction.
 397         (do_SYS): New function.  Stub for now,
 398         (dexSystem): Call new functions.
 399
 400 2016-03-18  Nick Clifton  <nickc@redhat.com>
 401
 402         * cpustate.c: Remove spurious spaces from TRACE strings.
 403         Print hex equivalents of floats and doubles.
 404         Check element number against array size when accessing vector
 405         registers.
 406         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 407         element index.
 408         (SET_VEC_ELEMENT): Likewise.
 409         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 410
 411         * memory.c: Trace memory reads when --trace-memory is enabled.
 412         Remove float and double load and store functions.
 413         * memory.h (aarch64_get_mem_float): Delete prototype.
 414         (aarch64_get_mem_double): Likewise.
 415         (aarch64_set_mem_float): Likewise.
 416         (aarch64_set_mem_double): Likewise.
 417         * simulator (IS_SET): Always return either 0 or 1.
 418         (IS_CLEAR): Likewise.
 419         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 420         and doubles using 64-bit memory accesses.
 421         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 422         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 423         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 424         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 425         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 426         (do_vec_MUL_by_element): New function.
 427         (do_vec_op2): Call do_vec_MUL_by_element.
 428         (do_scalar_NEG): New function.
 429         (do_double_add): Call do_scalar_NEG.
 430
 431 2016-03-03  Nick Clifton  <nickc@redhat.com>
 432
 433         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 434         (CondCompare): Swap interpretation of bit 30.
 435         (DO_ADDP): Delete macro.
 436         (do_vec_ADDP): Copy source registers before starting to update
 437         destination register.
 438         (do_vec_FADDP): Likewise.
 439         (do_vec_load_store): Fix computation of sizeof_operation.
 440         (rbit64): Fix type of constant.
 441         (aarch64_step): When displaying insn value, display all 32 bits.
 442
 443 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 444
 445         * config.in, configure: Regenerate.
 446
 447 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 448
 449         * configure: Regenerate.
 450
 451 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 452
 453         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 454         * configure: Regenerate.
 455
 456 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 457
 458         * configure: Regenerate.
 459
 460 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 461
 462         * configure: Regenerate.
 463
 464 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 465
 466         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 467         * configure: Regenerate.
 468
 469 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 470
 471         * configure: Regenerate.
 472
 473 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 474
 475         * configure: Regenerate.
 476
 477 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 478
 479         * config.in, configure: Regenerate.
 480
 481 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 482
 483         * interp.c (sim_create_inferior): Mark argv and env const.
 484         (sim_open): Mark argv const.
 485
 486 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 487
 488         * interp.c: Delete dis-asm.h include.
 489         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 490         (sim_create_inferior): Delete disassemble init logic.
 491         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 492         (sim_open): Delete sim_add_option_table call.
 493         * memory.c (mem_error): Delete disas check.
 494         * simulator.c: Delete dis-asm.h include.
 495         (disas): Delete.
 496         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 497         (HALT_NYI): Likewise.
 498         (handle_halt): Delete disas call.
 499         (aarch64_step): Replace disas logic with TRACE_DISASM.
 500         * simulator.h: Delete dis-asm.h include.
 501         (aarch64_print_insn): Delete.
 502
 503 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 504
 505         * simulator.c (MAX, MIN): Delete.
 506         (do_vec_maxv): Change MAX to max and MIN to min.
 507         (do_vec_fminmaxV): Likewise.
 508
 509 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 510
 511         * simulator.c: Remove syscall.h include.
 512
 513 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 514
 515         * configure: Regenerate.
 516
 517 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 518
 519         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 520         * configure: Regenerate.
 521
 522 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 523
 524         * configure: Regenerate.
 525
 526 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 527
 528         * interp.c (sim_dis_read): Change private_data to application_data.
 529         (sim_create_inferior): Likewise.
 530
 531 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 532
 533         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 534
 535 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 536
 537         * config.in, configure: Regenerate.
 538
 539 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 540
 541         * interp.c (sim_create_inferior): Update comment and argv check.
 542
 543 2015-12-14  Nick Clifton  <nickc@redhat.com>
 544
 545         * simulator.c (system_get): New function.  Provides read
 546         access to the dczid system register.
 547         (do_mrs): New function - implements the MRS instruction.
 548         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 549         unimplemented system instructions.
 550
 551 2015-11-24  Nick Clifton  <nickc@redhat.com>
 552
 553         * configure.ac: New configure template.
 554         * aclocal.m4: Generate.
 555         * config.in: Generate.
 556         * configure: Generate.
 557         * cpustate.c: New file - functions for accessing AArch64 registers.
 558         * cpustate.h: New header.
 559         * decode.h: New header.
 560         * interp.c: New file - interface between GDB and simulator.
 561         * Makefile.in: New makefile template.
 562         * memory.c: New file - functions for simulating aarch64 memory
 563         accesses.
 564         * memory.h: New header.
 565         * sim-main.h: New header.
 566         * simulator.c: New file - aarch64 simulator functions.
 567         * simulator.h: New header.