1 2021-06-16 Mike Frysinger <vapier@gentoo.org>
3 * configure: Regenerate.
5 2021-06-16 Mike Frysinger <vapier@gentoo.org>
7 * configure: Regenerate.
10 2021-06-15 Mike Frysinger <vapier@gentoo.org>
12 * config.in, configure: Regenerate.
14 2021-06-14 Mike Frysinger <vapier@gentoo.org>
16 * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
17 * configure: Regenerate.
19 2021-06-12 Mike Frysinger <vapier@gentoo.org>
21 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
22 * interp.c (sim_open): Set current_alignment.
24 2021-06-12 Mike Frysinger <vapier@gentoo.org>
26 * aclocal.m4, config.in, configure: Regenerate.
28 2021-06-12 Mike Frysinger <vapier@gentoo.org>
30 * config.in, configure: Regenerate.
32 2021-05-17 Mike Frysinger <vapier@gentoo.org>
34 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
36 2021-05-17 Mike Frysinger <vapier@gentoo.org>
38 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
39 (struct sim_state): Delete.
41 2021-05-16 Mike Frysinger <vapier@gentoo.org>
43 * cpustate.c: Include defs.h.
44 * interp.c: Replace config.h include with defs.h.
45 * memory.c, simulator.c: Likewise.
46 * cpustate.h, simulator.h: Delete config.h include.
48 2021-05-16 Mike Frysinger <vapier@gentoo.org>
50 * config.in, configure: Regenerate.
52 2021-05-14 Mike Frysinger <vapier@gentoo.org>
54 * cpustate.h: Update include path.
57 2021-05-04 Mike Frysinger <vapier@gentoo.org>
59 * configure: Regenerate.
61 2021-05-01 Mike Frysinger <vapier@gentoo.org>
63 * config.in, configure: Regenerate.
65 2021-05-01 Mike Frysinger <vapier@gentoo.org>
67 * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
68 (aarch64_set_FP_double, aarch64_set_FP_long_double,
69 aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
71 2021-05-01 Mike Frysinger <vapier@gentoo.org>
73 * simulator.c (do_fcvtzu): Change UL to ULL.
75 2021-04-26 Mike Frysinger <vapier@gentoo.org>
77 * aclocal.m4, config.in, configure: Regenerate.
79 2021-04-22 Tom Tromey <tom@tromey.com>
81 * configure, config.in: Rebuild.
83 2021-04-22 Tom Tromey <tom@tromey.com>
87 2021-04-21 Mike Frysinger <vapier@gentoo.org>
89 * aclocal.m4: Regenerate.
91 2021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
93 * configure: Regenerate.
95 2021-04-18 Mike Frysinger <vapier@gentoo.org>
97 * configure: Regenerate.
99 2021-04-12 Mike Frysinger <vapier@gentoo.org>
101 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
103 2021-04-07 Jim Wilson <jimw@sifive.com>
106 * simulator.c (set_flags_for_add32): Compare uresult against
107 itself. Compare sresult against itself.
109 2021-04-02 Mike Frysinger <vapier@gentoo.org>
111 * aclocal.m4, configure: Regenerate.
113 2021-02-28 Mike Frysinger <vapier@gentoo.org>
115 * configure: Regenerate.
117 2021-02-21 Mike Frysinger <vapier@gentoo.org>
119 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
120 * aclocal.m4, configure: Regenerate.
122 2021-02-13 Mike Frysinger <vapier@gentoo.org>
124 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
125 * aclocal.m4, configure: Regenerate.
127 2021-02-06 Mike Frysinger <vapier@gentoo.org>
129 * configure: Regenerate.
131 2021-01-11 Mike Frysinger <vapier@gentoo.org>
133 * config.in, configure: Regenerate.
135 2021-01-09 Mike Frysinger <vapier@gentoo.org>
137 * configure: Regenerate.
139 2021-01-08 Mike Frysinger <vapier@gentoo.org>
141 * configure: Regenerate.
143 2021-01-04 Mike Frysinger <vapier@gentoo.org>
145 * configure: Regenerate.
147 2020-02-06 Carlo Bramini <carlo_bramini@users.sourceforge.net>
150 * simulator.c (blr): Read destination register before calling
153 2019-03-28 Andrew Burgess <andrew.burgess@embecosm.com>
155 * cpustate.c: Add 'libiberty.h' include.
156 * interp.c: Add 'sim-assert.h' include.
158 2017-09-06 John Baldwin <jhb@FreeBSD.org>
160 * configure: Regenerate.
162 2017-04-22 Jim Wilson <jim.wilson@linaro.org>
164 * simulator.c (vec_load): Add M argument. Rewrite to iterate over
165 registers based on structure size.
166 (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
167 (LD1_1): Replace with call to vec_load.
168 (vec_store): Add new M argument. Rewrite to iterate over registers
169 based on structure size.
170 (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
171 (ST1_1): Replace with call to vec_store.
173 2017-04-08 Jim Wilson <jim.wilson@linaro.org>
175 * simulator.c (do_vec_FCVTL): New.
176 (do_vec_op1): Call do_vec_FCVTL.
178 * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
179 do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
180 (do_scalar_vec): Add calls to new functions.
182 2017-03-25 Jim Wilson <jim.wilson@linaro.org>
184 * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
187 2017-03-03 Jim Wilson <jim.wilson@linaro.org>
189 * simulator.c (mul64hi): Shift carry left by 32.
190 (smulh): Change signum to negate. If negate, invert result, and add
191 carry bit if low part of multiply result is zero.
193 2017-02-25 Jim Wilson <jim.wilson@linaro.org>
195 * simulator.c (do_vec_SMOV_into_scalar): New.
196 (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
198 (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
199 (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call. Add
200 do_vec_SMOV_into_scalar call. Delete do_vec_MOV_into_scalar and
201 do_vec_UMOV calls. Add do_vec_UMOV_into_scalar call.
203 * simulator.c (popcount): New.
205 (do_vec_op1): Add do_vec_CNT call.
207 2017-02-19 Jim Wilson <jim.wilson@linaro.org>
209 * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
210 with type set to input type size.
211 (do_vec_xtl): Change bias from 3 to 4 for byte case.
213 2017-02-14 Jim Wilson <jim.wilson@linaro.org>
215 * simulator.c (do_vec_MLA): Rewrite switch body.
217 * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
218 2. Move test_false if inside loop. Fix logic for computing result
221 * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
222 (do_vec_LDn_single, do_vec_STn_single): New.
223 (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with
224 loop over nregs using new var n. Add n times size to address in loop.
226 (do_vec_load_store): Add comment for instruction bit 24. New var
227 single to hold instruction bit 24. Add new code to use single. Move
228 ldnr support inside single if statements. Fix ldnr register counts
229 inside post if statement. Change HALT_NYI calls to HALT_UNALLOC.
231 2017-01-23 Jim Wilson <jim.wilson@linaro.org>
233 * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
235 2017-01-17 Jim Wilson <jim.wilson@linaro.org>
237 * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
238 aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
239 case 3, call HALT_UNALLOC unconditionally.
240 (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
241 i + 2. Delete if on bias, change index to i + bias * X.
243 2017-01-09 Jim Wilson <jim.wilson@linaro.org>
245 * simulator.c (do_vec_UZP): Rewrite.
247 2017-01-04 Jim Wilson <jim.wilson@linaro.org>
249 * cpustate.c: Include math.h.
250 (aarch64_set_FP_float): Use signbit to check for signed zero.
251 (aarch64_set_FP_double): Likewise.
252 * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
253 (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
254 args same size as third arg.
255 (fmaxnm): Use isnan instead of fpclassify.
256 (fminnm, dmaxnm, dminnm): Likewise.
257 (do_vec_MLS): Reverse order of subtraction operands.
258 (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
259 aarch64_get_FP_float to get source register contents.
260 (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
261 DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
262 DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
263 (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
264 raise_exception calls.
266 2016-12-21 Jim Wilson <jim.wilson@linaro.org>
268 * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
269 Add comment to document NaN issue.
270 (set_flags_for_double_compare): Likewise.
272 2016-12-13 Jim Wilson <jim.wilson@linaro.org>
274 * simulator.c (NEG, POS): Move before set_flags_for_add64.
275 (set_flags_for_add64): Replace with a modified copy of
278 2016-12-03 Jim Wilson <jim.wilson@linaro.org>
280 * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
281 (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
283 2016-12-01 Jim Wilson <jim.wilson@linaro.org>
285 * simulator.c (fsturs): Switch use of rn and st variables.
286 (fsturd, fsturq): Likewise
288 2016-08-15 Mike Frysinger <vapier@gentoo.org>
290 * interp.c: Include bfd.h.
291 (symcount, symtab, aarch64_get_sym_value): Delete.
292 (remove_useless_symbols): Change count type to long.
293 (aarch64_get_func): Add SIM_DESC to arg list. Add symcount
294 and symtab local variables.
295 (sim_create_inferior): Delete storage. Replace symbol code
296 with a call to trace_load_symbols.
297 * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
299 (aarch64_get_heap_start): Change aarch64_get_sym_value to
301 * memory.h: Delete bfd.h include.
302 (mem_add_blk): Delete unused prototype.
303 * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
304 * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
305 (aarch64_get_sym_value): Delete.
307 2016-08-12 Nick Clifton <nickc@redhat.com>
309 * simulator.c (aarch64_step): Revert pervious delta.
310 (aarch64_run): Call sim_events_tick after each
311 instruction is simulated, and if necessary call
313 * simulator.h: Revert previous delta.
315 2016-08-11 Nick Clifton <nickc@redhat.com>
317 * interp.c (sim_create_inferior): Allow for being called with a
318 NULL abfd parameter. If a bfd is provided, initialise the sim
319 with that start address.
320 * simulator.c (HALT_NYI): Just print out the numeric value of the
321 instruction when not tracing.
322 (aarch64_step): Change from static to global.
323 * simulator.h: Add a prototype for aarch64_step().
325 2016-07-27 Alan Modra <amodra@gmail.com>
327 * memory.c: Don't include libbfd.h.
329 2016-07-21 Nick Clifton <nickc@redhat.com>
331 * simulator.c (fsqrts): Use sqrtf rather than sqrt.
333 2016-06-30 Jim Wilson <jim.wilson@linaro.org>
335 * cpustate.h: Include config.h.
336 (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code
337 use anonymous structs to align members.
338 * simulator.c (aarch64_step): Use sim_core_read_buffer and
339 endian_le2h_4 to read instruction from pc.
341 2016-05-06 Nick Clifton <nickc@redhat.com>
343 * simulator.c (do_FMLA_by_element): New function.
344 (do_vec_op2): Call it.
346 2016-04-27 Nick Clifton <nickc@redhat.com>
348 * simulator.c: Add TRACE_DECODE statements to all emulation
351 2016-03-30 Nick Clifton <nickc@redhat.com>
353 * cpustate.c (aarch64_set_reg_s32): New function.
354 (aarch64_set_reg_u32): New function.
355 (aarch64_get_FP_half): Place half precision value into the correct
357 (aarch64_set_FP_half): Likewise.
358 * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
360 * memory.c (FETCH_FUNC): Cast the read value to the access type
361 before converting it to the return type. Rename to FETCH_FUNC64.
362 (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit
363 accesses. Use for 32-bit memory access functions.
364 * simulator.c (ldrsb_wb): Use sign extension not zero extension.
365 (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
366 (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
367 (ldrsh_scale_ext, ldrsw_abs): Likewise.
368 (ldrh32_abs): Store 32 bit value not 64-bits.
369 (ldrh32_wb, ldrh32_scale_ext): Likewise.
370 (do_vec_MOV_immediate): Fix computation of val.
371 (do_vec_MVNI): Likewise.
372 (DO_VEC_WIDENING_MUL): New macro.
373 (do_vec_mull): Use new macro.
374 (do_vec_mul): Use new macro.
375 (do_vec_MLA): Read values before writing.
376 (do_vec_xtl): Likewise.
377 (do_vec_SSHL): Select correct shift value.
378 (do_vec_USHL): Likewise.
379 (do_scalar_UCVTF): New function.
380 (do_scalar_vec): Call new function.
381 (store_pair_u64): Treat reads of SP as reads of XZR.
383 2016-03-29 Nick Clifton <nickc@redhat.com>
385 * cpustate.c: Remove space after asterisk in function parameters.
386 * decode.h (greg): Delete unused function.
387 (vreg, shift, extension, scaling, writeback, condcode): Likewise.
388 * simulator.c: Use INSTR macro in more places.
389 (HALT_NYI): Use sim_io_eprintf in place of fprintf.
390 Remove extraneous whitespace.
392 2016-03-23 Nick Clifton <nickc@redhat.com>
394 * cpustate.c (aarch64_get_FP_half): New function. Read a vector
395 register as a half precision floating point number.
396 (aarch64_set_FP_half): New function. Similar, but for setting
397 a half precision register.
398 (aarch64_get_thread_id): New function. Returns the value of the
399 CPU's TPIDR register.
400 (aarch64_get_FPCR): New function. Returns the value of the CPU's
401 floating point control register.
402 (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR
404 * cpustate.h: Add prototypes for new functions.
405 * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
406 * memory.c: Use unaligned core access functions for all memory
408 * simulator.c (HALT_NYI): Generate an error message if tracing
409 will not tell the user why the simulator is halting.
410 (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro.
411 (INSTR): New time-saver macro.
412 (fldrb_abs): New function. Loads an 8-bit value using a scaled
414 (fldrh_abs): New function. Likewise for 16-bit values.
415 (do_vec_SSHL): Allow for negative shift values.
416 (do_vec_USHL): Likewise.
417 (do_vec_SHL): Correct computation of shift amount.
418 (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
419 shifts and computation of shift value.
420 (clz): New function. Counts leading zero bits.
421 (do_vec_CLZ): New function. Implements CLZ (vector).
422 (do_vec_MOV_element): Call do_vec_CLZ.
423 (dexSimpleFPCondCompare): Implement.
424 (do_FCVT_half_to_single): New function. Implements one of the
426 (do_FCVT_half_to_double): New function. Likewise.
427 (do_FCVT_single_to_half): New function. Likewise.
428 (do_FCVT_double_to_half): New function. Likewise.
429 (dexSimpleFPDataProc1Source): Call new FCVT functions.
430 (do_scalar_SHL): Handle negative shifts.
431 (do_scalar_shift): Handle SSHR.
432 (do_scalar_USHL): New function.
433 (do_double_add): Simplify to just performing a double precision
434 add operation. Move remaining code into...
435 (do_scalar_vec): ... New function.
436 (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
438 (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
440 (system_set): New function.
441 (do_MSR_immediate): New function. Stub for now.
442 (do_MSR_reg): New function. Likewise. Partially implements MSR
444 (do_SYS): New function. Stub for now,
445 (dexSystem): Call new functions.
447 2016-03-18 Nick Clifton <nickc@redhat.com>
449 * cpustate.c: Remove spurious spaces from TRACE strings.
450 Print hex equivalents of floats and doubles.
451 Check element number against array size when accessing vector
453 (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
455 (SET_VEC_ELEMENT): Likewise.
456 (GET_VEC_ELEMENT): And fix thinko using macro arguments.
458 * memory.c: Trace memory reads when --trace-memory is enabled.
459 Remove float and double load and store functions.
460 * memory.h (aarch64_get_mem_float): Delete prototype.
461 (aarch64_get_mem_double): Likewise.
462 (aarch64_set_mem_float): Likewise.
463 (aarch64_set_mem_double): Likewise.
464 * simulator (IS_SET): Always return either 0 or 1.
465 (IS_CLEAR): Likewise.
466 (fldrs_pcrel): Load and store floats using 32-bit memory accesses
467 and doubles using 64-bit memory accesses.
468 (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
469 (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
470 (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
471 (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
472 (store_pair_double, load_pair_float, load_pair_double): Likewise.
473 (do_vec_MUL_by_element): New function.
474 (do_vec_op2): Call do_vec_MUL_by_element.
475 (do_scalar_NEG): New function.
476 (do_double_add): Call do_scalar_NEG.
478 2016-03-03 Nick Clifton <nickc@redhat.com>
480 * simulator.c (set_flags_for_sub32): Correct type of signbit.
481 (CondCompare): Swap interpretation of bit 30.
482 (DO_ADDP): Delete macro.
483 (do_vec_ADDP): Copy source registers before starting to update
484 destination register.
485 (do_vec_FADDP): Likewise.
486 (do_vec_load_store): Fix computation of sizeof_operation.
487 (rbit64): Fix type of constant.
488 (aarch64_step): When displaying insn value, display all 32 bits.
490 2016-01-10 Mike Frysinger <vapier@gentoo.org>
492 * config.in, configure: Regenerate.
494 2016-01-10 Mike Frysinger <vapier@gentoo.org>
496 * configure: Regenerate.
498 2016-01-10 Mike Frysinger <vapier@gentoo.org>
500 * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
501 * configure: Regenerate.
503 2016-01-10 Mike Frysinger <vapier@gentoo.org>
505 * configure: Regenerate.
507 2016-01-10 Mike Frysinger <vapier@gentoo.org>
509 * configure: Regenerate.
511 2016-01-10 Mike Frysinger <vapier@gentoo.org>
513 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
514 * configure: Regenerate.
516 2016-01-10 Mike Frysinger <vapier@gentoo.org>
518 * configure: Regenerate.
520 2016-01-10 Mike Frysinger <vapier@gentoo.org>
522 * configure: Regenerate.
524 2016-01-09 Mike Frysinger <vapier@gentoo.org>
526 * config.in, configure: Regenerate.
528 2016-01-06 Mike Frysinger <vapier@gentoo.org>
530 * interp.c (sim_create_inferior): Mark argv and env const.
531 (sim_open): Mark argv const.
533 2016-01-05 Mike Frysinger <vapier@gentoo.org>
535 * interp.c: Delete dis-asm.h include.
536 (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
537 (sim_create_inferior): Delete disassemble init logic.
538 (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
539 (sim_open): Delete sim_add_option_table call.
540 * memory.c (mem_error): Delete disas check.
541 * simulator.c: Delete dis-asm.h include.
543 (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
544 (HALT_NYI): Likewise.
545 (handle_halt): Delete disas call.
546 (aarch64_step): Replace disas logic with TRACE_DISASM.
547 * simulator.h: Delete dis-asm.h include.
548 (aarch64_print_insn): Delete.
550 2016-01-04 Mike Frysinger <vapier@gentoo.org>
552 * simulator.c (MAX, MIN): Delete.
553 (do_vec_maxv): Change MAX to max and MIN to min.
554 (do_vec_fminmaxV): Likewise.
556 2016-01-04 Tristan Gingold <gingold@adacore.com>
558 * simulator.c: Remove syscall.h include.
560 2016-01-04 Mike Frysinger <vapier@gentoo.org>
562 * configure: Regenerate.
564 2016-01-03 Mike Frysinger <vapier@gentoo.org>
566 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
567 * configure: Regenerate.
569 2016-01-02 Mike Frysinger <vapier@gentoo.org>
571 * configure: Regenerate.
573 2015-12-27 Mike Frysinger <vapier@gentoo.org>
575 * interp.c (sim_dis_read): Change private_data to application_data.
576 (sim_create_inferior): Likewise.
578 2015-12-27 Mike Frysinger <vapier@gentoo.org>
580 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
582 2015-12-26 Mike Frysinger <vapier@gentoo.org>
584 * config.in, configure: Regenerate.
586 2015-12-26 Mike Frysinger <vapier@gentoo.org>
588 * interp.c (sim_create_inferior): Update comment and argv check.
590 2015-12-14 Nick Clifton <nickc@redhat.com>
592 * simulator.c (system_get): New function. Provides read
593 access to the dczid system register.
594 (do_mrs): New function - implements the MRS instruction.
595 (dexSystem): Call do_mrs for the MRS instruction. Halt on
596 unimplemented system instructions.
598 2015-11-24 Nick Clifton <nickc@redhat.com>
600 * configure.ac: New configure template.
601 * aclocal.m4: Generate.
602 * config.in: Generate.
603 * configure: Generate.
604 * cpustate.c: New file - functions for accessing AArch64 registers.
605 * cpustate.h: New header.
606 * decode.h: New header.
607 * interp.c: New file - interface between GDB and simulator.
608 * Makefile.in: New makefile template.
609 * memory.c: New file - functions for simulating aarch64 memory
611 * memory.h: New header.
612 * sim-main.h: New header.
613 * simulator.c: New file - aarch64 simulator functions.
614 * simulator.h: New header.