sim/aarch64/ChangeLog

   1 2021-05-17  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
   4         (struct sim_state): Delete.
   5
   6 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
   7
   8         * cpustate.c: Include defs.h.
   9         * interp.c: Replace config.h include with defs.h.
  10         * memory.c, simulator.c: Likewise.
  11         * cpustate.h, simulator.h: Delete config.h include.
  12
  13 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
  14
  15         * config.in, configure: Regenerate.
  16
  17 2021-05-14  Mike Frysinger  <vapier@gentoo.org>
  18
  19         * cpustate.h: Update include path.
  20         * interp.c: Likewise.
  21
  22 2021-05-04  Mike Frysinger  <vapier@gentoo.org>
  23
  24         * configure: Regenerate.
  25
  26 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  27
  28         * config.in, configure: Regenerate.
  29
  30 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  31
  32         * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
  33         (aarch64_set_FP_double, aarch64_set_FP_long_double,
  34         aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
  35
  36 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  37
  38         * simulator.c (do_fcvtzu): Change UL to ULL.
  39
  40 2021-04-26  Mike Frysinger  <vapier@gentoo.org>
  41
  42         * aclocal.m4, config.in, configure: Regenerate.
  43
  44 2021-04-22  Tom Tromey  <tom@tromey.com>
  45
  46         * configure, config.in: Rebuild.
  47
  48 2021-04-22  Tom Tromey  <tom@tromey.com>
  49
  50         * configure: Rebuild.
  51
  52 2021-04-21  Mike Frysinger  <vapier@gentoo.org>
  53
  54         * aclocal.m4: Regenerate.
  55
  56 2021-04-21  Simon Marchi  <simon.marchi@polymtl.ca>
  57
  58         * configure: Regenerate.
  59
  60 2021-04-18  Mike Frysinger  <vapier@gentoo.org>
  61
  62         * configure: Regenerate.
  63
  64 2021-04-12  Mike Frysinger  <vapier@gentoo.org>
  65
  66         * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
  67
  68 2021-04-07  Jim Wilson  <jimw@sifive.com>
  69
  70         PR sim/27483
  71         * simulator.c (set_flags_for_add32): Compare uresult against
  72         itself.  Compare sresult against itself.
  73
  74 2021-04-02  Mike Frysinger  <vapier@gentoo.org>
  75
  76         * aclocal.m4, configure: Regenerate.
  77
  78 2021-02-28  Mike Frysinger  <vapier@gentoo.org>
  79
  80         * configure: Regenerate.
  81
  82 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
  83
  84         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
  85         * aclocal.m4, configure: Regenerate.
  86
  87 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
  88
  89         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
  90         * aclocal.m4, configure: Regenerate.
  91
  92 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
  93
  94         * configure: Regenerate.
  95
  96 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
  97
  98         * config.in, configure: Regenerate.
  99
 100 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
 101
 102         * configure: Regenerate.
 103
 104 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
 105
 106         * configure: Regenerate.
 107
 108 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
 109
 110         * configure: Regenerate.
 111
 112 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
 113
 114         PR sim/25318
 115         * simulator.c (blr): Read destination register before calling
 116         aarch64_save_LR.
 117
 118 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
 119
 120         * cpustate.c: Add 'libiberty.h' include.
 121         * interp.c: Add 'sim-assert.h' include.
 122
 123 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
 124
 125         * configure: Regenerate.
 126
 127 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
 128
 129         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
 130         registers based on structure size.
 131         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
 132         (LD1_1): Replace with call to vec_load.
 133         (vec_store): Add new M argument.  Rewrite to iterate over registers
 134         based on structure size.
 135         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
 136         (ST1_1): Replace with call to vec_store.
 137
 138 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
 139
 140         * simulator.c (do_vec_FCVTL): New.
 141         (do_vec_op1): Call do_vec_FCVTL.
 142
 143         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
 144         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
 145         (do_scalar_vec): Add calls to new functions.
 146
 147 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
 148
 149         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
 150         flag check.
 151
 152 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
 153
 154         * simulator.c (mul64hi): Shift carry left by 32.
 155         (smulh): Change signum to negate.  If negate, invert result, and add
 156         carry bit if low part of multiply result is zero.
 157
 158 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
 159
 160         * simulator.c (do_vec_SMOV_into_scalar): New.
 161         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
 162         Rewritten.
 163         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
 164         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
 165         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
 166         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
 167
 168         * simulator.c (popcount): New.
 169         (do_vec_CNT): New.
 170         (do_vec_op1): Add do_vec_CNT call.
 171
 172 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
 173
 174         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
 175         with type set to input type size.
 176         (do_vec_xtl): Change bias from 3 to 4 for byte case.
 177
 178 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
 179
 180         * simulator.c (do_vec_MLA): Rewrite switch body.
 181
 182         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
 183         2.  Move test_false if inside loop.  Fix logic for computing result
 184         stored to vd.
 185
 186         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
 187         (do_vec_LDn_single, do_vec_STn_single): New.
 188         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
 189         loop over nregs using new var n.  Add n times size to address in loop.
 190         Add n to vd in loop.
 191         (do_vec_load_store): Add comment for instruction bit 24.  New var
 192         single to hold instruction bit 24.  Add new code to use single.  Move
 193         ldnr support inside single if statements.  Fix ldnr register counts
 194         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 195
 196 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 197
 198         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 199
 200 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 201
 202         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 203         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 204         case 3, call HALT_UNALLOC unconditionally.
 205         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 206         i + 2.  Delete if on bias, change index to i + bias * X.
 207
 208 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 209
 210         * simulator.c (do_vec_UZP): Rewrite.
 211
 212 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 213
 214         * cpustate.c: Include math.h.
 215         (aarch64_set_FP_float): Use signbit to check for signed zero.
 216         (aarch64_set_FP_double): Likewise.
 217         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 218         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 219         args same size as third arg.
 220         (fmaxnm): Use isnan instead of fpclassify.
 221         (fminnm, dmaxnm, dminnm): Likewise.
 222         (do_vec_MLS): Reverse order of subtraction operands.
 223         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 224         aarch64_get_FP_float to get source register contents.
 225         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 226         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 227         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 228         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 229         raise_exception calls.
 230
 231 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 232
 233         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 234         Add comment to document NaN issue.
 235         (set_flags_for_double_compare): Likewise.
 236
 237 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 238
 239         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 240         (set_flags_for_add64): Replace with a modified copy of
 241         set_flags_for_sub64.
 242
 243 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 244
 245         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 246         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 247
 248 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 249
 250         * simulator.c (fsturs): Switch use of rn and st variables.
 251         (fsturd, fsturq): Likewise
 252
 253 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 254
 255         * interp.c: Include bfd.h.
 256         (symcount, symtab, aarch64_get_sym_value): Delete.
 257         (remove_useless_symbols): Change count type to long.
 258         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 259         and symtab local variables.
 260         (sim_create_inferior): Delete storage.  Replace symbol code
 261         with a call to trace_load_symbols.
 262         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 263         includes.
 264         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 265         trace_sym_value.
 266         * memory.h: Delete bfd.h include.
 267         (mem_add_blk): Delete unused prototype.
 268         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 269         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 270         (aarch64_get_sym_value): Delete.
 271
 272 2016-08-12  Nick Clifton  <nickc@redhat.com>
 273
 274         * simulator.c (aarch64_step): Revert pervious delta.
 275         (aarch64_run): Call sim_events_tick after each
 276         instruction is simulated, and if necessary call
 277         sim_events_process.
 278         * simulator.h: Revert previous delta.
 279
 280 2016-08-11  Nick Clifton  <nickc@redhat.com>
 281
 282         * interp.c (sim_create_inferior): Allow for being called with a
 283         NULL abfd parameter.  If a bfd is provided, initialise the sim
 284         with that start address.
 285         * simulator.c (HALT_NYI): Just print out the numeric value of the
 286         instruction when not tracing.
 287         (aarch64_step): Change from static to global.
 288         * simulator.h: Add a prototype for aarch64_step().
 289
 290 2016-07-27  Alan Modra  <amodra@gmail.com>
 291
 292         * memory.c: Don't include libbfd.h.
 293
 294 2016-07-21  Nick Clifton  <nickc@redhat.com>
 295
 296         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 297
 298 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 299
 300         * cpustate.h: Include config.h.
 301         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 302         use anonymous structs to align members.
 303         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 304         endian_le2h_4 to read instruction from pc.
 305
 306 2016-05-06  Nick Clifton  <nickc@redhat.com>
 307
 308         * simulator.c (do_FMLA_by_element): New function.
 309         (do_vec_op2): Call it.
 310
 311 2016-04-27  Nick Clifton  <nickc@redhat.com>
 312
 313         * simulator.c: Add TRACE_DECODE statements to all emulation
 314         functions.
 315
 316 2016-03-30  Nick Clifton  <nickc@redhat.com>
 317
 318         * cpustate.c (aarch64_set_reg_s32): New function.
 319         (aarch64_set_reg_u32): New function.
 320         (aarch64_get_FP_half): Place half precision value into the correct
 321         slot of the union.
 322         (aarch64_set_FP_half): Likewise.
 323         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 324         aarch64_set_reg_u32.
 325         * memory.c (FETCH_FUNC): Cast the read value to the access type
 326         before converting it to the return type.  Rename to FETCH_FUNC64.
 327         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 328         accesses.  Use for 32-bit memory access functions.
 329         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 330         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 331         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 332         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 333         (ldrh32_abs): Store 32 bit value not 64-bits.
 334         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 335         (do_vec_MOV_immediate): Fix computation of val.
 336         (do_vec_MVNI): Likewise.
 337         (DO_VEC_WIDENING_MUL): New macro.
 338         (do_vec_mull): Use new macro.
 339         (do_vec_mul): Use new macro.
 340         (do_vec_MLA): Read values before writing.
 341         (do_vec_xtl): Likewise.
 342         (do_vec_SSHL): Select correct shift value.
 343         (do_vec_USHL): Likewise.
 344         (do_scalar_UCVTF): New function.
 345         (do_scalar_vec): Call new function.
 346         (store_pair_u64): Treat reads of SP as reads of XZR.
 347
 348 2016-03-29  Nick Clifton  <nickc@redhat.com>
 349
 350         * cpustate.c: Remove space after asterisk in function parameters.
 351         * decode.h (greg): Delete unused function.
 352         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 353         * simulator.c: Use INSTR macro in more places.
 354         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 355         Remove extraneous whitespace.
 356
 357 2016-03-23  Nick Clifton  <nickc@redhat.com>
 358
 359         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 360         register as a half precision floating point number.
 361         (aarch64_set_FP_half): New function.  Similar, but for setting
 362         a half precision register.
 363         (aarch64_get_thread_id): New function.  Returns the value of the
 364         CPU's TPIDR register.
 365         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 366         floating point control register.
 367         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 368         register.
 369         * cpustate.h: Add prototypes for new functions.
 370         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 371         * memory.c: Use unaligned core access functions for all memory
 372         reads and writes.
 373         * simulator.c (HALT_NYI): Generate an error message if tracing
 374         will not tell the user why the simulator is halting.
 375         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 376         (INSTR): New time-saver macro.
 377         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 378         offset.
 379         (fldrh_abs): New function.  Likewise for 16-bit values.
 380         (do_vec_SSHL): Allow for negative shift values.
 381         (do_vec_USHL): Likewise.
 382         (do_vec_SHL): Correct computation of shift amount.
 383         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 384         shifts and computation of shift value.
 385         (clz): New function.  Counts leading zero bits.
 386         (do_vec_CLZ): New function.  Implements CLZ (vector).
 387         (do_vec_MOV_element): Call do_vec_CLZ.
 388         (dexSimpleFPCondCompare): Implement.
 389         (do_FCVT_half_to_single): New function.  Implements one of the
 390         FCVT operations.
 391         (do_FCVT_half_to_double): New function.  Likewise.
 392         (do_FCVT_single_to_half): New function.  Likewise.
 393         (do_FCVT_double_to_half): New function.  Likewise.
 394         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 395         (do_scalar_SHL): Handle negative shifts.
 396         (do_scalar_shift): Handle SSHR.
 397         (do_scalar_USHL): New function.
 398         (do_double_add): Simplify to just performing a double precision
 399         add operation.  Move remaining code into...
 400         (do_scalar_vec): ... New function.
 401         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 402         functions.
 403         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 404         registers.
 405         (system_set): New function.
 406         (do_MSR_immediate): New function.  Stub for now.
 407         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 408         instruction.
 409         (do_SYS): New function.  Stub for now,
 410         (dexSystem): Call new functions.
 411
 412 2016-03-18  Nick Clifton  <nickc@redhat.com>
 413
 414         * cpustate.c: Remove spurious spaces from TRACE strings.
 415         Print hex equivalents of floats and doubles.
 416         Check element number against array size when accessing vector
 417         registers.
 418         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 419         element index.
 420         (SET_VEC_ELEMENT): Likewise.
 421         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 422
 423         * memory.c: Trace memory reads when --trace-memory is enabled.
 424         Remove float and double load and store functions.
 425         * memory.h (aarch64_get_mem_float): Delete prototype.
 426         (aarch64_get_mem_double): Likewise.
 427         (aarch64_set_mem_float): Likewise.
 428         (aarch64_set_mem_double): Likewise.
 429         * simulator (IS_SET): Always return either 0 or 1.
 430         (IS_CLEAR): Likewise.
 431         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 432         and doubles using 64-bit memory accesses.
 433         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 434         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 435         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 436         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 437         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 438         (do_vec_MUL_by_element): New function.
 439         (do_vec_op2): Call do_vec_MUL_by_element.
 440         (do_scalar_NEG): New function.
 441         (do_double_add): Call do_scalar_NEG.
 442
 443 2016-03-03  Nick Clifton  <nickc@redhat.com>
 444
 445         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 446         (CondCompare): Swap interpretation of bit 30.
 447         (DO_ADDP): Delete macro.
 448         (do_vec_ADDP): Copy source registers before starting to update
 449         destination register.
 450         (do_vec_FADDP): Likewise.
 451         (do_vec_load_store): Fix computation of sizeof_operation.
 452         (rbit64): Fix type of constant.
 453         (aarch64_step): When displaying insn value, display all 32 bits.
 454
 455 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 456
 457         * config.in, configure: Regenerate.
 458
 459 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 460
 461         * configure: Regenerate.
 462
 463 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 464
 465         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 466         * configure: Regenerate.
 467
 468 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 469
 470         * configure: Regenerate.
 471
 472 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 473
 474         * configure: Regenerate.
 475
 476 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 477
 478         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 479         * configure: Regenerate.
 480
 481 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 482
 483         * configure: Regenerate.
 484
 485 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 486
 487         * configure: Regenerate.
 488
 489 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 490
 491         * config.in, configure: Regenerate.
 492
 493 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 494
 495         * interp.c (sim_create_inferior): Mark argv and env const.
 496         (sim_open): Mark argv const.
 497
 498 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 499
 500         * interp.c: Delete dis-asm.h include.
 501         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 502         (sim_create_inferior): Delete disassemble init logic.
 503         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 504         (sim_open): Delete sim_add_option_table call.
 505         * memory.c (mem_error): Delete disas check.
 506         * simulator.c: Delete dis-asm.h include.
 507         (disas): Delete.
 508         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 509         (HALT_NYI): Likewise.
 510         (handle_halt): Delete disas call.
 511         (aarch64_step): Replace disas logic with TRACE_DISASM.
 512         * simulator.h: Delete dis-asm.h include.
 513         (aarch64_print_insn): Delete.
 514
 515 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 516
 517         * simulator.c (MAX, MIN): Delete.
 518         (do_vec_maxv): Change MAX to max and MIN to min.
 519         (do_vec_fminmaxV): Likewise.
 520
 521 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 522
 523         * simulator.c: Remove syscall.h include.
 524
 525 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 526
 527         * configure: Regenerate.
 528
 529 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 530
 531         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 532         * configure: Regenerate.
 533
 534 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 535
 536         * configure: Regenerate.
 537
 538 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 539
 540         * interp.c (sim_dis_read): Change private_data to application_data.
 541         (sim_create_inferior): Likewise.
 542
 543 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 544
 545         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 546
 547 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 548
 549         * config.in, configure: Regenerate.
 550
 551 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 552
 553         * interp.c (sim_create_inferior): Update comment and argv check.
 554
 555 2015-12-14  Nick Clifton  <nickc@redhat.com>
 556
 557         * simulator.c (system_get): New function.  Provides read
 558         access to the dczid system register.
 559         (do_mrs): New function - implements the MRS instruction.
 560         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 561         unimplemented system instructions.
 562
 563 2015-11-24  Nick Clifton  <nickc@redhat.com>
 564
 565         * configure.ac: New configure template.
 566         * aclocal.m4: Generate.
 567         * config.in: Generate.
 568         * configure: Generate.
 569         * cpustate.c: New file - functions for accessing AArch64 registers.
 570         * cpustate.h: New header.
 571         * decode.h: New header.
 572         * interp.c: New file - interface between GDB and simulator.
 573         * Makefile.in: New makefile template.
 574         * memory.c: New file - functions for simulating aarch64 memory
 575         accesses.
 576         * memory.h: New header.
 577         * sim-main.h: New header.
 578         * simulator.c: New file - aarch64 simulator functions.
 579         * simulator.h: New header.