sim/aarch64/ChangeLog

   1 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
   2
   3         * simulator.c (do_vec_FCVTL): New.
   4         (do_vec_op1): Call do_vec_FCVTL.
   5
   6         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
   7         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
   8         (do_scalar_vec): Add calls to new functions.
   9
  10 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
  11
  12         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
  13         flag check.
  14
  15 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
  16
  17         * simulator.c (mul64hi): Shift carry left by 32.
  18         (smulh): Change signum to negate.  If negate, invert result, and add
  19         carry bit if low part of multiply result is zero.
  20
  21 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
  22
  23         * simulator.c (do_vec_SMOV_into_scalar): New.
  24         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
  25         Rewritten.
  26         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
  27         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
  28         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
  29         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  30
  31         * simulator.c (popcount): New.
  32         (do_vec_CNT): New.
  33         (do_vec_op1): Add do_vec_CNT call.
  34
  35 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  36
  37         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  38         with type set to input type size.
  39         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  40
  41 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  42
  43         * simulator.c (do_vec_MLA): Rewrite switch body.
  44
  45         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
  46         2.  Move test_false if inside loop.  Fix logic for computing result
  47         stored to vd.
  48
  49         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  50         (do_vec_LDn_single, do_vec_STn_single): New.
  51         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  52         loop over nregs using new var n.  Add n times size to address in loop.
  53         Add n to vd in loop.
  54         (do_vec_load_store): Add comment for instruction bit 24.  New var
  55         single to hold instruction bit 24.  Add new code to use single.  Move
  56         ldnr support inside single if statements.  Fix ldnr register counts
  57         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  58
  59 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  60
  61         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  62
  63 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  64
  65         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  66         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  67         case 3, call HALT_UNALLOC unconditionally.
  68         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  69         i + 2.  Delete if on bias, change index to i + bias * X.
  70
  71 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  72
  73         * simulator.c (do_vec_UZP): Rewrite.
  74
  75 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
  76
  77         * cpustate.c: Include math.h.
  78         (aarch64_set_FP_float): Use signbit to check for signed zero.
  79         (aarch64_set_FP_double): Likewise.
  80         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
  81         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
  82         args same size as third arg.
  83         (fmaxnm): Use isnan instead of fpclassify.
  84         (fminnm, dmaxnm, dminnm): Likewise.
  85         (do_vec_MLS): Reverse order of subtraction operands.
  86         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
  87         aarch64_get_FP_float to get source register contents.
  88         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
  89         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
  90         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
  91         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
  92         raise_exception calls.
  93
  94 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
  95
  96         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
  97         Add comment to document NaN issue.
  98         (set_flags_for_double_compare): Likewise.
  99
 100 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 101
 102         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 103         (set_flags_for_add64): Replace with a modified copy of
 104         set_flags_for_sub64.
 105
 106 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 107
 108         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 109         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 110
 111 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 112
 113         * simulator.c (fsturs): Switch use of rn and st variables.
 114         (fsturd, fsturq): Likewise
 115
 116 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 117
 118         * interp.c: Include bfd.h.
 119         (symcount, symtab, aarch64_get_sym_value): Delete.
 120         (remove_useless_symbols): Change count type to long.
 121         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 122         and symtab local variables.
 123         (sim_create_inferior): Delete storage.  Replace symbol code
 124         with a call to trace_load_symbols.
 125         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 126         includes.
 127         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 128         trace_sym_value.
 129         * memory.h: Delete bfd.h include.
 130         (mem_add_blk): Delete unused prototype.
 131         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 132         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 133         (aarch64_get_sym_value): Delete.
 134
 135 2016-08-12  Nick Clifton  <nickc@redhat.com>
 136
 137         * simulator.c (aarch64_step): Revert pervious delta.
 138         (aarch64_run): Call sim_events_tick after each
 139         instruction is simulated, and if necessary call
 140         sim_events_process.
 141         * simulator.h: Revert previous delta.
 142
 143 2016-08-11  Nick Clifton  <nickc@redhat.com>
 144
 145         * interp.c (sim_create_inferior): Allow for being called with a
 146         NULL abfd parameter.  If a bfd is provided, initialise the sim
 147         with that start address.
 148         * simulator.c (HALT_NYI): Just print out the numeric value of the
 149         instruction when not tracing.
 150         (aarch64_step): Change from static to global.
 151         * simulator.h: Add a prototype for aarch64_step().
 152
 153 2016-07-27  Alan Modra  <amodra@gmail.com>
 154
 155         * memory.c: Don't include libbfd.h.
 156
 157 2016-07-21  Nick Clifton  <nickc@redhat.com>
 158
 159         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 160
 161 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 162
 163         * cpustate.h: Include config.h.
 164         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 165         use anonymous structs to align members.
 166         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 167         endian_le2h_4 to read instruction from pc.
 168
 169 2016-05-06  Nick Clifton  <nickc@redhat.com>
 170
 171         * simulator.c (do_FMLA_by_element): New function.
 172         (do_vec_op2): Call it.
 173
 174 2016-04-27  Nick Clifton  <nickc@redhat.com>
 175
 176         * simulator.c: Add TRACE_DECODE statements to all emulation
 177         functions.
 178
 179 2016-03-30  Nick Clifton  <nickc@redhat.com>
 180
 181         * cpustate.c (aarch64_set_reg_s32): New function.
 182         (aarch64_set_reg_u32): New function.
 183         (aarch64_get_FP_half): Place half precision value into the correct
 184         slot of the union.
 185         (aarch64_set_FP_half): Likewise.
 186         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 187         aarch64_set_reg_u32.
 188         * memory.c (FETCH_FUNC): Cast the read value to the access type
 189         before converting it to the return type.  Rename to FETCH_FUNC64.
 190         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 191         accesses.  Use for 32-bit memory access functions.
 192         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 193         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 194         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 195         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 196         (ldrh32_abs): Store 32 bit value not 64-bits.
 197         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 198         (do_vec_MOV_immediate): Fix computation of val.
 199         (do_vec_MVNI): Likewise.
 200         (DO_VEC_WIDENING_MUL): New macro.
 201         (do_vec_mull): Use new macro.
 202         (do_vec_mul): Use new macro.
 203         (do_vec_MLA): Read values before writing.
 204         (do_vec_xtl): Likewise.
 205         (do_vec_SSHL): Select correct shift value.
 206         (do_vec_USHL): Likewise.
 207         (do_scalar_UCVTF): New function.
 208         (do_scalar_vec): Call new function.
 209         (store_pair_u64): Treat reads of SP as reads of XZR.
 210
 211 2016-03-29  Nick Clifton  <nickc@redhat.com>
 212
 213         * cpustate.c: Remove space after asterisk in function parameters.
 214         * decode.h (greg): Delete unused function.
 215         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 216         * simulator.c: Use INSTR macro in more places.
 217         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 218         Remove extraneous whitespace.
 219
 220 2016-03-23  Nick Clifton  <nickc@redhat.com>
 221
 222         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 223         register as a half precision floating point number.
 224         (aarch64_set_FP_half): New function.  Similar, but for setting
 225         a half precision register.
 226         (aarch64_get_thread_id): New function.  Returns the value of the
 227         CPU's TPIDR register.
 228         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 229         floating point control register.
 230         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 231         register.
 232         * cpustate.h: Add prototypes for new functions.
 233         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 234         * memory.c: Use unaligned core access functions for all memory
 235         reads and writes.
 236         * simulator.c (HALT_NYI): Generate an error message if tracing
 237         will not tell the user why the simulator is halting.
 238         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 239         (INSTR): New time-saver macro.
 240         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 241         offset.
 242         (fldrh_abs): New function.  Likewise for 16-bit values.
 243         (do_vec_SSHL): Allow for negative shift values.
 244         (do_vec_USHL): Likewise.
 245         (do_vec_SHL): Correct computation of shift amount.
 246         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 247         shifts and computation of shift value.
 248         (clz): New function.  Counts leading zero bits.
 249         (do_vec_CLZ): New function.  Implements CLZ (vector).
 250         (do_vec_MOV_element): Call do_vec_CLZ.
 251         (dexSimpleFPCondCompare): Implement.
 252         (do_FCVT_half_to_single): New function.  Implements one of the
 253         FCVT operations.
 254         (do_FCVT_half_to_double): New function.  Likewise.
 255         (do_FCVT_single_to_half): New function.  Likewise.
 256         (do_FCVT_double_to_half): New function.  Likewise.
 257         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 258         (do_scalar_SHL): Handle negative shifts.
 259         (do_scalar_shift): Handle SSHR.
 260         (do_scalar_USHL): New function.
 261         (do_double_add): Simplify to just performing a double precision
 262         add operation.  Move remaining code into...
 263         (do_scalar_vec): ... New function.
 264         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 265         functions.
 266         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 267         registers.
 268         (system_set): New function.
 269         (do_MSR_immediate): New function.  Stub for now.
 270         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 271         instruction.
 272         (do_SYS): New function.  Stub for now,
 273         (dexSystem): Call new functions.
 274
 275 2016-03-18  Nick Clifton  <nickc@redhat.com>
 276
 277         * cpustate.c: Remove spurious spaces from TRACE strings.
 278         Print hex equivalents of floats and doubles.
 279         Check element number against array size when accessing vector
 280         registers.
 281         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 282         element index.
 283         (SET_VEC_ELEMENT): Likewise.
 284         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 285
 286         * memory.c: Trace memory reads when --trace-memory is enabled.
 287         Remove float and double load and store functions.
 288         * memory.h (aarch64_get_mem_float): Delete prototype.
 289         (aarch64_get_mem_double): Likewise.
 290         (aarch64_set_mem_float): Likewise.
 291         (aarch64_set_mem_double): Likewise.
 292         * simulator (IS_SET): Always return either 0 or 1.
 293         (IS_CLEAR): Likewise.
 294         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 295         and doubles using 64-bit memory accesses.
 296         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 297         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 298         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 299         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 300         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 301         (do_vec_MUL_by_element): New function.
 302         (do_vec_op2): Call do_vec_MUL_by_element.
 303         (do_scalar_NEG): New function.
 304         (do_double_add): Call do_scalar_NEG.
 305
 306 2016-03-03  Nick Clifton  <nickc@redhat.com>
 307
 308         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 309         (CondCompare): Swap interpretation of bit 30.
 310         (DO_ADDP): Delete macro.
 311         (do_vec_ADDP): Copy source registers before starting to update
 312         destination register.
 313         (do_vec_FADDP): Likewise.
 314         (do_vec_load_store): Fix computation of sizeof_operation.
 315         (rbit64): Fix type of constant.
 316         (aarch64_step): When displaying insn value, display all 32 bits.
 317
 318 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 319
 320         * config.in, configure: Regenerate.
 321
 322 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 323
 324         * configure: Regenerate.
 325
 326 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 327
 328         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 329         * configure: Regenerate.
 330
 331 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 332
 333         * configure: Regenerate.
 334
 335 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 336
 337         * configure: Regenerate.
 338
 339 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 340
 341         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 342         * configure: Regenerate.
 343
 344 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 345
 346         * configure: Regenerate.
 347
 348 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 349
 350         * configure: Regenerate.
 351
 352 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 353
 354         * config.in, configure: Regenerate.
 355
 356 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 357
 358         * interp.c (sim_create_inferior): Mark argv and env const.
 359         (sim_open): Mark argv const.
 360
 361 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 362
 363         * interp.c: Delete dis-asm.h include.
 364         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 365         (sim_create_inferior): Delete disassemble init logic.
 366         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 367         (sim_open): Delete sim_add_option_table call.
 368         * memory.c (mem_error): Delete disas check.
 369         * simulator.c: Delete dis-asm.h include.
 370         (disas): Delete.
 371         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 372         (HALT_NYI): Likewise.
 373         (handle_halt): Delete disas call.
 374         (aarch64_step): Replace disas logic with TRACE_DISASM.
 375         * simulator.h: Delete dis-asm.h include.
 376         (aarch64_print_insn): Delete.
 377
 378 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 379
 380         * simulator.c (MAX, MIN): Delete.
 381         (do_vec_maxv): Change MAX to max and MIN to min.
 382         (do_vec_fminmaxV): Likewise.
 383
 384 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 385
 386         * simulator.c: Remove syscall.h include.
 387
 388 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 389
 390         * configure: Regenerate.
 391
 392 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 393
 394         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 395         * configure: Regenerate.
 396
 397 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 398
 399         * configure: Regenerate.
 400
 401 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 402
 403         * interp.c (sim_dis_read): Change private_data to application_data.
 404         (sim_create_inferior): Likewise.
 405
 406 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 407
 408         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 409
 410 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 411
 412         * config.in, configure: Regenerate.
 413
 414 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 415
 416         * interp.c (sim_create_inferior): Update comment and argv check.
 417
 418 2015-12-14  Nick Clifton  <nickc@redhat.com>
 419
 420         * simulator.c (system_get): New function.  Provides read
 421         access to the dczid system register.
 422         (do_mrs): New function - implements the MRS instruction.
 423         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 424         unimplemented system instructions.
 425
 426 2015-11-24  Nick Clifton  <nickc@redhat.com>
 427
 428         * configure.ac: New configure template.
 429         * aclocal.m4: Generate.
 430         * config.in: Generate.
 431         * configure: Generate.
 432         * cpustate.c: New file - functions for accessing AArch64 registers.
 433         * cpustate.h: New header.
 434         * decode.h: New header.
 435         * interp.c: New file - interface between GDB and simulator.
 436         * Makefile.in: New makefile template.
 437         * memory.c: New file - functions for simulating aarch64 memory
 438         accesses.
 439         * memory.h: New header.
 440         * sim-main.h: New header.
 441         * simulator.c: New file - aarch64 simulator functions.
 442         * simulator.h: New header.