sim/aarch64/ChangeLog

   1 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * config.in, configure: Regenerate.
   4
   5 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
   6
   7         * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
   8         (aarch64_set_FP_double, aarch64_set_FP_long_double,
   9         aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
  10
  11 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  12
  13         * simulator.c (do_fcvtzu): Change UL to ULL.
  14
  15 2021-04-26  Mike Frysinger  <vapier@gentoo.org>
  16
  17         * aclocal.m4, config.in, configure: Regenerate.
  18
  19 2021-04-22  Tom Tromey  <tom@tromey.com>
  20
  21         * configure, config.in: Rebuild.
  22
  23 2021-04-22  Tom Tromey  <tom@tromey.com>
  24
  25         * configure: Rebuild.
  26
  27 2021-04-21  Mike Frysinger  <vapier@gentoo.org>
  28
  29         * aclocal.m4: Regenerate.
  30
  31 2021-04-21  Simon Marchi  <simon.marchi@polymtl.ca>
  32
  33         * configure: Regenerate.
  34
  35 2021-04-18  Mike Frysinger  <vapier@gentoo.org>
  36
  37         * configure: Regenerate.
  38
  39 2021-04-12  Mike Frysinger  <vapier@gentoo.org>
  40
  41         * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
  42
  43 2021-04-07  Jim Wilson  <jimw@sifive.com>
  44
  45         PR sim/27483
  46         * simulator.c (set_flags_for_add32): Compare uresult against
  47         itself.  Compare sresult against itself.
  48
  49 2021-04-02  Mike Frysinger  <vapier@gentoo.org>
  50
  51         * aclocal.m4, configure: Regenerate.
  52
  53 2021-02-28  Mike Frysinger  <vapier@gentoo.org>
  54
  55         * configure: Regenerate.
  56
  57 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
  58
  59         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
  60         * aclocal.m4, configure: Regenerate.
  61
  62 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
  63
  64         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
  65         * aclocal.m4, configure: Regenerate.
  66
  67 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
  68
  69         * configure: Regenerate.
  70
  71 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
  72
  73         * config.in, configure: Regenerate.
  74
  75 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
  76
  77         * configure: Regenerate.
  78
  79 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
  80
  81         * configure: Regenerate.
  82
  83 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
  84
  85         * configure: Regenerate.
  86
  87 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
  88
  89         PR sim/25318
  90         * simulator.c (blr): Read destination register before calling
  91         aarch64_save_LR.
  92
  93 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
  94
  95         * cpustate.c: Add 'libiberty.h' include.
  96         * interp.c: Add 'sim-assert.h' include.
  97
  98 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
  99
 100         * configure: Regenerate.
 101
 102 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
 103
 104         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
 105         registers based on structure size.
 106         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
 107         (LD1_1): Replace with call to vec_load.
 108         (vec_store): Add new M argument.  Rewrite to iterate over registers
 109         based on structure size.
 110         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
 111         (ST1_1): Replace with call to vec_store.
 112
 113 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
 114
 115         * simulator.c (do_vec_FCVTL): New.
 116         (do_vec_op1): Call do_vec_FCVTL.
 117
 118         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
 119         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
 120         (do_scalar_vec): Add calls to new functions.
 121
 122 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
 123
 124         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
 125         flag check.
 126
 127 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
 128
 129         * simulator.c (mul64hi): Shift carry left by 32.
 130         (smulh): Change signum to negate.  If negate, invert result, and add
 131         carry bit if low part of multiply result is zero.
 132
 133 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
 134
 135         * simulator.c (do_vec_SMOV_into_scalar): New.
 136         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
 137         Rewritten.
 138         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
 139         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
 140         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
 141         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
 142
 143         * simulator.c (popcount): New.
 144         (do_vec_CNT): New.
 145         (do_vec_op1): Add do_vec_CNT call.
 146
 147 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
 148
 149         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
 150         with type set to input type size.
 151         (do_vec_xtl): Change bias from 3 to 4 for byte case.
 152
 153 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
 154
 155         * simulator.c (do_vec_MLA): Rewrite switch body.
 156
 157         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
 158         2.  Move test_false if inside loop.  Fix logic for computing result
 159         stored to vd.
 160
 161         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
 162         (do_vec_LDn_single, do_vec_STn_single): New.
 163         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
 164         loop over nregs using new var n.  Add n times size to address in loop.
 165         Add n to vd in loop.
 166         (do_vec_load_store): Add comment for instruction bit 24.  New var
 167         single to hold instruction bit 24.  Add new code to use single.  Move
 168         ldnr support inside single if statements.  Fix ldnr register counts
 169         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 170
 171 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 172
 173         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 174
 175 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 176
 177         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 178         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 179         case 3, call HALT_UNALLOC unconditionally.
 180         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 181         i + 2.  Delete if on bias, change index to i + bias * X.
 182
 183 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 184
 185         * simulator.c (do_vec_UZP): Rewrite.
 186
 187 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 188
 189         * cpustate.c: Include math.h.
 190         (aarch64_set_FP_float): Use signbit to check for signed zero.
 191         (aarch64_set_FP_double): Likewise.
 192         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 193         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 194         args same size as third arg.
 195         (fmaxnm): Use isnan instead of fpclassify.
 196         (fminnm, dmaxnm, dminnm): Likewise.
 197         (do_vec_MLS): Reverse order of subtraction operands.
 198         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 199         aarch64_get_FP_float to get source register contents.
 200         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 201         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 202         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 203         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 204         raise_exception calls.
 205
 206 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 207
 208         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 209         Add comment to document NaN issue.
 210         (set_flags_for_double_compare): Likewise.
 211
 212 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 213
 214         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 215         (set_flags_for_add64): Replace with a modified copy of
 216         set_flags_for_sub64.
 217
 218 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 219
 220         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 221         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 222
 223 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 224
 225         * simulator.c (fsturs): Switch use of rn and st variables.
 226         (fsturd, fsturq): Likewise
 227
 228 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 229
 230         * interp.c: Include bfd.h.
 231         (symcount, symtab, aarch64_get_sym_value): Delete.
 232         (remove_useless_symbols): Change count type to long.
 233         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 234         and symtab local variables.
 235         (sim_create_inferior): Delete storage.  Replace symbol code
 236         with a call to trace_load_symbols.
 237         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 238         includes.
 239         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 240         trace_sym_value.
 241         * memory.h: Delete bfd.h include.
 242         (mem_add_blk): Delete unused prototype.
 243         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 244         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 245         (aarch64_get_sym_value): Delete.
 246
 247 2016-08-12  Nick Clifton  <nickc@redhat.com>
 248
 249         * simulator.c (aarch64_step): Revert pervious delta.
 250         (aarch64_run): Call sim_events_tick after each
 251         instruction is simulated, and if necessary call
 252         sim_events_process.
 253         * simulator.h: Revert previous delta.
 254
 255 2016-08-11  Nick Clifton  <nickc@redhat.com>
 256
 257         * interp.c (sim_create_inferior): Allow for being called with a
 258         NULL abfd parameter.  If a bfd is provided, initialise the sim
 259         with that start address.
 260         * simulator.c (HALT_NYI): Just print out the numeric value of the
 261         instruction when not tracing.
 262         (aarch64_step): Change from static to global.
 263         * simulator.h: Add a prototype for aarch64_step().
 264
 265 2016-07-27  Alan Modra  <amodra@gmail.com>
 266
 267         * memory.c: Don't include libbfd.h.
 268
 269 2016-07-21  Nick Clifton  <nickc@redhat.com>
 270
 271         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 272
 273 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 274
 275         * cpustate.h: Include config.h.
 276         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 277         use anonymous structs to align members.
 278         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 279         endian_le2h_4 to read instruction from pc.
 280
 281 2016-05-06  Nick Clifton  <nickc@redhat.com>
 282
 283         * simulator.c (do_FMLA_by_element): New function.
 284         (do_vec_op2): Call it.
 285
 286 2016-04-27  Nick Clifton  <nickc@redhat.com>
 287
 288         * simulator.c: Add TRACE_DECODE statements to all emulation
 289         functions.
 290
 291 2016-03-30  Nick Clifton  <nickc@redhat.com>
 292
 293         * cpustate.c (aarch64_set_reg_s32): New function.
 294         (aarch64_set_reg_u32): New function.
 295         (aarch64_get_FP_half): Place half precision value into the correct
 296         slot of the union.
 297         (aarch64_set_FP_half): Likewise.
 298         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 299         aarch64_set_reg_u32.
 300         * memory.c (FETCH_FUNC): Cast the read value to the access type
 301         before converting it to the return type.  Rename to FETCH_FUNC64.
 302         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 303         accesses.  Use for 32-bit memory access functions.
 304         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 305         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 306         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 307         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 308         (ldrh32_abs): Store 32 bit value not 64-bits.
 309         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 310         (do_vec_MOV_immediate): Fix computation of val.
 311         (do_vec_MVNI): Likewise.
 312         (DO_VEC_WIDENING_MUL): New macro.
 313         (do_vec_mull): Use new macro.
 314         (do_vec_mul): Use new macro.
 315         (do_vec_MLA): Read values before writing.
 316         (do_vec_xtl): Likewise.
 317         (do_vec_SSHL): Select correct shift value.
 318         (do_vec_USHL): Likewise.
 319         (do_scalar_UCVTF): New function.
 320         (do_scalar_vec): Call new function.
 321         (store_pair_u64): Treat reads of SP as reads of XZR.
 322
 323 2016-03-29  Nick Clifton  <nickc@redhat.com>
 324
 325         * cpustate.c: Remove space after asterisk in function parameters.
 326         * decode.h (greg): Delete unused function.
 327         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 328         * simulator.c: Use INSTR macro in more places.
 329         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 330         Remove extraneous whitespace.
 331
 332 2016-03-23  Nick Clifton  <nickc@redhat.com>
 333
 334         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 335         register as a half precision floating point number.
 336         (aarch64_set_FP_half): New function.  Similar, but for setting
 337         a half precision register.
 338         (aarch64_get_thread_id): New function.  Returns the value of the
 339         CPU's TPIDR register.
 340         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 341         floating point control register.
 342         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 343         register.
 344         * cpustate.h: Add prototypes for new functions.
 345         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 346         * memory.c: Use unaligned core access functions for all memory
 347         reads and writes.
 348         * simulator.c (HALT_NYI): Generate an error message if tracing
 349         will not tell the user why the simulator is halting.
 350         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 351         (INSTR): New time-saver macro.
 352         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 353         offset.
 354         (fldrh_abs): New function.  Likewise for 16-bit values.
 355         (do_vec_SSHL): Allow for negative shift values.
 356         (do_vec_USHL): Likewise.
 357         (do_vec_SHL): Correct computation of shift amount.
 358         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 359         shifts and computation of shift value.
 360         (clz): New function.  Counts leading zero bits.
 361         (do_vec_CLZ): New function.  Implements CLZ (vector).
 362         (do_vec_MOV_element): Call do_vec_CLZ.
 363         (dexSimpleFPCondCompare): Implement.
 364         (do_FCVT_half_to_single): New function.  Implements one of the
 365         FCVT operations.
 366         (do_FCVT_half_to_double): New function.  Likewise.
 367         (do_FCVT_single_to_half): New function.  Likewise.
 368         (do_FCVT_double_to_half): New function.  Likewise.
 369         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 370         (do_scalar_SHL): Handle negative shifts.
 371         (do_scalar_shift): Handle SSHR.
 372         (do_scalar_USHL): New function.
 373         (do_double_add): Simplify to just performing a double precision
 374         add operation.  Move remaining code into...
 375         (do_scalar_vec): ... New function.
 376         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 377         functions.
 378         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 379         registers.
 380         (system_set): New function.
 381         (do_MSR_immediate): New function.  Stub for now.
 382         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 383         instruction.
 384         (do_SYS): New function.  Stub for now,
 385         (dexSystem): Call new functions.
 386
 387 2016-03-18  Nick Clifton  <nickc@redhat.com>
 388
 389         * cpustate.c: Remove spurious spaces from TRACE strings.
 390         Print hex equivalents of floats and doubles.
 391         Check element number against array size when accessing vector
 392         registers.
 393         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 394         element index.
 395         (SET_VEC_ELEMENT): Likewise.
 396         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 397
 398         * memory.c: Trace memory reads when --trace-memory is enabled.
 399         Remove float and double load and store functions.
 400         * memory.h (aarch64_get_mem_float): Delete prototype.
 401         (aarch64_get_mem_double): Likewise.
 402         (aarch64_set_mem_float): Likewise.
 403         (aarch64_set_mem_double): Likewise.
 404         * simulator (IS_SET): Always return either 0 or 1.
 405         (IS_CLEAR): Likewise.
 406         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 407         and doubles using 64-bit memory accesses.
 408         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 409         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 410         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 411         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 412         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 413         (do_vec_MUL_by_element): New function.
 414         (do_vec_op2): Call do_vec_MUL_by_element.
 415         (do_scalar_NEG): New function.
 416         (do_double_add): Call do_scalar_NEG.
 417
 418 2016-03-03  Nick Clifton  <nickc@redhat.com>
 419
 420         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 421         (CondCompare): Swap interpretation of bit 30.
 422         (DO_ADDP): Delete macro.
 423         (do_vec_ADDP): Copy source registers before starting to update
 424         destination register.
 425         (do_vec_FADDP): Likewise.
 426         (do_vec_load_store): Fix computation of sizeof_operation.
 427         (rbit64): Fix type of constant.
 428         (aarch64_step): When displaying insn value, display all 32 bits.
 429
 430 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 431
 432         * config.in, configure: Regenerate.
 433
 434 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 435
 436         * configure: Regenerate.
 437
 438 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 439
 440         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 441         * configure: Regenerate.
 442
 443 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 444
 445         * configure: Regenerate.
 446
 447 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 448
 449         * configure: Regenerate.
 450
 451 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 452
 453         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 454         * configure: Regenerate.
 455
 456 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 457
 458         * configure: Regenerate.
 459
 460 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 461
 462         * configure: Regenerate.
 463
 464 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 465
 466         * config.in, configure: Regenerate.
 467
 468 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 469
 470         * interp.c (sim_create_inferior): Mark argv and env const.
 471         (sim_open): Mark argv const.
 472
 473 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 474
 475         * interp.c: Delete dis-asm.h include.
 476         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 477         (sim_create_inferior): Delete disassemble init logic.
 478         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 479         (sim_open): Delete sim_add_option_table call.
 480         * memory.c (mem_error): Delete disas check.
 481         * simulator.c: Delete dis-asm.h include.
 482         (disas): Delete.
 483         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 484         (HALT_NYI): Likewise.
 485         (handle_halt): Delete disas call.
 486         (aarch64_step): Replace disas logic with TRACE_DISASM.
 487         * simulator.h: Delete dis-asm.h include.
 488         (aarch64_print_insn): Delete.
 489
 490 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 491
 492         * simulator.c (MAX, MIN): Delete.
 493         (do_vec_maxv): Change MAX to max and MIN to min.
 494         (do_vec_fminmaxV): Likewise.
 495
 496 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 497
 498         * simulator.c: Remove syscall.h include.
 499
 500 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 501
 502         * configure: Regenerate.
 503
 504 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 505
 506         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 507         * configure: Regenerate.
 508
 509 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 510
 511         * configure: Regenerate.
 512
 513 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 514
 515         * interp.c (sim_dis_read): Change private_data to application_data.
 516         (sim_create_inferior): Likewise.
 517
 518 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 519
 520         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 521
 522 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 523
 524         * config.in, configure: Regenerate.
 525
 526 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 527
 528         * interp.c (sim_create_inferior): Update comment and argv check.
 529
 530 2015-12-14  Nick Clifton  <nickc@redhat.com>
 531
 532         * simulator.c (system_get): New function.  Provides read
 533         access to the dczid system register.
 534         (do_mrs): New function - implements the MRS instruction.
 535         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 536         unimplemented system instructions.
 537
 538 2015-11-24  Nick Clifton  <nickc@redhat.com>
 539
 540         * configure.ac: New configure template.
 541         * aclocal.m4: Generate.
 542         * config.in: Generate.
 543         * configure: Generate.
 544         * cpustate.c: New file - functions for accessing AArch64 registers.
 545         * cpustate.h: New header.
 546         * decode.h: New header.
 547         * interp.c: New file - interface between GDB and simulator.
 548         * Makefile.in: New makefile template.
 549         * memory.c: New file - functions for simulating aarch64 memory
 550         accesses.
 551         * memory.h: New header.
 552         * sim-main.h: New header.
 553         * simulator.c: New file - aarch64 simulator functions.
 554         * simulator.h: New header.