sim/aarch64/cpustate.c

   1 /* cpustate.h -- Prototypes for AArch64 simulator functions.
   2
   3    Copyright (C) 2015-2016 Free Software Foundation, Inc.
   4
   5    Contributed by Red Hat.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include <stdio.h>
  23
  24 #include "sim-main.h"
  25 #include "cpustate.h"
  26 #include "simulator.h"
  27
  28 /* Some operands are allowed to access the stack pointer (reg 31).
  29    For others a read from r31 always returns 0, and a write to r31 is ignored.  */
  30 #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
  31
  32 void
  33 aarch64_set_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint64_t val)
  34 {
  35   if (reg == R31 && ! r31_is_sp)
  36     {
  37       TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
  38       return;
  39     }
  40
  41   if (val != cpu->gr[reg].u64)
  42     TRACE_REGISTER (cpu,
  43                     "GR[%2d] changes from %16" PRIx64 " to %16" PRIx64,
  44                     reg, cpu->gr[reg].u64, val);
  45
  46   cpu->gr[reg].u64 = val;
  47 }
  48
  49 void
  50 aarch64_set_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp, int64_t val)
  51 {
  52   if (reg == R31 && ! r31_is_sp)
  53     {
  54       TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
  55       return;
  56     }
  57
  58   if (val != cpu->gr[reg].s64)
  59     TRACE_REGISTER (cpu,
  60                     "GR[%2d] changes from %16" PRIx64 " to %16" PRIx64,
  61                     reg, cpu->gr[reg].s64, val);
  62
  63   cpu->gr[reg].s64 = val;
  64 }
  65
  66 uint64_t
  67 aarch64_get_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp)
  68 {
  69   return cpu->gr[reg_num(reg)].u64;
  70 }
  71
  72 int64_t
  73 aarch64_get_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp)
  74 {
  75   return cpu->gr[reg_num(reg)].s64;
  76 }
  77
  78 uint32_t
  79 aarch64_get_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp)
  80 {
  81   return cpu->gr[reg_num(reg)].u32;
  82 }
  83
  84 int32_t
  85 aarch64_get_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp)
  86 {
  87   return cpu->gr[reg_num(reg)].s32;
  88 }
  89
  90 uint32_t
  91 aarch64_get_reg_u16 (sim_cpu *cpu, GReg reg, int r31_is_sp)
  92 {
  93   return cpu->gr[reg_num(reg)].u16;
  94 }
  95
  96 int32_t
  97 aarch64_get_reg_s16 (sim_cpu *cpu, GReg reg, int r31_is_sp)
  98 {
  99   return cpu->gr[reg_num(reg)].s16;
 100 }
 101
 102 uint32_t
 103 aarch64_get_reg_u8 (sim_cpu *cpu, GReg reg, int r31_is_sp)
 104 {
 105   return cpu->gr[reg_num(reg)].u8;
 106 }
 107
 108 int32_t
 109 aarch64_get_reg_s8 (sim_cpu *cpu, GReg reg, int r31_is_sp)
 110 {
 111   return cpu->gr[reg_num(reg)].s8;
 112 }
 113
 114 uint64_t
 115 aarch64_get_PC (sim_cpu *cpu)
 116 {
 117   return cpu->pc;
 118 }
 119
 120 uint64_t
 121 aarch64_get_next_PC (sim_cpu *cpu)
 122 {
 123   return cpu->nextpc;
 124 }
 125
 126 void
 127 aarch64_set_next_PC (sim_cpu *cpu, uint64_t next)
 128 {
 129   if (next != cpu->nextpc + 4)
 130     TRACE_REGISTER (cpu,
 131                     "NextPC changes from %16" PRIx64 " to %16" PRIx64,
 132                     cpu->nextpc, next);
 133
 134   cpu->nextpc = next;
 135 }
 136
 137 void
 138 aarch64_set_next_PC_by_offset (sim_cpu *cpu, int64_t offset)
 139 {
 140   if (cpu->pc + offset != cpu->nextpc + 4)
 141     TRACE_REGISTER (cpu,
 142                     "NextPC changes from %16" PRIx64 " to %16" PRIx64,
 143                     cpu->nextpc, cpu->pc + offset);
 144
 145   cpu->nextpc = cpu->pc + offset;
 146 }
 147
 148 /* Install nextpc as current pc.  */
 149 void
 150 aarch64_update_PC (sim_cpu *cpu)
 151 {
 152   cpu->pc = cpu->nextpc;
 153   /* Rezero the register we hand out when asked for ZR just in case it
 154      was used as the destination for a write by the previous
 155      instruction.  */
 156   cpu->gr[32].u64 = 0UL;
 157 }
 158
 159 /* This instruction can be used to save the next PC to LR
 160    just before installing a branch PC.  */
 161 void
 162 aarch64_save_LR (sim_cpu *cpu)
 163 {
 164   if (cpu->gr[LR].u64 != cpu->nextpc)
 165     TRACE_REGISTER (cpu,
 166                     "LR    changes from %16" PRIx64 " to %16" PRIx64,
 167                     cpu->gr[LR].u64, cpu->nextpc);
 168
 169   cpu->gr[LR].u64 = cpu->nextpc;
 170 }
 171
 172 static const char *
 173 decode_cpsr (FlagMask flags)
 174 {
 175   switch (flags & CPSR_ALL_FLAGS)
 176     {
 177     default:
 178     case 0:  return "----";
 179     case 1:  return "---V";
 180     case 2:  return "--C-";
 181     case 3:  return "--CV";
 182     case 4:  return "-Z--";
 183     case 5:  return "-Z-V";
 184     case 6:  return "-ZC-";
 185     case 7:  return "-ZCV";
 186     case 8:  return "N---";
 187     case 9:  return "N--V";
 188     case 10: return "N-C-";
 189     case 11: return "N-CV";
 190     case 12: return "NZ--";
 191     case 13: return "NZ-V";
 192     case 14: return "NZC-";
 193     case 15: return "NZCV";
 194     }
 195 }
 196
 197 /* Retrieve the CPSR register as an int.  */
 198 uint32_t
 199 aarch64_get_CPSR (sim_cpu *cpu)
 200 {
 201   return cpu->CPSR;
 202 }
 203
 204 /* Set the CPSR register as an int.  */
 205 void
 206 aarch64_set_CPSR (sim_cpu *cpu, uint32_t new_flags)
 207 {
 208   if (TRACE_REGISTER_P (cpu))
 209     {
 210       if (cpu->CPSR != new_flags)
 211         TRACE_REGISTER (cpu,
 212                         "CPSR changes from %s to %s",
 213                         decode_cpsr (cpu->CPSR), decode_cpsr (new_flags));
 214       else
 215         TRACE_REGISTER (cpu,
 216                         "CPSR stays at %s", decode_cpsr (cpu->CPSR));
 217     }
 218
 219   cpu->CPSR = new_flags & CPSR_ALL_FLAGS;
 220 }
 221
 222 /* Read a specific subset of the CPSR as a bit pattern.  */
 223 uint32_t
 224 aarch64_get_CPSR_bits (sim_cpu *cpu, FlagMask mask)
 225 {
 226   return cpu->CPSR & mask;
 227 }
 228
 229 /* Assign a specific subset of the CPSR as a bit pattern.  */
 230 void
 231 aarch64_set_CPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
 232 {
 233   uint32_t old_flags = cpu->CPSR;
 234
 235   mask &= CPSR_ALL_FLAGS;
 236   cpu->CPSR &= ~ mask;
 237   cpu->CPSR |= (value & mask);
 238
 239   if (old_flags != cpu->CPSR)
 240     TRACE_REGISTER (cpu,
 241                     "CPSR changes from %s to %s",
 242                     decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
 243 }
 244
 245 /* Test the value of a single CPSR returned as non-zero or zero.  */
 246 uint32_t
 247 aarch64_test_CPSR_bit (sim_cpu *cpu, FlagMask bit)
 248 {
 249   return cpu->CPSR & bit;
 250 }
 251
 252 /* Set a single flag in the CPSR.  */
 253 void
 254 aarch64_set_CPSR_bit (sim_cpu *cpu, FlagMask bit)
 255 {
 256   uint32_t old_flags = cpu->CPSR;
 257
 258   cpu->CPSR |= (bit & CPSR_ALL_FLAGS);
 259
 260   if (old_flags != cpu->CPSR)
 261     TRACE_REGISTER (cpu,
 262                     "CPSR changes from %s to %s",
 263                     decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
 264 }
 265
 266 /* Clear a single flag in the CPSR.  */
 267 void
 268 aarch64_clear_CPSR_bit (sim_cpu *cpu, FlagMask bit)
 269 {
 270   uint32_t old_flags = cpu->CPSR;
 271
 272   cpu->CPSR &= ~(bit & CPSR_ALL_FLAGS);
 273
 274   if (old_flags != cpu->CPSR)
 275     TRACE_REGISTER (cpu,
 276                     "CPSR changes from %s to %s",
 277                     decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
 278 }
 279
 280 float
 281 aarch64_get_FP_half (sim_cpu *cpu, VReg reg)
 282 {
 283   union
 284   {
 285     uint16_t h[2];
 286     float    f;
 287   } u;
 288
 289   u.h[0] = cpu->fr[reg].h[0];
 290   u.h[1] = 0;
 291   return u.f;
 292 }
 293
 294
 295 float
 296 aarch64_get_FP_float (sim_cpu *cpu, VReg reg)
 297 {
 298   return cpu->fr[reg].s;
 299 }
 300
 301 double
 302 aarch64_get_FP_double (sim_cpu *cpu, VReg reg)
 303 {
 304   return cpu->fr[reg].d;
 305 }
 306
 307 void
 308 aarch64_get_FP_long_double (sim_cpu *cpu, VReg reg, FRegister *a)
 309 {
 310   a->v[0] = cpu->fr[reg].v[0];
 311   a->v[1] = cpu->fr[reg].v[1];
 312 }
 313
 314 void
 315 aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val)
 316 {
 317   union
 318   {
 319     uint16_t h[2];
 320     float    f;
 321   } u;
 322
 323   u.f = val;
 324   cpu->fr[reg].h[0] = u.h[0];
 325   cpu->fr[reg].h[1] = 0;
 326 }
 327
 328
 329 void
 330 aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
 331 {
 332   if (val != cpu->fr[reg].s)
 333     {
 334       FRegister v;
 335
 336       v.s = val;
 337       TRACE_REGISTER (cpu,
 338                       "FR[%d].s changes from %f to %f [hex: %0lx]",
 339                       reg, cpu->fr[reg].s, val, v.v[0]);
 340     }
 341
 342   cpu->fr[reg].s = val;
 343 }
 344
 345 void
 346 aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val)
 347 {
 348   if (val != cpu->fr[reg].d)
 349     {
 350       FRegister v;
 351
 352       v.d = val;
 353       TRACE_REGISTER (cpu,
 354                       "FR[%d].d changes from %f to %f [hex: %0lx]",
 355                       reg, cpu->fr[reg].d, val, v.v[0]);
 356     }
 357   cpu->fr[reg].d = val;
 358 }
 359
 360 void
 361 aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a)
 362 {
 363   if (cpu->fr[reg].v[0] != a.v[0]
 364       || cpu->fr[reg].v[1] != a.v[1])
 365     TRACE_REGISTER (cpu,
 366                     "FR[%d].q changes from [%0lx %0lx] to [%0lx %0lx] ",
 367                     reg,
 368                     cpu->fr[reg].v[0], cpu->fr[reg].v[1],
 369                     a.v[0], a.v[1]);
 370
 371   cpu->fr[reg].v[0] = a.v[0];
 372   cpu->fr[reg].v[1] = a.v[1];
 373 }
 374
 375 #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD)       \
 376   do                                               \
 377     {                                              \
 378       if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
 379         {                                                               \
 380           TRACE_REGISTER (cpu, \
 381                           "Internal SIM error: invalid element number: %d ",\
 382                           ELEMENT);                                     \
 383           sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
 384                            sim_stopped, SIM_SIGBUS);                    \
 385         }                                                               \
 386       return cpu->fr[REG].FIELD [ELEMENT];                              \
 387     }                                                                   \
 388   while (0)
 389
 390 uint64_t
 391 aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element)
 392 {
 393   GET_VEC_ELEMENT (reg, element, v);
 394 }
 395
 396 uint32_t
 397 aarch64_get_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element)
 398 {
 399   GET_VEC_ELEMENT (reg, element, w);
 400 }
 401
 402 uint16_t
 403 aarch64_get_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element)
 404 {
 405   GET_VEC_ELEMENT (reg, element, h);
 406 }
 407
 408 uint8_t
 409 aarch64_get_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element)
 410 {
 411   GET_VEC_ELEMENT (reg, element, b);
 412 }
 413
 414 int64_t
 415 aarch64_get_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element)
 416 {
 417   GET_VEC_ELEMENT (reg, element, V);
 418 }
 419
 420 int32_t
 421 aarch64_get_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element)
 422 {
 423   GET_VEC_ELEMENT (reg, element, W);
 424 }
 425
 426 int16_t
 427 aarch64_get_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element)
 428 {
 429   GET_VEC_ELEMENT (reg, element, H);
 430 }
 431
 432 int8_t
 433 aarch64_get_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element)
 434 {
 435   GET_VEC_ELEMENT (reg, element, B);
 436 }
 437
 438 float
 439 aarch64_get_vec_float (sim_cpu *cpu, VReg reg, unsigned element)
 440 {
 441   GET_VEC_ELEMENT (reg, element, S);
 442 }
 443
 444 double
 445 aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element)
 446 {
 447   GET_VEC_ELEMENT (reg, element, D);
 448 }
 449
 450
 451 #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER)      \
 452   do                                                            \
 453     {                                                           \
 454       if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD))                     \
 455         {                                                               \
 456           TRACE_REGISTER (cpu, \
 457                           "Internal SIM error: invalid element number: %d ",\
 458                           ELEMENT);                                     \
 459           sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
 460                            sim_stopped, SIM_SIGBUS);                    \
 461         }                                                               \
 462       if (VAL != cpu->fr[REG].FIELD [ELEMENT])                          \
 463         TRACE_REGISTER (cpu,                                            \
 464                         "VR[%2d]." #FIELD " [%d] changes from " PRINTER \
 465                         " to " PRINTER , REG,                           \
 466                         ELEMENT, cpu->fr[REG].FIELD [ELEMENT], VAL);    \
 467       \
 468       cpu->fr[REG].FIELD [ELEMENT] = VAL;     \
 469     }                                         \
 470   while (0)
 471
 472 void
 473 aarch64_set_vec_u64 (sim_cpu * cpu, VReg reg, unsigned element, uint64_t val)
 474 {
 475   SET_VEC_ELEMENT (reg, element, val, v, "%16lx");
 476 }
 477
 478 void
 479 aarch64_set_vec_u32 (sim_cpu * cpu, VReg reg, unsigned element, uint32_t val)
 480 {
 481   SET_VEC_ELEMENT (reg, element, val, w, "%8x");
 482 }
 483
 484 void
 485 aarch64_set_vec_u16 (sim_cpu * cpu, VReg reg, unsigned element, uint16_t val)
 486 {
 487   SET_VEC_ELEMENT (reg, element, val, h, "%4x");
 488 }
 489
 490 void
 491 aarch64_set_vec_u8 (sim_cpu * cpu, VReg reg, unsigned element, uint8_t val)
 492 {
 493   SET_VEC_ELEMENT (reg, element, val, b, "%x");
 494 }
 495
 496 void
 497 aarch64_set_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element, int64_t val)
 498 {
 499   SET_VEC_ELEMENT (reg, element, val, V, "%16lx");
 500 }
 501
 502 void
 503 aarch64_set_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element, int32_t val)
 504 {
 505   SET_VEC_ELEMENT (reg, element, val, W, "%8x");
 506 }
 507
 508 void
 509 aarch64_set_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element, int16_t val)
 510 {
 511   SET_VEC_ELEMENT (reg, element, val, H, "%4x");
 512 }
 513
 514 void
 515 aarch64_set_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element, int8_t val)
 516 {
 517   SET_VEC_ELEMENT (reg, element, val, B, "%x");
 518 }
 519
 520 void
 521 aarch64_set_vec_float (sim_cpu *cpu, VReg reg, unsigned element, float val)
 522 {
 523   SET_VEC_ELEMENT (reg, element, val, S, "%f");
 524 }
 525
 526 void
 527 aarch64_set_vec_double (sim_cpu *cpu, VReg reg, unsigned element, double val)
 528 {
 529   SET_VEC_ELEMENT (reg, element, val, D, "%f");
 530 }
 531
 532 void
 533 aarch64_set_FPSR (sim_cpu *cpu, uint32_t value)
 534 {
 535   if (cpu->FPSR != value)
 536     TRACE_REGISTER (cpu,
 537                     "FPSR changes from %x to %x", cpu->FPSR, value);
 538
 539   cpu->FPSR = value & FPSR_ALL_FPSRS;
 540 }
 541
 542 uint32_t
 543 aarch64_get_FPSR (sim_cpu *cpu)
 544 {
 545   return cpu->FPSR;
 546 }
 547
 548 void
 549 aarch64_set_FPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
 550 {
 551   uint32_t old_FPSR = cpu->FPSR;
 552
 553   mask &= FPSR_ALL_FPSRS;
 554   cpu->FPSR &= ~mask;
 555   cpu->FPSR |= (value & mask);
 556
 557   if (cpu->FPSR != old_FPSR)
 558     TRACE_REGISTER (cpu,
 559                     "FPSR changes from %x to %x", old_FPSR, cpu->FPSR);
 560 }
 561
 562 uint32_t
 563 aarch64_get_FPSR_bits (sim_cpu *cpu, uint32_t mask)
 564 {
 565   mask &= FPSR_ALL_FPSRS;
 566   return cpu->FPSR & mask;
 567 }
 568
 569 int
 570 aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag)
 571 {
 572   return cpu->FPSR & flag;
 573 }
 574
 575 uint64_t
 576 aarch64_get_thread_id (sim_cpu * cpu)
 577 {
 578   return cpu->tpidr;
 579 }
 580
 581 uint32_t
 582 aarch64_get_FPCR (sim_cpu * cpu)
 583 {
 584   return cpu->FPCR;
 585 }
 586
 587 void
 588 aarch64_set_FPCR (sim_cpu * cpu, uint32_t val)
 589 {
 590   if (cpu->FPCR != val)
 591     TRACE_REGISTER (cpu,
 592                     "FPCR changes from %x to %x", cpu->FPCR, val);
 593   cpu->FPCR = val;
 594 }