]>
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1 /* cpustate.h -- Prototypes for AArch64 simulator functions.
3 Copyright (C) 2015-2021 Free Software Foundation, Inc.
5 Contributed by Red Hat.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* This must come before any other includes. */
30 #include "simulator.h"
31 #include "libiberty.h"
33 /* Some operands are allowed to access the stack pointer (reg 31).
34 For others a read from r31 always returns 0, and a write to r31 is ignored. */
35 #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
38 aarch64_set_reg_u64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, uint64_t val
)
40 if (reg
== R31
&& ! r31_is_sp
)
42 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
46 if (val
!= cpu
->gr
[reg
].u64
)
48 "GR[%2d] changes from %16" PRIx64
" to %16" PRIx64
,
49 reg
, cpu
->gr
[reg
].u64
, val
);
51 cpu
->gr
[reg
].u64
= val
;
55 aarch64_set_reg_s64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, int64_t val
)
57 if (reg
== R31
&& ! r31_is_sp
)
59 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
63 if (val
!= cpu
->gr
[reg
].s64
)
65 "GR[%2d] changes from %16" PRIx64
" to %16" PRIx64
,
66 reg
, cpu
->gr
[reg
].s64
, val
);
68 cpu
->gr
[reg
].s64
= val
;
72 aarch64_get_reg_u64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
74 return cpu
->gr
[reg_num(reg
)].u64
;
78 aarch64_get_reg_s64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
80 return cpu
->gr
[reg_num(reg
)].s64
;
84 aarch64_get_reg_u32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
86 return cpu
->gr
[reg_num(reg
)].u32
;
90 aarch64_get_reg_s32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
92 return cpu
->gr
[reg_num(reg
)].s32
;
96 aarch64_set_reg_s32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, int32_t val
)
98 if (reg
== R31
&& ! r31_is_sp
)
100 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
104 if (val
!= cpu
->gr
[reg
].s32
)
105 TRACE_REGISTER (cpu
, "GR[%2d] changes from %8x to %8x",
106 reg
, cpu
->gr
[reg
].s32
, val
);
108 /* The ARM ARM states that (C1.2.4):
109 When the data size is 32 bits, the lower 32 bits of the
110 register are used and the upper 32 bits are ignored on
111 a read and cleared to zero on a write.
112 We simulate this by first clearing the whole 64-bits and
113 then writing to the 32-bit value in the GRegister union. */
114 cpu
->gr
[reg
].s64
= 0;
115 cpu
->gr
[reg
].s32
= val
;
119 aarch64_set_reg_u32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, uint32_t val
)
121 if (reg
== R31
&& ! r31_is_sp
)
123 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
127 if (val
!= cpu
->gr
[reg
].u32
)
128 TRACE_REGISTER (cpu
, "GR[%2d] changes from %8x to %8x",
129 reg
, cpu
->gr
[reg
].u32
, val
);
131 cpu
->gr
[reg
].u64
= 0;
132 cpu
->gr
[reg
].u32
= val
;
136 aarch64_get_reg_u16 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
138 return cpu
->gr
[reg_num(reg
)].u16
;
142 aarch64_get_reg_s16 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
144 return cpu
->gr
[reg_num(reg
)].s16
;
148 aarch64_get_reg_u8 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
150 return cpu
->gr
[reg_num(reg
)].u8
;
154 aarch64_get_reg_s8 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
156 return cpu
->gr
[reg_num(reg
)].s8
;
160 aarch64_get_PC (sim_cpu
*cpu
)
166 aarch64_get_next_PC (sim_cpu
*cpu
)
172 aarch64_set_next_PC (sim_cpu
*cpu
, uint64_t next
)
174 if (next
!= cpu
->nextpc
+ 4)
176 "NextPC changes from %16" PRIx64
" to %16" PRIx64
,
183 aarch64_set_next_PC_by_offset (sim_cpu
*cpu
, int64_t offset
)
185 if (cpu
->pc
+ offset
!= cpu
->nextpc
+ 4)
187 "NextPC changes from %16" PRIx64
" to %16" PRIx64
,
188 cpu
->nextpc
, cpu
->pc
+ offset
);
190 cpu
->nextpc
= cpu
->pc
+ offset
;
193 /* Install nextpc as current pc. */
195 aarch64_update_PC (sim_cpu
*cpu
)
197 cpu
->pc
= cpu
->nextpc
;
198 /* Rezero the register we hand out when asked for ZR just in case it
199 was used as the destination for a write by the previous
201 cpu
->gr
[32].u64
= 0UL;
204 /* This instruction can be used to save the next PC to LR
205 just before installing a branch PC. */
207 aarch64_save_LR (sim_cpu
*cpu
)
209 if (cpu
->gr
[LR
].u64
!= cpu
->nextpc
)
211 "LR changes from %16" PRIx64
" to %16" PRIx64
,
212 cpu
->gr
[LR
].u64
, cpu
->nextpc
);
214 cpu
->gr
[LR
].u64
= cpu
->nextpc
;
218 decode_cpsr (FlagMask flags
)
220 switch (flags
& CPSR_ALL_FLAGS
)
223 case 0: return "----";
224 case 1: return "---V";
225 case 2: return "--C-";
226 case 3: return "--CV";
227 case 4: return "-Z--";
228 case 5: return "-Z-V";
229 case 6: return "-ZC-";
230 case 7: return "-ZCV";
231 case 8: return "N---";
232 case 9: return "N--V";
233 case 10: return "N-C-";
234 case 11: return "N-CV";
235 case 12: return "NZ--";
236 case 13: return "NZ-V";
237 case 14: return "NZC-";
238 case 15: return "NZCV";
242 /* Retrieve the CPSR register as an int. */
244 aarch64_get_CPSR (sim_cpu
*cpu
)
249 /* Set the CPSR register as an int. */
251 aarch64_set_CPSR (sim_cpu
*cpu
, uint32_t new_flags
)
253 if (TRACE_REGISTER_P (cpu
))
255 if (cpu
->CPSR
!= new_flags
)
257 "CPSR changes from %s to %s",
258 decode_cpsr (cpu
->CPSR
), decode_cpsr (new_flags
));
261 "CPSR stays at %s", decode_cpsr (cpu
->CPSR
));
264 cpu
->CPSR
= new_flags
& CPSR_ALL_FLAGS
;
267 /* Read a specific subset of the CPSR as a bit pattern. */
269 aarch64_get_CPSR_bits (sim_cpu
*cpu
, FlagMask mask
)
271 return cpu
->CPSR
& mask
;
274 /* Assign a specific subset of the CPSR as a bit pattern. */
276 aarch64_set_CPSR_bits (sim_cpu
*cpu
, uint32_t mask
, uint32_t value
)
278 uint32_t old_flags
= cpu
->CPSR
;
280 mask
&= CPSR_ALL_FLAGS
;
282 cpu
->CPSR
|= (value
& mask
);
284 if (old_flags
!= cpu
->CPSR
)
286 "CPSR changes from %s to %s",
287 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
290 /* Test the value of a single CPSR returned as non-zero or zero. */
292 aarch64_test_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
294 return cpu
->CPSR
& bit
;
297 /* Set a single flag in the CPSR. */
299 aarch64_set_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
301 uint32_t old_flags
= cpu
->CPSR
;
303 cpu
->CPSR
|= (bit
& CPSR_ALL_FLAGS
);
305 if (old_flags
!= cpu
->CPSR
)
307 "CPSR changes from %s to %s",
308 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
311 /* Clear a single flag in the CPSR. */
313 aarch64_clear_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
315 uint32_t old_flags
= cpu
->CPSR
;
317 cpu
->CPSR
&= ~(bit
& CPSR_ALL_FLAGS
);
319 if (old_flags
!= cpu
->CPSR
)
321 "CPSR changes from %s to %s",
322 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
326 aarch64_get_FP_half (sim_cpu
*cpu
, VReg reg
)
335 u
.h
[1] = cpu
->fr
[reg
].h
[0];
341 aarch64_get_FP_float (sim_cpu
*cpu
, VReg reg
)
343 return cpu
->fr
[reg
].s
;
347 aarch64_get_FP_double (sim_cpu
*cpu
, VReg reg
)
349 return cpu
->fr
[reg
].d
;
353 aarch64_get_FP_long_double (sim_cpu
*cpu
, VReg reg
, FRegister
*a
)
355 a
->v
[0] = cpu
->fr
[reg
].v
[0];
356 a
->v
[1] = cpu
->fr
[reg
].v
[1];
360 aarch64_set_FP_half (sim_cpu
*cpu
, VReg reg
, float val
)
369 cpu
->fr
[reg
].h
[0] = u
.h
[1];
370 cpu
->fr
[reg
].h
[1] = 0;
375 aarch64_set_FP_float (sim_cpu
*cpu
, VReg reg
, float val
)
377 if (val
!= cpu
->fr
[reg
].s
378 /* Handle +/- zero. */
379 || signbit (val
) != signbit (cpu
->fr
[reg
].s
))
385 "FR[%d].s changes from %f to %f [hex: %0" PRIx64
"]",
386 reg
, cpu
->fr
[reg
].s
, val
, v
.v
[0]);
389 cpu
->fr
[reg
].s
= val
;
393 aarch64_set_FP_double (sim_cpu
*cpu
, VReg reg
, double val
)
395 if (val
!= cpu
->fr
[reg
].d
396 /* Handle +/- zero. */
397 || signbit (val
) != signbit (cpu
->fr
[reg
].d
))
403 "FR[%d].d changes from %f to %f [hex: %0" PRIx64
"]",
404 reg
, cpu
->fr
[reg
].d
, val
, v
.v
[0]);
406 cpu
->fr
[reg
].d
= val
;
410 aarch64_set_FP_long_double (sim_cpu
*cpu
, VReg reg
, FRegister a
)
412 if (cpu
->fr
[reg
].v
[0] != a
.v
[0]
413 || cpu
->fr
[reg
].v
[1] != a
.v
[1])
415 "FR[%d].q changes from [%0" PRIx64
" %0" PRIx64
"] to [%0"
416 PRIx64
" %0" PRIx64
"] ",
418 cpu
->fr
[reg
].v
[0], cpu
->fr
[reg
].v
[1],
421 cpu
->fr
[reg
].v
[0] = a
.v
[0];
422 cpu
->fr
[reg
].v
[1] = a
.v
[1];
425 #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \
428 if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
430 TRACE_REGISTER (cpu, \
431 "Internal SIM error: invalid element number: %d ",\
433 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
434 sim_stopped, SIM_SIGBUS); \
436 return cpu->fr[REG].FIELD [ELEMENT]; \
441 aarch64_get_vec_u64 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
443 GET_VEC_ELEMENT (reg
, element
, v
);
447 aarch64_get_vec_u32 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
449 GET_VEC_ELEMENT (reg
, element
, w
);
453 aarch64_get_vec_u16 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
455 GET_VEC_ELEMENT (reg
, element
, h
);
459 aarch64_get_vec_u8 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
461 GET_VEC_ELEMENT (reg
, element
, b
);
465 aarch64_get_vec_s64 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
467 GET_VEC_ELEMENT (reg
, element
, V
);
471 aarch64_get_vec_s32 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
473 GET_VEC_ELEMENT (reg
, element
, W
);
477 aarch64_get_vec_s16 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
479 GET_VEC_ELEMENT (reg
, element
, H
);
483 aarch64_get_vec_s8 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
485 GET_VEC_ELEMENT (reg
, element
, B
);
489 aarch64_get_vec_float (sim_cpu
*cpu
, VReg reg
, unsigned element
)
491 GET_VEC_ELEMENT (reg
, element
, S
);
495 aarch64_get_vec_double (sim_cpu
*cpu
, VReg reg
, unsigned element
)
497 GET_VEC_ELEMENT (reg
, element
, D
);
501 #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \
504 if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
506 TRACE_REGISTER (cpu, \
507 "Internal SIM error: invalid element number: %d ",\
509 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
510 sim_stopped, SIM_SIGBUS); \
512 if (VAL != cpu->fr[REG].FIELD [ELEMENT]) \
513 TRACE_REGISTER (cpu, \
514 "VR[%2d]." #FIELD " [%d] changes from " PRINTER \
515 " to " PRINTER , REG, \
516 ELEMENT, cpu->fr[REG].FIELD [ELEMENT], VAL); \
518 cpu->fr[REG].FIELD [ELEMENT] = VAL; \
523 aarch64_set_vec_u64 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint64_t val
)
525 SET_VEC_ELEMENT (reg
, element
, val
, v
, "%16" PRIx64
);
529 aarch64_set_vec_u32 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint32_t val
)
531 SET_VEC_ELEMENT (reg
, element
, val
, w
, "%8x");
535 aarch64_set_vec_u16 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint16_t val
)
537 SET_VEC_ELEMENT (reg
, element
, val
, h
, "%4x");
541 aarch64_set_vec_u8 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint8_t val
)
543 SET_VEC_ELEMENT (reg
, element
, val
, b
, "%x");
547 aarch64_set_vec_s64 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int64_t val
)
549 SET_VEC_ELEMENT (reg
, element
, val
, V
, "%16" PRIx64
);
553 aarch64_set_vec_s32 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int32_t val
)
555 SET_VEC_ELEMENT (reg
, element
, val
, W
, "%8x");
559 aarch64_set_vec_s16 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int16_t val
)
561 SET_VEC_ELEMENT (reg
, element
, val
, H
, "%4x");
565 aarch64_set_vec_s8 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int8_t val
)
567 SET_VEC_ELEMENT (reg
, element
, val
, B
, "%x");
571 aarch64_set_vec_float (sim_cpu
*cpu
, VReg reg
, unsigned element
, float val
)
573 SET_VEC_ELEMENT (reg
, element
, val
, S
, "%f");
577 aarch64_set_vec_double (sim_cpu
*cpu
, VReg reg
, unsigned element
, double val
)
579 SET_VEC_ELEMENT (reg
, element
, val
, D
, "%f");
583 aarch64_set_FPSR (sim_cpu
*cpu
, uint32_t value
)
585 if (cpu
->FPSR
!= value
)
587 "FPSR changes from %x to %x", cpu
->FPSR
, value
);
589 cpu
->FPSR
= value
& FPSR_ALL_FPSRS
;
593 aarch64_get_FPSR (sim_cpu
*cpu
)
599 aarch64_set_FPSR_bits (sim_cpu
*cpu
, uint32_t mask
, uint32_t value
)
601 uint32_t old_FPSR
= cpu
->FPSR
;
603 mask
&= FPSR_ALL_FPSRS
;
605 cpu
->FPSR
|= (value
& mask
);
607 if (cpu
->FPSR
!= old_FPSR
)
609 "FPSR changes from %x to %x", old_FPSR
, cpu
->FPSR
);
613 aarch64_get_FPSR_bits (sim_cpu
*cpu
, uint32_t mask
)
615 mask
&= FPSR_ALL_FPSRS
;
616 return cpu
->FPSR
& mask
;
620 aarch64_test_FPSR_bit (sim_cpu
*cpu
, FPSRMask flag
)
622 return cpu
->FPSR
& flag
;
626 aarch64_get_thread_id (sim_cpu
*cpu
)
632 aarch64_get_FPCR (sim_cpu
*cpu
)
638 aarch64_set_FPCR (sim_cpu
*cpu
, uint32_t val
)
640 if (cpu
->FPCR
!= val
)
642 "FPCR changes from %x to %x", cpu
->FPCR
, val
);