]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/arm/armdefs.h
1 /* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 3 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, see <http://www.gnu.org/licenses/>. */
29 typedef char *VoidStar
;
34 typedef uint32_t ARMword
;
35 typedef int32_t ARMsword
;
36 typedef uint64_t ARMdword
;
37 typedef int64_t ARMsdword
;
39 typedef unsigned int ARMword
; /* must be 32 bits wide */
40 typedef signed int ARMsword
;
41 typedef unsigned long long ARMdword
; /* Must be at least 64 bits wide. */
42 typedef signed long long ARMsdword
;
44 typedef struct ARMul_State ARMul_State
;
46 typedef unsigned ARMul_CPInits (ARMul_State
* state
);
47 typedef unsigned ARMul_CPExits (ARMul_State
* state
);
48 typedef unsigned ARMul_LDCs (ARMul_State
* state
, unsigned type
,
49 ARMword instr
, ARMword value
);
50 typedef unsigned ARMul_STCs (ARMul_State
* state
, unsigned type
,
51 ARMword instr
, ARMword
* value
);
52 typedef unsigned ARMul_MRCs (ARMul_State
* state
, unsigned type
,
53 ARMword instr
, ARMword
* value
);
54 typedef unsigned ARMul_MCRs (ARMul_State
* state
, unsigned type
,
55 ARMword instr
, ARMword value
);
56 typedef unsigned ARMul_CDPs (ARMul_State
* state
, unsigned type
,
58 typedef unsigned ARMul_CPReads (ARMul_State
* state
, unsigned reg
,
60 typedef unsigned ARMul_CPWrites (ARMul_State
* state
, unsigned reg
,
65 ARMword Emulate
; /* to start and stop emulation */
66 unsigned EndCondition
; /* reason for stopping */
67 unsigned ErrorCode
; /* type of illegal instruction */
68 ARMword Reg
[16]; /* the current register file */
69 ARMword RegBank
[7][16]; /* all the registers */
70 /* 40 bit accumulator. We always keep this 64 bits wide,
71 and move only 40 bits out of it in an MRA insn. */
73 ARMword Cpsr
; /* the current psr */
74 ARMword Spsr
[7]; /* the exception psr's */
75 ARMword NFlag
, ZFlag
, CFlag
, VFlag
, IFFlags
; /* dummy flags for speed */
78 ARMword TFlag
; /* Thumb state */
80 ARMword Bank
; /* the current register bank */
81 ARMword Mode
; /* the current mode */
82 ARMword instr
, pc
, temp
; /* saved register state */
83 ARMword loaded
, decoded
; /* saved pipeline state */
84 unsigned long NumScycles
, NumNcycles
, NumIcycles
, NumCcycles
, NumFcycles
; /* emulated cycles used */
85 unsigned long NumInstrs
; /* the number of instructions executed */
87 unsigned VectorCatch
; /* caught exception mask */
88 unsigned CallDebug
; /* set to call the debugger */
89 unsigned CanWatch
; /* set by memory interface if its willing to suffer the
90 overhead of checking for watchpoints on each memory
92 unsigned MemReadDebug
, MemWriteDebug
;
93 unsigned long StopHandle
;
95 unsigned char *MemDataPtr
; /* admin data */
96 unsigned char *MemInPtr
; /* the Data In bus */
97 unsigned char *MemOutPtr
; /* the Data Out bus (which you may not need */
98 unsigned char *MemSparePtr
; /* extra space */
101 unsigned char *OSptr
; /* OS Handle */
102 char *CommandLine
; /* Command Line from ARMsd */
104 ARMul_CPInits
*CPInit
[16]; /* coprocessor initialisers */
105 ARMul_CPExits
*CPExit
[16]; /* coprocessor finalisers */
106 ARMul_LDCs
*LDC
[16]; /* LDC instruction */
107 ARMul_STCs
*STC
[16]; /* STC instruction */
108 ARMul_MRCs
*MRC
[16]; /* MRC instruction */
109 ARMul_MCRs
*MCR
[16]; /* MCR instruction */
110 ARMul_CDPs
*CDP
[16]; /* CDP instruction */
111 ARMul_CPReads
*CPRead
[16]; /* Read CP register */
112 ARMul_CPWrites
*CPWrite
[16]; /* Write CP register */
113 unsigned char *CPData
[16]; /* Coprocessor data */
114 unsigned char const *CPRegWords
[16]; /* map of coprocessor register sizes */
115 unsigned long LastTime
; /* Value of last call to ARMul_Time() */
116 ARMword CP14R0_CCD
; /* used to count 64 clock cycles with CP14 R0 bit
119 unsigned EventSet
; /* the number of events in the queue */
120 unsigned long Now
; /* time to the nearest cycle */
121 struct EventNode
**EventPtr
; /* the event list */
123 unsigned Exception
; /* enable the next four values */
124 unsigned Debug
; /* show instructions as they are executed */
125 unsigned NresetSig
; /* reset the processor */
135 ARMword Vector
; /* synthesize aborts in cycle modes */
136 ARMword Aborted
; /* sticky flag for aborts */
137 ARMword Reseted
; /* sticky flag for Reset */
138 ARMword Inted
, LastInted
; /* sticky flags for interrupts */
139 ARMword Base
; /* extra hand for base writeback */
140 ARMword AbortAddr
; /* to keep track of Prefetch aborts */
142 const struct Dbg_HostosInterface
*hostif
;
144 unsigned is_v4
; /* Are we emulating a v4 architecture (or higher) ? */
145 unsigned is_v5
; /* Are we emulating a v5 architecture ? */
146 unsigned is_v5e
; /* Are we emulating a v5e architecture ? */
147 unsigned is_v6
; /* Are we emulating a v6 architecture ? */
148 unsigned is_XScale
; /* Are we emulating an XScale architecture ? */
149 unsigned is_iWMMXt
; /* Are we emulating an iWMMXt co-processor ? */
150 unsigned is_ep9312
; /* Are we emulating a Cirrus Maverick co-processor ? */
151 unsigned verbose
; /* Print various messages like the banner */
154 #define ResetPin NresetSig
155 #define FIQPin NfiqSig
156 #define IRQPin NirqSig
157 #define AbortPin abortSig
158 #define TransPin NtransSig
159 #define BigEndPin bigendSig
160 #define Prog32Pin prog32Sig
161 #define Data32Pin data32Sig
162 #define LateAbortPin lateabtSig
164 /***************************************************************************\
165 * Properties of ARM we know about *
166 \***************************************************************************/
169 #define ARM_Fix26_Prop 0x01
170 #define ARM_Nexec_Prop 0x02
171 #define ARM_Debug_Prop 0x10
172 #define ARM_Isync_Prop ARM_Debug_Prop
173 #define ARM_Lock_Prop 0x20
174 #define ARM_v4_Prop 0x40
175 #define ARM_v5_Prop 0x80
176 #define ARM_v5e_Prop 0x100
177 #define ARM_XScale_Prop 0x200
178 #define ARM_ep9312_Prop 0x400
179 #define ARM_iWMMXt_Prop 0x800
180 #define ARM_v6_Prop 0x1000
182 /***************************************************************************\
183 * Macros to extract instruction fields *
184 \***************************************************************************/
186 #define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
187 #define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
188 #define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
190 /***************************************************************************\
191 * The hardware vector addresses *
192 \***************************************************************************/
195 #define ARMUndefinedInstrV 4L
197 #define ARMPrefetchAbortV 12L
198 #define ARMDataAbortV 16L
199 #define ARMAddrExceptnV 20L
202 #define ARMErrorV 32L /* This is an offset, not an address ! */
204 #define ARMul_ResetV ARMResetV
205 #define ARMul_UndefinedInstrV ARMUndefinedInstrV
206 #define ARMul_SWIV ARMSWIV
207 #define ARMul_PrefetchAbortV ARMPrefetchAbortV
208 #define ARMul_DataAbortV ARMDataAbortV
209 #define ARMul_AddrExceptnV ARMAddrExceptnV
210 #define ARMul_IRQV ARMIRQV
211 #define ARMul_FIQV ARMFIQV
213 /***************************************************************************\
214 * Mode and Bank Constants *
215 \***************************************************************************/
217 #define USER26MODE 0L
221 #define USER32MODE 16L
222 #define FIQ32MODE 17L
223 #define IRQ32MODE 18L
224 #define SVC32MODE 19L
225 #define ABORT32MODE 23L
226 #define UNDEF32MODE 27L
227 #define SYSTEMMODE 31L
229 #define ARM32BITMODE (state->Mode > 3)
230 #define ARM26BITMODE (state->Mode <= 3)
231 #define ARMMODE (state->Mode)
232 #define ARMul_MODEBITS 0x1fL
233 #define ARMul_MODE32BIT ARM32BITMODE
234 #define ARMul_MODE26BIT ARM26BITMODE
243 #define SYSTEMBANK USERBANK
245 #define BANK_CAN_ACCESS_SPSR(bank) \
246 ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
248 /***************************************************************************\
249 * Definitons of things in the emulator *
250 \***************************************************************************/
252 extern void ARMul_EmulateInit (void);
253 extern ARMul_State
*ARMul_NewState (void);
254 extern void ARMul_Reset (ARMul_State
* state
);
255 extern ARMword
ARMul_DoProg (ARMul_State
* state
);
256 extern ARMword
ARMul_DoInstr (ARMul_State
* state
);
258 /***************************************************************************\
259 * Definitons of things for event handling *
260 \***************************************************************************/
262 extern void ARMul_ScheduleEvent (ARMul_State
* state
, unsigned long delay
,
263 unsigned (*func
) ());
264 extern void ARMul_EnvokeEvent (ARMul_State
* state
);
265 extern unsigned long ARMul_Time (ARMul_State
* state
);
267 /***************************************************************************\
268 * Useful support routines *
269 \***************************************************************************/
271 extern ARMword
ARMul_GetReg (ARMul_State
* state
, unsigned mode
,
273 extern void ARMul_SetReg (ARMul_State
* state
, unsigned mode
, unsigned reg
,
275 extern ARMword
ARMul_GetPC (ARMul_State
* state
);
276 extern ARMword
ARMul_GetNextPC (ARMul_State
* state
);
277 extern void ARMul_SetPC (ARMul_State
* state
, ARMword value
);
278 extern ARMword
ARMul_GetR15 (ARMul_State
* state
);
279 extern void ARMul_SetR15 (ARMul_State
* state
, ARMword value
);
281 extern ARMword
ARMul_GetCPSR (ARMul_State
* state
);
282 extern void ARMul_SetCPSR (ARMul_State
* state
, ARMword value
);
283 extern ARMword
ARMul_GetSPSR (ARMul_State
* state
, ARMword mode
);
284 extern void ARMul_SetSPSR (ARMul_State
* state
, ARMword mode
, ARMword value
);
286 /***************************************************************************\
287 * Definitons of things to handle aborts *
288 \***************************************************************************/
290 extern void ARMul_Abort (ARMul_State
* state
, ARMword address
);
291 #define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
292 #define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
293 state->AbortAddr = (address & ~3L)
294 #define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
295 state->Aborted = ARMul_DataAbortV ;
296 #define ARMul_CLEARABORT state->abortSig = LOW
298 /***************************************************************************\
299 * Definitons of things in the memory interface *
300 \***************************************************************************/
302 extern unsigned ARMul_MemoryInit (ARMul_State
* state
,
303 unsigned long initmemsize
);
304 extern void ARMul_MemoryExit (ARMul_State
* state
);
306 extern ARMword
ARMul_LoadInstrS (ARMul_State
* state
, ARMword address
,
308 extern ARMword
ARMul_LoadInstrN (ARMul_State
* state
, ARMword address
,
310 extern ARMword
ARMul_ReLoadInstr (ARMul_State
* state
, ARMword address
,
313 extern ARMword
ARMul_LoadWordS (ARMul_State
* state
, ARMword address
);
314 extern ARMword
ARMul_LoadWordN (ARMul_State
* state
, ARMword address
);
315 extern ARMword
ARMul_LoadHalfWord (ARMul_State
* state
, ARMword address
);
316 extern ARMword
ARMul_LoadByte (ARMul_State
* state
, ARMword address
);
318 extern void ARMul_StoreWordS (ARMul_State
* state
, ARMword address
,
320 extern void ARMul_StoreWordN (ARMul_State
* state
, ARMword address
,
322 extern void ARMul_StoreHalfWord (ARMul_State
* state
, ARMword address
,
324 extern void ARMul_StoreByte (ARMul_State
* state
, ARMword address
,
327 extern ARMword
ARMul_SwapWord (ARMul_State
* state
, ARMword address
,
329 extern ARMword
ARMul_SwapByte (ARMul_State
* state
, ARMword address
,
332 extern void ARMul_Icycles (ARMul_State
* state
, unsigned number
,
334 extern void ARMul_Ccycles (ARMul_State
* state
, unsigned number
,
337 extern ARMword
ARMul_ReadWord (ARMul_State
* state
, ARMword address
);
338 extern ARMword
ARMul_ReadByte (ARMul_State
* state
, ARMword address
);
339 extern ARMword
ARMul_SafeReadByte (ARMul_State
* state
, ARMword address
);
340 extern void ARMul_WriteWord (ARMul_State
* state
, ARMword address
,
342 extern void ARMul_WriteByte (ARMul_State
* state
, ARMword address
,
344 extern void ARMul_SafeWriteByte (ARMul_State
* state
, ARMword address
,
347 extern ARMword
ARMul_MemAccess (ARMul_State
* state
, ARMword
, ARMword
,
348 ARMword
, ARMword
, ARMword
, ARMword
, ARMword
,
349 ARMword
, ARMword
, ARMword
);
351 /***************************************************************************\
352 * Definitons of things in the co-processor interface *
353 \***************************************************************************/
355 #define ARMul_FIRST 0
356 #define ARMul_TRANSFER 1
359 #define ARMul_INTERRUPT 4
364 #define ARMul_CP13_R0_FIQ 0x1
365 #define ARMul_CP13_R0_IRQ 0x2
366 #define ARMul_CP13_R8_PMUS 0x1
368 #define ARMul_CP14_R0_ENABLE 0x0001
369 #define ARMul_CP14_R0_CLKRST 0x0004
370 #define ARMul_CP14_R0_CCD 0x0008
371 #define ARMul_CP14_R0_INTEN0 0x0010
372 #define ARMul_CP14_R0_INTEN1 0x0020
373 #define ARMul_CP14_R0_INTEN2 0x0040
374 #define ARMul_CP14_R0_FLAG0 0x0100
375 #define ARMul_CP14_R0_FLAG1 0x0200
376 #define ARMul_CP14_R0_FLAG2 0x0400
377 #define ARMul_CP14_R10_MOE_IB 0x0004
378 #define ARMul_CP14_R10_MOE_DB 0x0008
379 #define ARMul_CP14_R10_MOE_BT 0x000c
380 #define ARMul_CP15_R1_ENDIAN 0x0080
381 #define ARMul_CP15_R1_ALIGN 0x0002
382 #define ARMul_CP15_R5_X 0x0400
383 #define ARMul_CP15_R5_ST_ALIGN 0x0001
384 #define ARMul_CP15_R5_IMPRE 0x0406
385 #define ARMul_CP15_R5_MMU_EXCPT 0x0400
386 #define ARMul_CP15_DBCON_M 0x0100
387 #define ARMul_CP15_DBCON_E1 0x000c
388 #define ARMul_CP15_DBCON_E0 0x0003
390 extern unsigned ARMul_CoProInit (ARMul_State
* state
);
391 extern void ARMul_CoProExit (ARMul_State
* state
);
392 extern void ARMul_CoProAttach (ARMul_State
* state
, unsigned number
,
393 ARMul_CPInits
* init
, ARMul_CPExits
* exit
,
394 ARMul_LDCs
* ldc
, ARMul_STCs
* stc
,
395 ARMul_MRCs
* mrc
, ARMul_MCRs
* mcr
,
397 ARMul_CPReads
* read
, ARMul_CPWrites
* write
);
398 extern void ARMul_CoProDetach (ARMul_State
* state
, unsigned number
);
399 extern void XScale_check_memacc (ARMul_State
* state
, ARMword
* address
,
401 extern void XScale_set_fsr_far (ARMul_State
* state
, ARMword fsr
, ARMword far
);
402 extern int XScale_debug_moe (ARMul_State
* state
, int moe
);
404 /***************************************************************************\
405 * Definitons of things in the host environment *
406 \***************************************************************************/
408 extern unsigned ARMul_OSInit (ARMul_State
* state
);
409 extern void ARMul_OSExit (ARMul_State
* state
);
410 extern unsigned ARMul_OSHandleSWI (ARMul_State
* state
, ARMword number
);
411 extern ARMword
ARMul_OSLastErrorP (ARMul_State
* state
);
413 extern ARMword
ARMul_Debug (ARMul_State
* state
, ARMword pc
, ARMword instr
);
414 extern unsigned ARMul_OSException (ARMul_State
* state
, ARMword vector
,
418 /***************************************************************************\
419 * Host-dependent stuff *
420 \***************************************************************************/
423 pascal void SpinCursor (short increment
); /* copied from CursorCtl.h */
424 # define HOURGLASS SpinCursor( 1 )
425 # define HOURGLASS_RATE 1023 /* 2^n - 1 */
428 extern void ARMul_UndefInstr (ARMul_State
*, ARMword
);
429 extern void ARMul_FixCPSR (ARMul_State
*, ARMword
, ARMword
);
430 extern void ARMul_FixSPSR (ARMul_State
*, ARMword
, ARMword
);
431 extern void ARMul_ConsolePrint (ARMul_State
*, const char *, ...);
432 extern void ARMul_SelectProcessor (ARMul_State
*, unsigned);