sim/arm/arminit.c

   1 /*  arminit.c -- ARMulator initialization:  ARM6 Instruction Emulator.
   2     Copyright (C) 1994 Advanced RISC Machines Ltd.
   3
   4     This program is free software; you can redistribute it and/or modify
   5     it under the terms of the GNU General Public License as published by
   6     the Free Software Foundation; either version 2 of the License, or
   7     (at your option) any later version.
   8
   9     This program is distributed in the hope that it will be useful,
  10     but WITHOUT ANY WARRANTY; without even the implied warranty of
  11     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12     GNU General Public License for more details.
  13
  14     You should have received a copy of the GNU General Public License
  15     along with this program; if not, write to the Free Software
  16     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  17
  18 #include "armdefs.h"
  19 #include "armemu.h"
  20
  21 /***************************************************************************\
  22 *                 Definitions for the emulator architecture                 *
  23 \***************************************************************************/
  24
  25 void ARMul_EmulateInit (void);
  26 ARMul_State *ARMul_NewState (void);
  27 void ARMul_Reset (ARMul_State * state);
  28 ARMword ARMul_DoCycle (ARMul_State * state);
  29 unsigned ARMul_DoCoPro (ARMul_State * state);
  30 ARMword ARMul_DoProg (ARMul_State * state);
  31 ARMword ARMul_DoInstr (ARMul_State * state);
  32 void ARMul_Abort (ARMul_State * state, ARMword address);
  33
  34 unsigned ARMul_MultTable[32] =
  35   { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
  36   10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
  37 };
  38 ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */
  39 char ARMul_BitList[256];        /* number of bits in a byte table */
  40
  41 /***************************************************************************\
  42 *         Call this routine once to set up the emulator's tables.           *
  43 \***************************************************************************/
  44
  45 void
  46 ARMul_EmulateInit (void)
  47 {
  48   unsigned long i, j;
  49
  50   for (i = 0; i < 4096; i++)
  51     {                           /* the values of 12 bit dp rhs's */
  52       ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL);
  53     }
  54
  55   for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */
  56   for (j = 1; j < 256; j <<= 1)
  57     for (i = 0; i < 256; i++)
  58       if ((i & j) > 0)
  59         ARMul_BitList[i]++;
  60
  61   for (i = 0; i < 256; i++)
  62     ARMul_BitList[i] *= 4;      /* you always need 4 times these values */
  63
  64 }
  65
  66 /***************************************************************************\
  67 *            Returns a new instantiation of the ARMulator's state           *
  68 \***************************************************************************/
  69
  70 ARMul_State *
  71 ARMul_NewState (void)
  72 {
  73   ARMul_State *state;
  74   unsigned i, j;
  75
  76   state = (ARMul_State *) malloc (sizeof (ARMul_State));
  77   memset (state, 0, sizeof (ARMul_State));
  78
  79   state->Emulate = RUN;
  80   for (i = 0; i < 16; i++)
  81     {
  82       state->Reg[i] = 0;
  83       for (j = 0; j < 7; j++)
  84         state->RegBank[j][i] = 0;
  85     }
  86   for (i = 0; i < 7; i++)
  87     state->Spsr[i] = 0;
  88
  89   /* state->Mode = USER26MODE;  */
  90   state->Mode = USER32MODE;
  91
  92   state->CallDebug = FALSE;
  93   state->Debug = FALSE;
  94   state->VectorCatch = 0;
  95   state->Aborted = FALSE;
  96   state->Reseted = FALSE;
  97   state->Inted = 3;
  98   state->LastInted = 3;
  99
 100   state->MemDataPtr = NULL;
 101   state->MemInPtr = NULL;
 102   state->MemOutPtr = NULL;
 103   state->MemSparePtr = NULL;
 104   state->MemSize = 0;
 105
 106   state->OSptr = NULL;
 107   state->CommandLine = NULL;
 108
 109   state->CP14R0_CCD = -1;
 110   state->LastTime = 0;
 111
 112   state->EventSet = 0;
 113   state->Now = 0;
 114   state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
 115                                                   sizeof (struct EventNode
 116                                                           *));
 117   for (i = 0; i < EVENTLISTSIZE; i++)
 118     *(state->EventPtr + i) = NULL;
 119
 120   state->prog32Sig = HIGH;
 121   state->data32Sig = HIGH;
 122
 123   state->lateabtSig = LOW;
 124   state->bigendSig = LOW;
 125
 126   state->is_v4 = LOW;
 127   state->is_v5 = LOW;
 128   state->is_v5e = LOW;
 129   state->is_XScale = LOW;
 130
 131   ARMul_Reset (state);
 132
 133   return state;
 134 }
 135
 136 /***************************************************************************\
 137   Call this routine to set ARMulator to model certain processor properities
 138 \***************************************************************************/
 139
 140 void
 141 ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
 142 {
 143   if (properties & ARM_Fix26_Prop)
 144     {
 145       state->prog32Sig = LOW;
 146       state->data32Sig = LOW;
 147     }
 148   else
 149     {
 150       state->prog32Sig = HIGH;
 151       state->data32Sig = HIGH;
 152     }
 153
 154   state->lateabtSig = LOW;
 155
 156   state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW;
 157   state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
 158   state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
 159   state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW;
 160   state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW;
 161
 162   /* Only initialse the coprocessor support once we
 163      know what kind of chip we are dealing with.  */
 164   ARMul_CoProInit (state);
 165 }
 166
 167 /***************************************************************************\
 168 * Call this routine to set up the initial machine state (or perform a RESET *
 169 \***************************************************************************/
 170
 171 void
 172 ARMul_Reset (ARMul_State * state)
 173 {
 174   state->NextInstr = 0;
 175
 176   if (state->prog32Sig)
 177     {
 178       state->Reg[15] = 0;
 179       state->Cpsr = INTBITS | SVC32MODE;
 180       state->Mode = SVC32MODE;
 181     }
 182   else
 183     {
 184       state->Reg[15] = R15INTBITS | SVC26MODE;
 185       state->Cpsr = INTBITS | SVC26MODE;
 186       state->Mode = SVC26MODE;
 187     }
 188
 189   ARMul_CPSRAltered (state);
 190   state->Bank = SVCBANK;
 191
 192   FLUSHPIPE;
 193
 194   state->EndCondition = 0;
 195   state->ErrorCode = 0;
 196
 197   state->Exception = FALSE;
 198   state->NresetSig = HIGH;
 199   state->NfiqSig = HIGH;
 200   state->NirqSig = HIGH;
 201   state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
 202   state->abortSig = LOW;
 203   state->AbortAddr = 1;
 204
 205   state->NumInstrs = 0;
 206   state->NumNcycles = 0;
 207   state->NumScycles = 0;
 208   state->NumIcycles = 0;
 209   state->NumCcycles = 0;
 210   state->NumFcycles = 0;
 211 #ifdef ASIM
 212   (void) ARMul_MemoryInit ();
 213   ARMul_OSInit (state);
 214 #endif
 215 }
 216
 217
 218 /***************************************************************************\
 219 * Emulate the execution of an entire program.  Start the correct emulator   *
 220 * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the   *
 221 * address of the last instruction that is executed.                         *
 222 \***************************************************************************/
 223
 224 ARMword
 225 ARMul_DoProg (ARMul_State * state)
 226 {
 227   ARMword pc = 0;
 228
 229   state->Emulate = RUN;
 230   while (state->Emulate != STOP)
 231     {
 232       state->Emulate = RUN;
 233       if (state->prog32Sig && ARMul_MODE32BIT)
 234         pc = ARMul_Emulate32 (state);
 235       else
 236         pc = ARMul_Emulate26 (state);
 237     }
 238   return (pc);
 239 }
 240
 241 /***************************************************************************\
 242 * Emulate the execution of one instruction.  Start the correct emulator     *
 243 * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the   *
 244 * address of the instruction that is executed.                              *
 245 \***************************************************************************/
 246
 247 ARMword
 248 ARMul_DoInstr (ARMul_State * state)
 249 {
 250   ARMword pc = 0;
 251
 252   state->Emulate = ONCE;
 253   if (state->prog32Sig && ARMul_MODE32BIT)
 254     pc = ARMul_Emulate32 (state);
 255   else
 256     pc = ARMul_Emulate26 (state);
 257
 258   return (pc);
 259 }
 260
 261 /***************************************************************************\
 262 * This routine causes an Abort to occur, including selecting the correct    *
 263 * mode, register bank, and the saving of registers.  Call with the          *
 264 * appropriate vector's memory address (0,4,8 ....)                          *
 265 \***************************************************************************/
 266
 267 void
 268 ARMul_Abort (ARMul_State * state, ARMword vector)
 269 {
 270   ARMword temp;
 271   int isize = INSN_SIZE;
 272   int esize = (TFLAG ? 0 : 4);
 273   int e2size = (TFLAG ? -4 : 0);
 274
 275   state->Aborted = FALSE;
 276
 277   if (ARMul_OSException (state, vector, ARMul_GetPC (state)))
 278     return;
 279
 280   if (state->prog32Sig)
 281     if (ARMul_MODE26BIT)
 282       temp = R15PC;
 283     else
 284       temp = state->Reg[15];
 285   else
 286     temp = R15PC | ECC | ER15INT | EMODE;
 287
 288   switch (vector)
 289     {
 290     case ARMul_ResetV:          /* RESET */
 291       SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0);
 292       break;
 293     case ARMul_UndefinedInstrV: /* Undefined Instruction */
 294       SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize);
 295       break;
 296     case ARMul_SWIV:            /* Software Interrupt */
 297       SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize);
 298       break;
 299     case ARMul_PrefetchAbortV:  /* Prefetch Abort */
 300       state->AbortAddr = 1;
 301       SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize);
 302       break;
 303     case ARMul_DataAbortV:      /* Data Abort */
 304       SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size);
 305       break;
 306     case ARMul_AddrExceptnV:    /* Address Exception */
 307       SETABORT (IBIT, SVC26MODE, isize);
 308       break;
 309     case ARMul_IRQV:            /* IRQ */
 310       if (   ! state->is_XScale
 311           || ! state->CPRead[13] (state, 0, & temp)
 312           || (temp & ARMul_CP13_R0_IRQ))
 313         SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
 314       break;
 315     case ARMul_FIQV:            /* FIQ */
 316       if (   ! state->is_XScale
 317           || ! state->CPRead[13] (state, 0, & temp)
 318           || (temp & ARMul_CP13_R0_FIQ))
 319         SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
 320       break;
 321     }
 322   if (ARMul_MODE32BIT)
 323     ARMul_SetR15 (state, vector);
 324   else
 325     ARMul_SetR15 (state, R15CCINTMODE | vector);
 326 }