sim/common/cgen-engine.h

   1 /* Engine header for Cpu tools GENerated simulators.
   2    Copyright (C) 1998-2023 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* This file is included by ${cpu}.h.
  21    It needs CGEN_INSN_WORD which is defined by ${cpu}.h.
  22    ??? A lot of this could be moved to genmloop.sh to be put in eng.h
  23    and thus remove some conditional compilation.  We'd still need
  24    CGEN_INSN_WORD though.  */
  25
  26 /* Semantic functions come in six versions on two axes:
  27    fast/full-featured, and using one of the simple/scache/compilation engines.
  28    A full featured simulator is always provided.  --enable-sim-fast includes
  29    support for fast execution by duplicating the semantic code but leaving
  30    out all features like tracing and profiling.
  31    Using the scache is selected with --enable-sim-scache.  */
  32 /* FIXME: --enable-sim-fast not implemented yet.  */
  33 /* FIXME: undecided how to handle WITH_SCACHE_PBB.  */
  34
  35 /* There are several styles of engines, all generally supported by the
  36    same code:
  37
  38    WITH_SCACHE && WITH_SCACHE_PBB - pseudo-basic-block scaching
  39    WITH_SCACHE && !WITH_SCACHE_PBB - scaching on an insn by insn basis
  40    !WITH_SCACHE - simple engine: fetch an insn, execute an insn
  41
  42    The !WITH_SCACHE case can also be broken up into two flavours:
  43    extract the fields of the insn into an ARGBUF struct, or defer the
  44    extraction to the semantic handler.  The former can be viewed as the
  45    WITH_SCACHE case with a cache size of 1 (thus there's no need for a
  46    WITH_EXTRACTION macro).  The WITH_SCACHE case always extracts the fields
  47    into an ARGBUF struct.  */
  48
  49 #ifndef CGEN_ENGINE_H
  50 #define CGEN_ENGINE_H
  51
  52 /* Instruction field support macros.  */
  53
  54 #define EXTRACT_MSB0_SINT(val, total, start, length) \
  55 (((INT) (val) << ((sizeof (INT) * 8) - (total) + (start))) \
  56  >> ((sizeof (INT) * 8) - (length)))
  57 #define EXTRACT_MSB0_UINT(val, total, start, length) \
  58 (((UINT) (val) << ((sizeof (UINT) * 8) - (total) + (start))) \
  59  >> ((sizeof (UINT) * 8) - (length)))
  60
  61 #define EXTRACT_LSB0_SINT(val, total, start, length) \
  62 (((INT) (val) << ((sizeof (INT) * 8) - (start) - 1)) \
  63  >> ((sizeof (INT) * 8) - (length)))
  64 #define EXTRACT_LSB0_UINT(val, total, start, length) \
  65 (((UINT) (val) << ((sizeof (UINT) * 8) - (start) - 1)) \
  66  >> ((sizeof (UINT) * 8) - (length)))
  67
  68 #define EXTRACT_MSB0_LGSINT(val, total, start, length) \
  69 (((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (total) + (start))) \
  70  >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
  71 #define EXTRACT_MSB0_LGUINT(val, total, start, length) \
  72 (((CGEN_INSN_UINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (total) + (start))) \
  73  >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
  74
  75 #define EXTRACT_LSB0_LGSINT(val, total, start, length) \
  76 (((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (start) - 1)) \
  77  >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
  78 #define EXTRACT_LSB0_LGUINT(val, total, start, length) \
  79 (((CGEN_INSN_LGUINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (start) - 1)) \
  80  >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
  81 \f
  82 /* Semantic routines.  */
  83
  84 /* Type of the machine generated extraction fns.  */
  85 /* ??? No longer used.  */
  86 typedef void (EXTRACT_FN) (SIM_CPU *, IADDR, CGEN_INSN_WORD, ARGBUF *);
  87
  88 /* Type of the machine generated semantic fns.  */
  89
  90 #if WITH_SCACHE
  91
  92 /* Instruction fields are extracted into ARGBUF before calling the
  93    semantic routine.  */
  94 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
  95 typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *);
  96 #else
  97 typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG);
  98 #endif
  99
 100 #else
 101
 102 /* Result of semantic routines is a status indicator (wip).  */
 103 typedef unsigned int SEM_STATUS;
 104
 105 /* Instruction fields are extracted by the semantic routine.
 106    ??? TODO: multi word insns.  */
 107 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
 108 typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *, CGEN_INSN_WORD);
 109 #else
 110 typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, CGEN_INSN_WORD);
 111 #endif
 112
 113 #endif
 114
 115 /* In the ARGBUF struct, a pointer to the semantic routine for the insn.  */
 116
 117 union sem {
 118 #if ! WITH_SEM_SWITCH_FULL
 119   SEMANTIC_FN *sem_full;
 120 #endif
 121 #if ! WITH_SEM_SWITCH_FAST
 122   SEMANTIC_FN *sem_fast;
 123 #endif
 124 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
 125 #ifdef __GNUC__
 126   void *sem_case;
 127 #else
 128   int sem_case;
 129 #endif
 130 #endif
 131 };
 132
 133 /* Set the appropriate semantic handler in ABUF.  */
 134
 135 #if WITH_SEM_SWITCH_FULL
 136 #ifdef __GNUC__
 137 #define SEM_SET_FULL_CODE(abuf, idesc) \
 138   do { (abuf)->semantic.sem_case = (idesc)->sem_full_lab; } while (0)
 139 #else
 140 #define SEM_SET_FULL_CODE(abuf, idesc) \
 141   do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
 142 #endif
 143 #else
 144 #define SEM_SET_FULL_CODE(abuf, idesc) \
 145   do { (abuf)->semantic.sem_full = (idesc)->sem_full; } while (0)
 146 #endif
 147
 148 #if WITH_SEM_SWITCH_FAST
 149 #ifdef __GNUC__
 150 #define SEM_SET_FAST_CODE(abuf, idesc) \
 151   do { (abuf)->semantic.sem_case = (idesc)->sem_fast_lab; } while (0)
 152 #else
 153 #define SEM_SET_FAST_CODE(abuf, idesc) \
 154   do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
 155 #endif
 156 #else
 157 #define SEM_SET_FAST_CODE(abuf, idesc) \
 158   do { (abuf)->semantic.sem_fast = (idesc)->sem_fast; } while (0)
 159 #endif
 160
 161 #define SEM_SET_CODE(abuf, idesc, fast_p) \
 162 do { \
 163   if (fast_p) \
 164     SEM_SET_FAST_CODE ((abuf), (idesc)); \
 165   else \
 166     SEM_SET_FULL_CODE ((abuf), (idesc)); \
 167 } while (0)
 168 \f
 169 /* Return non-zero if IDESC is a conditional or unconditional CTI.  */
 170
 171 #define IDESC_CTI_P(idesc) \
 172      ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \
 173        & (CGEN_ATTR_MASK (CGEN_INSN_COND_CTI) \
 174           | CGEN_ATTR_MASK (CGEN_INSN_UNCOND_CTI))) \
 175       != 0)
 176
 177 /* Return non-zero if IDESC is a skip insn.  */
 178
 179 #define IDESC_SKIP_P(idesc) \
 180      ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \
 181        & CGEN_ATTR_MASK (CGEN_INSN_SKIP_CTI)) \
 182       != 0)
 183
 184 /* Return pointer to ARGBUF given ptr to SCACHE.  */
 185 #define SEM_ARGBUF(sem_arg) (& (sem_arg) -> argbuf)
 186
 187 #if WITH_SCACHE
 188
 189 #if WITH_SCACHE_PBB
 190
 191 /* Return the scache pointer of the current insn.  */
 192 #define SEM_SEM_ARG(vpc, sc) (vpc)
 193
 194 /* Return the virtual pc of the next insn to execute
 195    (assuming this isn't a cti or the branch isn't taken).  */
 196 #define SEM_NEXT_VPC(sem_arg, pc, len) ((sem_arg) + 1)
 197
 198 /* Update the instruction counter.  */
 199 #define PBB_UPDATE_INSN_COUNT(cpu,sc) \
 200   (CPU_INSN_COUNT (cpu) += SEM_ARGBUF (sc) -> fields.chain.insn_count)
 201
 202 /* Do not append a `;' to invocations of this.
 203    npc,br_type are for communication between the cti insn and cti-chain.  */
 204 #define SEM_BRANCH_INIT \
 205   IADDR npc = 0; /* assign a value for -Wall */ \
 206   SEM_BRANCH_TYPE br_type = SEM_BRANCH_UNTAKEN;
 207
 208 /* SEM_IN_SWITCH is defined at the top of the mainloop.c files
 209    generated by genmloop.sh.  It exists so generated semantic code needn't
 210    care whether it's being put in a switch or in a function.  */
 211 #ifdef SEM_IN_SWITCH
 212 #define SEM_BRANCH_FINI(pcvar) \
 213 do { \
 214   pbb_br_npc = npc; \
 215   pbb_br_type = br_type; \
 216 } while (0)
 217 #else /* 1 semantic function per instruction */
 218 #define SEM_BRANCH_FINI(pcvar) \
 219 do { \
 220   CPU_PBB_BR_NPC (current_cpu) = npc; \
 221   CPU_PBB_BR_TYPE (current_cpu) = br_type; \
 222 } while (0)
 223 #endif
 224
 225 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
 226 do { \
 227   npc = (newval); \
 228   br_type = SEM_BRANCH_CACHEABLE; \
 229 } while (0)
 230
 231 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
 232 do { \
 233   npc = (newval); \
 234   br_type = SEM_BRANCH_UNCACHEABLE; \
 235 } while (0)
 236
 237 #define SEM_SKIP_COMPILE(cpu, sc, skip) \
 238 do { \
 239   SEM_ARGBUF (sc) -> skip_count = (skip); \
 240 } while (0)
 241
 242 #define SEM_SKIP_INSN(cpu, sc, vpcvar) \
 243 do { \
 244   (vpcvar) += SEM_ARGBUF (sc) -> skip_count; \
 245 } while (0)
 246
 247 #else /* ! WITH_SCACHE_PBB */
 248
 249 #define SEM_SEM_ARG(vpc, sc) (sc)
 250
 251 #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
 252
 253 /* ??? May wish to move taken_p out of here and make it explicit.  */
 254 #define SEM_BRANCH_INIT \
 255   int taken_p = 0;
 256
 257 #ifndef TARGET_SEM_BRANCH_FINI
 258 #define TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
 259 #endif
 260 #define SEM_BRANCH_FINI(pcvar) \
 261   do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0)
 262
 263 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
 264 do { \
 265   (pcvar) = (newval); \
 266   taken_p = 1; \
 267 } while (0)
 268
 269 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
 270 do { \
 271   (pcvar) = (newval); \
 272   taken_p = 1; \
 273 } while (0)
 274
 275 #endif /* ! WITH_SCACHE_PBB */
 276
 277 #else /* ! WITH_SCACHE */
 278
 279 /* This is the "simple" engine case.  */
 280
 281 #define SEM_SEM_ARG(vpc, sc) (sc)
 282
 283 #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
 284
 285 #define SEM_BRANCH_INIT \
 286   int taken_p = 0;
 287
 288 #define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar) \
 289 do { \
 290   (pcvar) = (newval); \
 291   taken_p = 1; \
 292 } while (0)
 293
 294 #define SEM_BRANCH_VIA_ADDR(cpu, abuf, newval, pcvar) \
 295 do { \
 296   (pcvar) = (newval); \
 297   taken_p = 1; \
 298 } while (0)
 299
 300 /* Finish off branch insns.
 301    The target must define TARGET_SEM_BRANCH_FINI.
 302    ??? This can probably go away when define-execute is finished.  */
 303 #define SEM_BRANCH_FINI(pcvar, bool_attrs) \
 304   do { TARGET_SEM_BRANCH_FINI ((pcvar), (bool_attrs), taken_p); } while (0)
 305
 306 /* Finish off non-branch insns.
 307    The target must define TARGET_SEM_NBRANCH_FINI.
 308    ??? This can probably go away when define-execute is finished.  */
 309 #define SEM_NBRANCH_FINI(pcvar, bool_attrs) \
 310   do { TARGET_SEM_NBRANCH_FINI ((pcvar), (bool_attrs)); } while (0)
 311
 312 #endif /* ! WITH_SCACHE */
 313 \f
 314 /* Instruction information.  */
 315
 316 /* Sanity check, at most one of these may be true.  */
 317 #if WITH_PARALLEL_READ + WITH_PARALLEL_WRITE + WITH_PARALLEL_GENWRITE > 1
 318 #error "At most one of WITH_PARALLEL_{READ,WRITE,GENWRITE} can be true."
 319 #endif
 320
 321 /* Compile time computable instruction data.  */
 322
 323 struct insn_sem {
 324   /* The instruction type (a number that identifies each insn over the
 325      entire architecture).  */
 326   CGEN_INSN_TYPE type;
 327
 328   /* Index in IDESC table.  */
 329   int index;
 330
 331   /* Semantic format number.  */
 332   int sfmt;
 333
 334 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_ONLY
 335   /* Index in IDESC table of parallel handler.  */
 336   int par_index;
 337 #endif
 338
 339 #if WITH_PARALLEL_READ
 340   /* Index in IDESC table of read handler.  */
 341   int read_index;
 342 #endif
 343
 344 #if WITH_PARALLEL_WRITE
 345   /* Index in IDESC table of writeback handler.  */
 346   int write_index;
 347 #endif
 348 };
 349
 350 /* Entry in semantic function table.
 351    This information is copied to the insn descriptor table at run-time.  */
 352
 353 struct sem_fn_desc {
 354   /* Index in IDESC table.  */
 355   int index;
 356
 357   /* Function to perform the semantics of the insn.  */
 358   SEMANTIC_FN *fn;
 359 };
 360
 361 /* Run-time computed instruction descriptor.  */
 362
 363 struct idesc {
 364 #if WITH_SEM_SWITCH_FAST
 365 #ifdef __GNUC__
 366   void *sem_fast_lab;
 367 #else
 368   /* nothing needed, switch's on `num' member */
 369 #endif
 370 #else
 371   SEMANTIC_FN *sem_fast;
 372 #endif
 373
 374 #if WITH_SEM_SWITCH_FULL
 375 #ifdef __GNUC__
 376   void *sem_full_lab;
 377 #else
 378   /* nothing needed, switch's on `num' member */
 379 #endif
 380 #else
 381   SEMANTIC_FN *sem_full;
 382 #endif
 383
 384   /* Parallel support.  */
 385 #if HAVE_PARALLEL_INSNS && (! WITH_PARALLEL_ONLY || (WITH_PARALLEL_ONLY && ! WITH_PARALLEL_GENWRITE))
 386   /* Pointer to parallel handler if serial insn.
 387      Pointer to readahead/writeback handler if parallel insn.  */
 388   struct idesc *par_idesc;
 389 #endif
 390
 391   /* Instruction number (index in IDESC table, profile table).
 392      Also used to switch on in non-gcc semantic switches.  */
 393   int num;
 394
 395   /* Semantic format id.  */
 396   int sfmt;
 397
 398   /* instruction data (name, attributes, size, etc.) */
 399   const CGEN_INSN *idata;
 400
 401   /* instruction attributes, copied from `idata' for speed */
 402   const CGEN_INSN_ATTR_TYPE *attrs;
 403
 404   /* instruction length in bytes, copied from `idata' for speed */
 405   int length;
 406
 407   /* profiling/modelling support */
 408   const INSN_TIMING *timing;
 409 };
 410 \f
 411 /* Tracing/profiling.  */
 412
 413 /* Return non-zero if a before/after handler is needed.
 414    When tracing/profiling a selected range there's no need to slow
 415    down simulation of the other insns (except to get more accurate data!).
 416
 417    ??? May wish to profile all insns if doing insn tracing, or to
 418    get more accurate cycle data.
 419
 420    First test ANY_P so we avoid a potentially expensive HIT_P call
 421    [if there are lots of address ranges].  */
 422
 423 #define PC_IN_TRACE_RANGE_P(cpu, pc) \
 424   (TRACE_ANY_P (cpu) \
 425    && ADDR_RANGE_HIT_P (TRACE_RANGE (CPU_TRACE_DATA (cpu)), (pc)))
 426 #define PC_IN_PROFILE_RANGE_P(cpu, pc) \
 427   (PROFILE_ANY_P (cpu) \
 428    && ADDR_RANGE_HIT_P (PROFILE_RANGE (CPU_PROFILE_DATA (cpu)), (pc)))
 429
 430 #endif /* CGEN_ENGINE_H */