sim/common/cgen-trace.c

   1 /* Tracing support for CGEN-based simulators.
   2    Copyright (C) 1996-2021 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* This must come before any other includes.  */
  21 #include "defs.h"
  22
  23 #include <errno.h>
  24 #include <stdlib.h>
  25 #include "dis-asm.h"
  26 #include "bfd.h"
  27 #include "sim-main.h"
  28 #include "sim-fpu.h"
  29 #include "sim/callback.h"
  30
  31 #ifndef SIZE_INSTRUCTION
  32 #define SIZE_INSTRUCTION 16
  33 #endif
  34
  35 #ifndef SIZE_LOCATION
  36 #define SIZE_LOCATION 20
  37 #endif
  38
  39 #ifndef SIZE_PC
  40 #define SIZE_PC 6
  41 #endif
  42
  43 #ifndef SIZE_LINE_NUMBER
  44 #define SIZE_LINE_NUMBER 4
  45 #endif
  46
  47 #ifndef SIZE_CYCLE_COUNT
  48 #define SIZE_CYCLE_COUNT 2
  49 #endif
  50
  51 #ifndef SIZE_TOTAL_CYCLE_COUNT
  52 #define SIZE_TOTAL_CYCLE_COUNT 9
  53 #endif
  54
  55 #ifndef SIZE_TRACE_BUF
  56 #define SIZE_TRACE_BUF 1024
  57 #endif
  58
  59 /* Text is queued in TRACE_BUF because we want to output the insn's cycle
  60    count first but that isn't known until after the insn has executed.
  61    This also handles the queueing of trace results, TRACE_RESULT may be
  62    called multiple times for one insn.  */
  63 static char trace_buf[SIZE_TRACE_BUF];
  64 /* If NULL, output to stdout directly.  */
  65 static char *bufptr;
  66
  67 /* Non-zero if this is the first insn in a set of parallel insns.  */
  68 static int first_insn_p;
  69
  70 /* For communication between cgen_trace_insn and cgen_trace_result.  */
  71 static int printed_result_p;
  72
  73 /* Insn and its extracted fields.
  74    Set by cgen_trace_insn, used by cgen_trace_insn_fini.
  75    ??? Move to SIM_CPU to support heterogeneous multi-cpu case.  */
  76 static const struct cgen_insn *current_insn;
  77 static const struct argbuf *current_abuf;
  78
  79 void
  80 cgen_trace_insn_init (SIM_CPU *cpu, int first_p)
  81 {
  82   bufptr = trace_buf;
  83   *bufptr = 0;
  84   first_insn_p = first_p;
  85
  86   /* Set to NULL so cgen_trace_insn_fini can know if cgen_trace_insn was
  87      called.  */
  88   current_insn = NULL;
  89   current_abuf = NULL;
  90 }
  91
  92 void
  93 cgen_trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p)
  94 {
  95   SIM_DESC sd = CPU_STATE (cpu);
  96
  97   /* Was insn traced?  It might not be if trace ranges are in effect.  */
  98   if (current_insn == NULL)
  99     return;
 100
 101   /* The first thing printed is current and total cycle counts.  */
 102
 103   if (PROFILE_MODEL_P (cpu)
 104       && ARGBUF_PROFILE_P (current_abuf))
 105     {
 106       unsigned long total = PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu));
 107       unsigned long this_insn = PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu));
 108
 109       if (last_p)
 110         {
 111           trace_printf (sd, cpu, "%-*ld %-*ld ",
 112                         SIZE_CYCLE_COUNT, this_insn,
 113                         SIZE_TOTAL_CYCLE_COUNT, total);
 114         }
 115       else
 116         {
 117           trace_printf (sd, cpu, "%-*ld %-*s ",
 118                         SIZE_CYCLE_COUNT, this_insn,
 119                         SIZE_TOTAL_CYCLE_COUNT, "---");
 120         }
 121     }
 122
 123   /* Print the disassembled insn.  */
 124
 125   trace_printf (sd, cpu, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu)));
 126
 127 #if 0
 128   /* Print insn results.  */
 129   {
 130     const CGEN_OPINST *opinst = CGEN_INSN_OPERANDS (current_insn);
 131
 132     if (opinst)
 133       {
 134         int i;
 135         int indices[MAX_OPERAND_INSTANCES];
 136
 137         /* Fetch the operands used by the insn.  */
 138         /* FIXME: Add fn ptr to CGEN_CPU_DESC.  */
 139         CGEN_SYM (get_insn_operands) (CPU_CPU_DESC (cpu), current_insn,
 140                                       0, CGEN_FIELDS_BITSIZE (&insn_fields),
 141                                       indices);
 142
 143         for (i = 0;
 144              CGEN_OPINST_TYPE (opinst) != CGEN_OPINST_END;
 145              ++i, ++opinst)
 146           {
 147             if (CGEN_OPINST_TYPE (opinst) == CGEN_OPINST_OUTPUT)
 148               cgen_trace_result (cpu, current_insn, opinst, indices[i]);
 149           }
 150       }
 151   }
 152 #endif
 153
 154   /* Print anything else requested.  */
 155
 156   if (*trace_buf)
 157     trace_printf (sd, cpu, " %s\n", trace_buf);
 158   else
 159     trace_printf (sd, cpu, "\n");
 160 }
 161
 162 void
 163 cgen_trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode,
 164                  const struct argbuf *abuf, IADDR pc)
 165 {
 166   char disasm_buf[50];
 167
 168   printed_result_p = 0;
 169   current_insn = opcode;
 170   current_abuf = abuf;
 171
 172   if (CGEN_INSN_VIRTUAL_P (opcode))
 173     {
 174       trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, 0,
 175                     NULL, 0, "%s", CGEN_INSN_NAME (opcode));
 176       return;
 177     }
 178
 179   CPU_DISASSEMBLER (cpu) (cpu, opcode, abuf, pc, disasm_buf);
 180   trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
 181                 NULL, 0,
 182                 "%s%-*s",
 183                 first_insn_p ? " " : "|",
 184                 SIZE_INSTRUCTION, disasm_buf);
 185 }
 186
 187 void
 188 cgen_trace_extract (SIM_CPU *cpu, IADDR pc, char *name, ...)
 189 {
 190   va_list args;
 191   int printed_one_p = 0;
 192   char *fmt;
 193
 194   va_start (args, name);
 195
 196   trace_printf (CPU_STATE (cpu), cpu, "Extract: 0x%.*lx: %s ",
 197                 SIZE_PC, (unsigned long) pc, name);
 198
 199   do {
 200     int type,ival;
 201
 202     fmt = va_arg (args, char *);
 203
 204     if (fmt)
 205       {
 206         if (printed_one_p)
 207           trace_printf (CPU_STATE (cpu), cpu, ", ");
 208         printed_one_p = 1;
 209         type = va_arg (args, int);
 210         switch (type)
 211           {
 212           case 'x' :
 213             ival = va_arg (args, int);
 214             trace_printf (CPU_STATE (cpu), cpu, fmt, ival);
 215             break;
 216           default :
 217             abort ();
 218           }
 219       }
 220   } while (fmt);
 221
 222   va_end (args);
 223   trace_printf (CPU_STATE (cpu), cpu, "\n");
 224 }
 225
 226 void
 227 cgen_trace_result (SIM_CPU *cpu, char *name, int type, ...)
 228 {
 229   va_list args;
 230
 231   va_start (args, type);
 232   if (printed_result_p)
 233     cgen_trace_printf (cpu, ", ");
 234
 235   switch (type)
 236     {
 237     case 'x' :
 238     default :
 239       cgen_trace_printf (cpu, "%s <- 0x%x", name, va_arg (args, int));
 240       break;
 241     case 'f':
 242       {
 243         DI di;
 244         sim_fpu f;
 245
 246         /* this is separated from previous line for sunos cc */
 247         di = va_arg (args, DI);
 248         sim_fpu_64to (&f, di);
 249
 250         cgen_trace_printf (cpu, "%s <- ", name);
 251         sim_fpu_printn_fpu (&f, (sim_fpu_print_func *) cgen_trace_printf, 4, cpu);
 252         break;
 253       }
 254     case 'D' :
 255       {
 256         DI di;
 257         /* this is separated from previous line for sunos cc */
 258         di = va_arg (args, DI);
 259         cgen_trace_printf (cpu, "%s <- 0x%x%08x", name,
 260                            GETHIDI(di), GETLODI (di));
 261         break;
 262       }
 263     }
 264
 265   printed_result_p = 1;
 266   va_end (args);
 267 }
 268
 269 /* Print trace output to BUFPTR if active, otherwise print normally.
 270    This is only for tracing semantic code.  */
 271
 272 void
 273 cgen_trace_printf (SIM_CPU *cpu, char *fmt, ...)
 274 {
 275   va_list args;
 276
 277   va_start (args, fmt);
 278
 279   if (bufptr == NULL)
 280     {
 281       if (TRACE_FILE (CPU_TRACE_DATA (cpu)) == NULL)
 282         (* STATE_CALLBACK (CPU_STATE (cpu))->evprintf_filtered)
 283           (STATE_CALLBACK (CPU_STATE (cpu)), fmt, args);
 284       else
 285         vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu)), fmt, args);
 286     }
 287   else
 288     {
 289       vsprintf (bufptr, fmt, args);
 290       bufptr += strlen (bufptr);
 291       /* ??? Need version of SIM_ASSERT that is always enabled.  */
 292       if (bufptr - trace_buf > SIZE_TRACE_BUF)
 293         abort ();
 294     }
 295
 296   va_end (args);
 297 }
 298 \f
 299 /* Disassembly support.  */
 300
 301 /* sprintf to a "stream" */
 302
 303 int
 304 sim_disasm_sprintf (SFILE *f, const char *format, ...)
 305 {
 306   int n;
 307   va_list args;
 308
 309   va_start (args, format);
 310   vsprintf (f->current, format, args);
 311   f->current += n = strlen (f->current);
 312   va_end (args);
 313   return n;
 314 }
 315
 316 /* Memory read support for an opcodes disassembler.  */
 317
 318 int
 319 sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
 320                         struct disassemble_info *info)
 321 {
 322   SIM_CPU *cpu = (SIM_CPU *) info->application_data;
 323   SIM_DESC sd = CPU_STATE (cpu);
 324   unsigned length_read;
 325
 326   length_read = sim_core_read_buffer (sd, cpu, read_map, myaddr, memaddr,
 327                                       length);
 328   if (length_read != length)
 329     return EIO;
 330   return 0;
 331 }
 332
 333 /* Memory error support for an opcodes disassembler.  */
 334
 335 void
 336 sim_disasm_perror_memory (int status, bfd_vma memaddr,
 337                           struct disassemble_info *info)
 338 {
 339   if (status != EIO)
 340     /* Can't happen.  */
 341     info->fprintf_func (info->stream, "Unknown error %d.", status);
 342   else
 343     /* Actually, address between memaddr and memaddr + len was
 344        out of bounds.  */
 345     info->fprintf_func (info->stream,
 346                         "Address 0x%" BFD_VMA_FMT "x is out of bounds.",
 347                         memaddr);
 348 }
 349
 350 /* Disassemble using the CGEN opcode table.
 351    ??? While executing an instruction, the insn has been decoded and all its
 352    fields have been extracted.  It is certainly possible to do the disassembly
 353    with that data.  This seems simpler, but maybe in the future the already
 354    extracted fields will be used.  */
 355
 356 void
 357 sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
 358                            const ARGBUF *abuf, IADDR pc, char *buf)
 359 {
 360   unsigned int length;
 361   unsigned int base_length;
 362   unsigned long insn_value;
 363   struct disassemble_info disasm_info;
 364   SFILE sfile;
 365   union {
 366     unsigned8 bytes[CGEN_MAX_INSN_SIZE];
 367     unsigned16 shorts[8];
 368     unsigned32 words[4];
 369   } insn_buf;
 370   SIM_DESC sd = CPU_STATE (cpu);
 371   CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu);
 372   CGEN_EXTRACT_INFO ex_info;
 373   CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
 374   int insn_bit_length = CGEN_INSN_BITSIZE (insn);
 375   int insn_length = insn_bit_length / 8;
 376
 377   sfile.buffer = sfile.current = buf;
 378   INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
 379                          (fprintf_ftype) sim_disasm_sprintf);
 380   disasm_info.endian =
 381     (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
 382      : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
 383      : BFD_ENDIAN_UNKNOWN);
 384
 385   length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc,
 386                                  insn_length);
 387
 388   if (length != insn_length)
 389   {
 390     sim_io_error (sd, "unable to read address %" PRIxTA, pc);
 391   }
 392
 393   /* If the entire insn will fit into an integer, then do it. Otherwise, just
 394      use the bits of the base_insn.  */
 395   if (insn_bit_length <= 32)
 396     base_length = insn_bit_length;
 397   else
 398     base_length = min (cd->base_insn_bitsize, insn_bit_length);
 399   switch (base_length)
 400     {
 401     case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
 402     case 8 : insn_value = insn_buf.bytes[0]; break;
 403     case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break;
 404     case 32 : insn_value = T2H_4 (insn_buf.words[0]); break;
 405     default: abort ();
 406     }
 407
 408   disasm_info.buffer_vma = pc;
 409   disasm_info.buffer = insn_buf.bytes;
 410   disasm_info.buffer_length = length;
 411
 412   ex_info.dis_info = (PTR) &disasm_info;
 413   ex_info.valid = (1 << length) - 1;
 414   ex_info.insn_bytes = insn_buf.bytes;
 415
 416   length = (*CGEN_EXTRACT_FN (cd, insn)) (cd, insn, &ex_info, insn_value, fields, pc);
 417   /* Result of extract fn is in bits.  */
 418   /* ??? This assumes that each instruction has a fixed length (and thus
 419      for insns with multiple versions of variable lengths they would each
 420      have their own table entry).  */
 421   if (length == insn_bit_length)
 422     {
 423       (*CGEN_PRINT_FN (cd, insn)) (cd, &disasm_info, insn, fields, pc, length);
 424     }
 425   else
 426     {
 427       /* This shouldn't happen, but aborting is too drastic.  */
 428       strcpy (buf, "***unknown***");
 429     }
 430 }