sim/common/cgen-trace.c

   1 /* Tracing support for CGEN-based simulators.
   2    Copyright (C) 1996-2021 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* This must come before any other includes.  */
  21 #include "defs.h"
  22
  23 #include <errno.h>
  24 #include <stdlib.h>
  25
  26 #include "bfd.h"
  27 #include "diagnostics.h"
  28 #include "dis-asm.h"
  29
  30 #include "sim-main.h"
  31 #include "sim-fpu.h"
  32 #include "sim/callback.h"
  33
  34 #ifndef SIZE_INSTRUCTION
  35 #define SIZE_INSTRUCTION 16
  36 #endif
  37
  38 #ifndef SIZE_LOCATION
  39 #define SIZE_LOCATION 20
  40 #endif
  41
  42 #ifndef SIZE_PC
  43 #define SIZE_PC 6
  44 #endif
  45
  46 #ifndef SIZE_LINE_NUMBER
  47 #define SIZE_LINE_NUMBER 4
  48 #endif
  49
  50 #ifndef SIZE_CYCLE_COUNT
  51 #define SIZE_CYCLE_COUNT 2
  52 #endif
  53
  54 #ifndef SIZE_TOTAL_CYCLE_COUNT
  55 #define SIZE_TOTAL_CYCLE_COUNT 9
  56 #endif
  57
  58 #ifndef SIZE_TRACE_BUF
  59 #define SIZE_TRACE_BUF 1024
  60 #endif
  61
  62 /* Text is queued in TRACE_BUF because we want to output the insn's cycle
  63    count first but that isn't known until after the insn has executed.
  64    This also handles the queueing of trace results, TRACE_RESULT may be
  65    called multiple times for one insn.  */
  66 static char trace_buf[SIZE_TRACE_BUF];
  67 /* If NULL, output to stdout directly.  */
  68 static char *bufptr;
  69
  70 /* Non-zero if this is the first insn in a set of parallel insns.  */
  71 static int first_insn_p;
  72
  73 /* For communication between cgen_trace_insn and cgen_trace_result.  */
  74 static int printed_result_p;
  75
  76 /* Insn and its extracted fields.
  77    Set by cgen_trace_insn, used by cgen_trace_insn_fini.
  78    ??? Move to SIM_CPU to support heterogeneous multi-cpu case.  */
  79 static const struct cgen_insn *current_insn;
  80 static const struct argbuf *current_abuf;
  81
  82 void
  83 cgen_trace_insn_init (SIM_CPU *cpu, int first_p)
  84 {
  85   bufptr = trace_buf;
  86   *bufptr = 0;
  87   first_insn_p = first_p;
  88
  89   /* Set to NULL so cgen_trace_insn_fini can know if cgen_trace_insn was
  90      called.  */
  91   current_insn = NULL;
  92   current_abuf = NULL;
  93 }
  94
  95 void
  96 cgen_trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p)
  97 {
  98   SIM_DESC sd = CPU_STATE (cpu);
  99
 100   /* Was insn traced?  It might not be if trace ranges are in effect.  */
 101   if (current_insn == NULL)
 102     return;
 103
 104   /* The first thing printed is current and total cycle counts.  */
 105
 106   if (PROFILE_MODEL_P (cpu)
 107       && ARGBUF_PROFILE_P (current_abuf))
 108     {
 109       unsigned long total = PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu));
 110       unsigned long this_insn = PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu));
 111
 112       if (last_p)
 113         {
 114           trace_printf (sd, cpu, "%-*ld %-*ld ",
 115                         SIZE_CYCLE_COUNT, this_insn,
 116                         SIZE_TOTAL_CYCLE_COUNT, total);
 117         }
 118       else
 119         {
 120           trace_printf (sd, cpu, "%-*ld %-*s ",
 121                         SIZE_CYCLE_COUNT, this_insn,
 122                         SIZE_TOTAL_CYCLE_COUNT, "---");
 123         }
 124     }
 125
 126   /* Print the disassembled insn.  */
 127
 128   trace_printf (sd, cpu, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu)));
 129
 130 #if 0
 131   /* Print insn results.  */
 132   {
 133     const CGEN_OPINST *opinst = CGEN_INSN_OPERANDS (current_insn);
 134
 135     if (opinst)
 136       {
 137         int i;
 138         int indices[MAX_OPERAND_INSTANCES];
 139
 140         /* Fetch the operands used by the insn.  */
 141         /* FIXME: Add fn ptr to CGEN_CPU_DESC.  */
 142         CGEN_SYM (get_insn_operands) (CPU_CPU_DESC (cpu), current_insn,
 143                                       0, CGEN_FIELDS_BITSIZE (&insn_fields),
 144                                       indices);
 145
 146         for (i = 0;
 147              CGEN_OPINST_TYPE (opinst) != CGEN_OPINST_END;
 148              ++i, ++opinst)
 149           {
 150             if (CGEN_OPINST_TYPE (opinst) == CGEN_OPINST_OUTPUT)
 151               cgen_trace_result (cpu, current_insn, opinst, indices[i]);
 152           }
 153       }
 154   }
 155 #endif
 156
 157   /* Print anything else requested.  */
 158
 159   if (*trace_buf)
 160     trace_printf (sd, cpu, " %s\n", trace_buf);
 161   else
 162     trace_printf (sd, cpu, "\n");
 163 }
 164
 165 void
 166 cgen_trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode,
 167                  const struct argbuf *abuf, IADDR pc)
 168 {
 169   char disasm_buf[50];
 170
 171   printed_result_p = 0;
 172   current_insn = opcode;
 173   current_abuf = abuf;
 174
 175   if (CGEN_INSN_VIRTUAL_P (opcode))
 176     {
 177       trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, 0,
 178                     NULL, 0, "%s", CGEN_INSN_NAME (opcode));
 179       return;
 180     }
 181
 182   CPU_DISASSEMBLER (cpu) (cpu, opcode, abuf, pc, disasm_buf);
 183   trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
 184                 NULL, 0,
 185                 "%s%-*s",
 186                 first_insn_p ? " " : "|",
 187                 SIZE_INSTRUCTION, disasm_buf);
 188 }
 189
 190 void
 191 cgen_trace_extract (SIM_CPU *cpu, IADDR pc, const char *name, ...)
 192 {
 193   va_list args;
 194   int printed_one_p = 0;
 195   const char *fmt;
 196
 197   va_start (args, name);
 198
 199   trace_printf (CPU_STATE (cpu), cpu, "Extract: 0x%.*lx: %s ",
 200                 SIZE_PC, (unsigned long) pc, name);
 201
 202   do {
 203     int type,ival;
 204
 205     fmt = va_arg (args, const char *);
 206
 207     if (fmt)
 208       {
 209         if (printed_one_p)
 210           trace_printf (CPU_STATE (cpu), cpu, ", ");
 211         printed_one_p = 1;
 212         type = va_arg (args, int);
 213         switch (type)
 214           {
 215           case 'x' :
 216             ival = va_arg (args, int);
 217             DIAGNOSTIC_PUSH
 218             DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL
 219             trace_printf (CPU_STATE (cpu), cpu, fmt, ival);
 220             DIAGNOSTIC_POP
 221             break;
 222           default :
 223             abort ();
 224           }
 225       }
 226   } while (fmt);
 227
 228   va_end (args);
 229   trace_printf (CPU_STATE (cpu), cpu, "\n");
 230 }
 231
 232 void
 233 cgen_trace_result (SIM_CPU *cpu, const char *name, int type, ...)
 234 {
 235   va_list args;
 236
 237   va_start (args, type);
 238   if (printed_result_p)
 239     cgen_trace_printf (cpu, ", ");
 240
 241   switch (type)
 242     {
 243     case 'x' :
 244     default :
 245       cgen_trace_printf (cpu, "%s <- 0x%x", name, va_arg (args, int));
 246       break;
 247     case 'f':
 248       {
 249         DI di;
 250         sim_fpu f;
 251
 252         /* this is separated from previous line for sunos cc */
 253         di = va_arg (args, DI);
 254         sim_fpu_64to (&f, di);
 255
 256         cgen_trace_printf (cpu, "%s <- ", name);
 257         sim_fpu_printn_fpu (&f, (sim_fpu_print_func *) cgen_trace_printf, 4, cpu);
 258         break;
 259       }
 260     case 'D' :
 261       {
 262         DI di;
 263         /* this is separated from previous line for sunos cc */
 264         di = va_arg (args, DI);
 265         cgen_trace_printf (cpu, "%s <- 0x%x%08x", name,
 266                            GETHIDI(di), GETLODI (di));
 267         break;
 268       }
 269     }
 270
 271   printed_result_p = 1;
 272   va_end (args);
 273 }
 274
 275 /* Print trace output to BUFPTR if active, otherwise print normally.
 276    This is only for tracing semantic code.  */
 277
 278 void
 279 cgen_trace_printf (SIM_CPU *cpu, const char *fmt, ...)
 280 {
 281   va_list args;
 282
 283   va_start (args, fmt);
 284
 285   if (bufptr == NULL)
 286     {
 287       if (TRACE_FILE (CPU_TRACE_DATA (cpu)) == NULL)
 288         (* STATE_CALLBACK (CPU_STATE (cpu))->evprintf_filtered)
 289           (STATE_CALLBACK (CPU_STATE (cpu)), fmt, args);
 290       else
 291         vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu)), fmt, args);
 292     }
 293   else
 294     {
 295       vsprintf (bufptr, fmt, args);
 296       bufptr += strlen (bufptr);
 297       /* ??? Need version of SIM_ASSERT that is always enabled.  */
 298       if (bufptr - trace_buf > SIZE_TRACE_BUF)
 299         abort ();
 300     }
 301
 302   va_end (args);
 303 }
 304 \f
 305 /* Disassembly support.  */
 306
 307 /* sprintf to a "stream" */
 308
 309 int
 310 sim_disasm_sprintf (SFILE *f, const char *format, ...)
 311 {
 312   int n;
 313   va_list args;
 314
 315   va_start (args, format);
 316   vsprintf (f->current, format, args);
 317   f->current += n = strlen (f->current);
 318   va_end (args);
 319   return n;
 320 }
 321
 322 /* Memory read support for an opcodes disassembler.  */
 323
 324 int
 325 sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
 326                         struct disassemble_info *info)
 327 {
 328   SIM_CPU *cpu = (SIM_CPU *) info->application_data;
 329   SIM_DESC sd = CPU_STATE (cpu);
 330   unsigned length_read;
 331
 332   length_read = sim_core_read_buffer (sd, cpu, read_map, myaddr, memaddr,
 333                                       length);
 334   if (length_read != length)
 335     return EIO;
 336   return 0;
 337 }
 338
 339 /* Memory error support for an opcodes disassembler.  */
 340
 341 void
 342 sim_disasm_perror_memory (int status, bfd_vma memaddr,
 343                           struct disassemble_info *info)
 344 {
 345   if (status != EIO)
 346     /* Can't happen.  */
 347     info->fprintf_func (info->stream, "Unknown error %d.", status);
 348   else
 349     /* Actually, address between memaddr and memaddr + len was
 350        out of bounds.  */
 351     info->fprintf_func (info->stream,
 352                         "Address 0x%" BFD_VMA_FMT "x is out of bounds.",
 353                         memaddr);
 354 }
 355
 356 /* Disassemble using the CGEN opcode table.
 357    ??? While executing an instruction, the insn has been decoded and all its
 358    fields have been extracted.  It is certainly possible to do the disassembly
 359    with that data.  This seems simpler, but maybe in the future the already
 360    extracted fields will be used.  */
 361
 362 void
 363 sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
 364                            const ARGBUF *abuf, IADDR pc, char *buf)
 365 {
 366   unsigned int length;
 367   unsigned int base_length;
 368   unsigned long insn_value;
 369   struct disassemble_info disasm_info;
 370   SFILE sfile;
 371   union {
 372     unsigned8 bytes[CGEN_MAX_INSN_SIZE];
 373     unsigned16 shorts[8];
 374     unsigned32 words[4];
 375   } insn_buf;
 376   SIM_DESC sd = CPU_STATE (cpu);
 377   CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu);
 378   CGEN_EXTRACT_INFO ex_info;
 379   CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
 380   int insn_bit_length = CGEN_INSN_BITSIZE (insn);
 381   int insn_length = insn_bit_length / 8;
 382
 383   sfile.buffer = sfile.current = buf;
 384   INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
 385                          (fprintf_ftype) sim_disasm_sprintf);
 386   disasm_info.endian =
 387     (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
 388      : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
 389      : BFD_ENDIAN_UNKNOWN);
 390
 391   length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc,
 392                                  insn_length);
 393
 394   if (length != insn_length)
 395   {
 396     sim_io_error (sd, "unable to read address %" PRIxTA, pc);
 397   }
 398
 399   /* If the entire insn will fit into an integer, then do it. Otherwise, just
 400      use the bits of the base_insn.  */
 401   if (insn_bit_length <= 32)
 402     base_length = insn_bit_length;
 403   else
 404     base_length = min (cd->base_insn_bitsize, insn_bit_length);
 405   switch (base_length)
 406     {
 407     case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
 408     case 8 : insn_value = insn_buf.bytes[0]; break;
 409     case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break;
 410     case 32 : insn_value = T2H_4 (insn_buf.words[0]); break;
 411     default: abort ();
 412     }
 413
 414   disasm_info.buffer_vma = pc;
 415   disasm_info.buffer = insn_buf.bytes;
 416   disasm_info.buffer_length = length;
 417
 418   ex_info.dis_info = (PTR) &disasm_info;
 419   ex_info.valid = (1 << length) - 1;
 420   ex_info.insn_bytes = insn_buf.bytes;
 421
 422   length = (*CGEN_EXTRACT_FN (cd, insn)) (cd, insn, &ex_info, insn_value, fields, pc);
 423   /* Result of extract fn is in bits.  */
 424   /* ??? This assumes that each instruction has a fixed length (and thus
 425      for insns with multiple versions of variable lengths they would each
 426      have their own table entry).  */
 427   if (length == insn_bit_length)
 428     {
 429       (*CGEN_PRINT_FN (cd, insn)) (cd, &disasm_info, insn, fields, pc, length);
 430     }
 431   else
 432     {
 433       /* This shouldn't happen, but aborting is too drastic.  */
 434       strcpy (buf, "***unknown***");
 435     }
 436 }