1 /* This is a software floating point library which can be used instead
2 of the floating point routines in libgcc1.c for targets without
3 hardware floating point. */
5 /* Copyright 1994-2021 Free Software Foundation, Inc.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* As a special exception, if you link this library with other files,
21 some of which are compiled with GCC, to produce an executable,
22 this library does not by itself cause the resulting executable
23 to be covered by the GNU General Public License.
24 This exception does not however invalidate any other reasons why
25 the executable file might be covered by the GNU General Public License. */
27 /* This implements IEEE 754 format arithmetic, but does not provide a
28 mechanism for setting the rounding mode, or for generating or handling
31 The original code by Steve Chamberlain, hacked by Mark Eichin and Jim
32 Wilson, all of Cygnus Support. */
38 /* This must come before any other includes. */
43 #include "sim-basics.h"
47 #include "sim-assert.h"
50 If digits is -1, then print all digits. */
53 print_bits (unsigned64 x
,
56 sim_fpu_print_func print
,
59 unsigned64 bit
= LSBIT64 (msbit
);
80 /* Quick and dirty conversion between a host double and host 64bit int. */
89 /* A packed IEEE floating point number.
91 Form is <SIGN:1><BIASEDEXP:NR_EXPBITS><FRAC:NR_FRACBITS> for both
92 32 and 64 bit numbers. This number is interpreted as:
94 Normalized (0 < BIASEDEXP && BIASEDEXP < EXPMAX):
95 (sign ? '-' : '+') 1.<FRAC> x 2 ^ (BIASEDEXP - EXPBIAS)
97 Denormalized (0 == BIASEDEXP && FRAC != 0):
98 (sign ? "-" : "+") 0.<FRAC> x 2 ^ (- EXPBIAS)
100 Zero (0 == BIASEDEXP && FRAC == 0):
101 (sign ? "-" : "+") 0.0
103 Infinity (BIASEDEXP == EXPMAX && FRAC == 0):
104 (sign ? "-" : "+") "infinity"
106 SignalingNaN (BIASEDEXP == EXPMAX && FRAC > 0 && FRAC < QUIET_NAN):
109 QuietNaN (BIASEDEXP == EXPMAX && FRAC > 0 && FRAC > QUIET_NAN):
114 #define NR_EXPBITS (is_double ? 11 : 8)
115 #define NR_FRACBITS (is_double ? 52 : 23)
116 #define SIGNBIT (is_double ? MSBIT64 (0) : MSBIT64 (32))
118 #define EXPMAX32 (255)
119 #define EXMPAX64 (2047)
120 #define EXPMAX ((unsigned) (is_double ? EXMPAX64 : EXPMAX32))
122 #define EXPBIAS32 (127)
123 #define EXPBIAS64 (1023)
124 #define EXPBIAS (is_double ? EXPBIAS64 : EXPBIAS32)
126 #define QUIET_NAN LSBIT64 (NR_FRACBITS - 1)
130 /* An unpacked floating point number.
132 When unpacked, the fraction of both a 32 and 64 bit floating point
133 number is stored using the same format:
135 64 bit - <IMPLICIT_1:1><FRACBITS:52><GUARDS:8><PAD:00>
136 32 bit - <IMPLICIT_1:1><FRACBITS:23><GUARDS:7><PAD:30> */
138 #define NR_PAD32 (30)
140 #define NR_PAD (is_double ? NR_PAD64 : NR_PAD32)
141 #define PADMASK (is_double ? 0 : LSMASK64 (NR_PAD32 - 1, 0))
143 #define NR_GUARDS32 (7 + NR_PAD32)
144 #define NR_GUARDS64 (8 + NR_PAD64)
145 #define NR_GUARDS (is_double ? NR_GUARDS64 : NR_GUARDS32)
146 #define GUARDMASK LSMASK64 (NR_GUARDS - 1, 0)
148 #define GUARDMSB LSBIT64 (NR_GUARDS - 1)
149 #define GUARDLSB LSBIT64 (NR_PAD)
150 #define GUARDROUND LSMASK64 (NR_GUARDS - 2, 0)
152 #define NR_FRAC_GUARD (60)
153 #define IMPLICIT_1 LSBIT64 (NR_FRAC_GUARD)
154 #define IMPLICIT_2 LSBIT64 (NR_FRAC_GUARD + 1)
155 #define IMPLICIT_4 LSBIT64 (NR_FRAC_GUARD + 2)
158 #define FRAC32MASK LSMASK64 (63, NR_FRAC_GUARD - 32 + 1)
160 #define NORMAL_EXPMIN (-(EXPBIAS)+1)
162 #define NORMAL_EXPMAX32 (EXPBIAS32)
163 #define NORMAL_EXPMAX64 (EXPBIAS64)
164 #define NORMAL_EXPMAX (EXPBIAS)
167 /* Integer constants */
169 #define MAX_INT32 ((signed64) LSMASK64 (30, 0))
170 #define MAX_UINT32 LSMASK64 (31, 0)
171 #define MIN_INT32 ((signed64) LSMASK64 (63, 31))
173 #define MAX_INT64 ((signed64) LSMASK64 (62, 0))
174 #define MAX_UINT64 LSMASK64 (63, 0)
175 #define MIN_INT64 ((signed64) LSMASK64 (63, 63))
177 #define MAX_INT (is_64bit ? MAX_INT64 : MAX_INT32)
178 #define MIN_INT (is_64bit ? MIN_INT64 : MIN_INT32)
179 #define MAX_UINT (is_64bit ? MAX_UINT64 : MAX_UINT32)
180 #define NR_INTBITS (is_64bit ? 64 : 32)
182 /* Squeeze an unpacked sim_fpu struct into a 32/64 bit integer. */
183 STATIC_INLINE_SIM_FPU (unsigned64
)
184 pack_fpu (const sim_fpu
*src
,
195 case sim_fpu_class_qnan
:
198 /* Force fraction to correct class. */
199 fraction
= src
->fraction
;
200 fraction
>>= NR_GUARDS
;
201 #ifdef SIM_QUIET_NAN_NEGATED
202 fraction
|= QUIET_NAN
- 1;
204 fraction
|= QUIET_NAN
;
207 case sim_fpu_class_snan
:
210 /* Force fraction to correct class. */
211 fraction
= src
->fraction
;
212 fraction
>>= NR_GUARDS
;
213 #ifdef SIM_QUIET_NAN_NEGATED
214 fraction
|= QUIET_NAN
;
216 fraction
&= ~QUIET_NAN
;
219 case sim_fpu_class_infinity
:
224 case sim_fpu_class_zero
:
229 case sim_fpu_class_number
:
230 case sim_fpu_class_denorm
:
231 ASSERT (src
->fraction
>= IMPLICIT_1
);
232 ASSERT (src
->fraction
< IMPLICIT_2
);
233 if (src
->normal_exp
< NORMAL_EXPMIN
)
235 /* This number's exponent is too low to fit into the bits
236 available in the number We'll denormalize the number by
237 storing zero in the exponent and shift the fraction to
238 the right to make up for it. */
239 int nr_shift
= NORMAL_EXPMIN
- src
->normal_exp
;
240 if (nr_shift
> NR_FRACBITS
)
242 /* Underflow, just make the number zero. */
251 /* Shift by the value. */
252 fraction
= src
->fraction
;
253 fraction
>>= NR_GUARDS
;
254 fraction
>>= nr_shift
;
257 else if (src
->normal_exp
> NORMAL_EXPMAX
)
266 exp
= (src
->normal_exp
+ EXPBIAS
);
268 fraction
= src
->fraction
;
269 /* FIXME: Need to round according to WITH_SIM_FPU_ROUNDING
271 /* Round to nearest: If the guard bits are the all zero, but
272 the first, then we're half way between two numbers,
273 choose the one which makes the lsb of the answer 0. */
274 if ((fraction
& GUARDMASK
) == GUARDMSB
)
276 if ((fraction
& (GUARDMSB
<< 1)))
277 fraction
+= (GUARDMSB
<< 1);
281 /* Add a one to the guards to force round to nearest. */
282 fraction
+= GUARDROUND
;
284 if ((fraction
& IMPLICIT_2
)) /* Rounding resulted in carry. */
289 fraction
>>= NR_GUARDS
;
290 /* When exp == EXPMAX (overflow from carry) fraction must
291 have been made zero. */
292 ASSERT ((exp
== EXPMAX
) <= ((fraction
& ~IMPLICIT_1
) == 0));
299 packed
= ((sign
? SIGNBIT
: 0)
300 | (exp
<< NR_FRACBITS
)
301 | LSMASKED64 (fraction
, NR_FRACBITS
- 1, 0));
303 /* Trace operation. */
310 printf ("pack_fpu: ");
311 printf ("-> %c%0lX.%06lX\n",
312 LSMASKED32 (packed
, 31, 31) ? '8' : '0',
313 (long) LSEXTRACTED32 (packed
, 30, 23),
314 (long) LSEXTRACTED32 (packed
, 23 - 1, 0));
322 /* Unpack a 32/64 bit integer into a sim_fpu structure. */
323 STATIC_INLINE_SIM_FPU (void)
324 unpack_fpu (sim_fpu
*dst
, unsigned64 packed
, int is_double
)
326 unsigned64 fraction
= LSMASKED64 (packed
, NR_FRACBITS
- 1, 0);
327 unsigned exp
= LSEXTRACTED64 (packed
, NR_EXPBITS
+ NR_FRACBITS
- 1, NR_FRACBITS
);
328 int sign
= (packed
& SIGNBIT
) != 0;
332 /* Hmm. Looks like 0 */
335 /* Tastes like zero. */
336 dst
->class = sim_fpu_class_zero
;
342 /* Zero exponent with non zero fraction - it's denormalized,
343 so there isn't a leading implicit one - we'll shift it so
345 dst
->normal_exp
= exp
- EXPBIAS
+ 1;
346 dst
->class = sim_fpu_class_denorm
;
348 fraction
<<= NR_GUARDS
;
349 while (fraction
< IMPLICIT_1
)
354 dst
->fraction
= fraction
;
357 else if (exp
== EXPMAX
)
362 /* Attached to a zero fraction - means infinity. */
363 dst
->class = sim_fpu_class_infinity
;
365 /* dst->normal_exp = EXPBIAS; */
366 /* dst->fraction = 0; */
372 /* Non zero fraction, means NaN. */
374 dst
->fraction
= (fraction
<< NR_GUARDS
);
375 #ifdef SIM_QUIET_NAN_NEGATED
376 qnan
= (fraction
& QUIET_NAN
) == 0;
378 qnan
= fraction
>= QUIET_NAN
;
381 dst
->class = sim_fpu_class_qnan
;
383 dst
->class = sim_fpu_class_snan
;
388 /* Nothing strange about this number. */
389 dst
->class = sim_fpu_class_number
;
391 dst
->fraction
= ((fraction
<< NR_GUARDS
) | IMPLICIT_1
);
392 dst
->normal_exp
= exp
- EXPBIAS
;
395 /* Trace operation. */
402 printf ("unpack_fpu: %c%02lX.%06lX ->\n",
403 LSMASKED32 (packed
, 31, 31) ? '8' : '0',
404 (long) LSEXTRACTED32 (packed
, 30, 23),
405 (long) LSEXTRACTED32 (packed
, 23 - 1, 0));
412 val
.i
= pack_fpu (dst
, 1);
415 ASSERT (val
.i
== packed
);
419 unsigned32 val
= pack_fpu (dst
, 0);
420 unsigned32 org
= packed
;
427 /* Convert a floating point into an integer. */
428 STATIC_INLINE_SIM_FPU (int)
437 if (sim_fpu_is_zero (s
))
442 if (sim_fpu_is_snan (s
))
444 *i
= MIN_INT
; /* FIXME */
445 return sim_fpu_status_invalid_cvi
;
447 if (sim_fpu_is_qnan (s
))
449 *i
= MIN_INT
; /* FIXME */
450 return sim_fpu_status_invalid_cvi
;
452 /* Map infinity onto MAX_INT... */
453 if (sim_fpu_is_infinity (s
))
455 *i
= s
->sign
? MIN_INT
: MAX_INT
;
456 return sim_fpu_status_invalid_cvi
;
458 /* It is a number, but a small one. */
459 if (s
->normal_exp
< 0)
462 return sim_fpu_status_inexact
;
464 /* Is the floating point MIN_INT or just close? */
465 if (s
->sign
&& s
->normal_exp
== (NR_INTBITS
- 1))
468 ASSERT (s
->fraction
>= IMPLICIT_1
);
469 if (s
->fraction
== IMPLICIT_1
)
470 return 0; /* exact */
471 if (is_64bit
) /* can't round */
472 return sim_fpu_status_invalid_cvi
; /* must be overflow */
473 /* For a 32bit with MAX_INT, rounding is possible. */
476 case sim_fpu_round_default
:
478 case sim_fpu_round_zero
:
479 if ((s
->fraction
& FRAC32MASK
) != IMPLICIT_1
)
480 return sim_fpu_status_invalid_cvi
;
482 return sim_fpu_status_inexact
;
484 case sim_fpu_round_near
:
486 if ((s
->fraction
& FRAC32MASK
) != IMPLICIT_1
)
487 return sim_fpu_status_invalid_cvi
;
488 else if ((s
->fraction
& !FRAC32MASK
) >= (~FRAC32MASK
>> 1))
489 return sim_fpu_status_invalid_cvi
;
491 return sim_fpu_status_inexact
;
493 case sim_fpu_round_up
:
494 if ((s
->fraction
& FRAC32MASK
) == IMPLICIT_1
)
495 return sim_fpu_status_inexact
;
497 return sim_fpu_status_invalid_cvi
;
498 case sim_fpu_round_down
:
499 return sim_fpu_status_invalid_cvi
;
502 /* Would right shifting result in the FRAC being shifted into
503 (through) the integer's sign bit? */
504 if (s
->normal_exp
> (NR_INTBITS
- 2))
506 *i
= s
->sign
? MIN_INT
: MAX_INT
;
507 return sim_fpu_status_invalid_cvi
;
509 /* Normal number, shift it into place. */
511 shift
= (s
->normal_exp
- (NR_FRAC_GUARD
));
519 if (tmp
& ((SIGNED64 (1) << shift
) - 1))
520 status
|= sim_fpu_status_inexact
;
523 *i
= s
->sign
? (-tmp
) : (tmp
);
527 /* Convert an integer into a floating point. */
528 STATIC_INLINE_SIM_FPU (int)
529 i2fpu (sim_fpu
*f
, signed64 i
, int is_64bit
)
534 f
->class = sim_fpu_class_zero
;
540 f
->class = sim_fpu_class_number
;
542 f
->normal_exp
= NR_FRAC_GUARD
;
546 /* Special case for minint, since there is no corresponding
547 +ve integer representation for it. */
550 f
->fraction
= IMPLICIT_1
;
551 f
->normal_exp
= NR_INTBITS
- 1;
559 if (f
->fraction
>= IMPLICIT_2
)
563 f
->fraction
= (f
->fraction
>> 1) | (f
->fraction
& 1);
566 while (f
->fraction
>= IMPLICIT_2
);
568 else if (f
->fraction
< IMPLICIT_1
)
575 while (f
->fraction
< IMPLICIT_1
);
579 /* trace operation */
582 printf ("i2fpu: 0x%08lX ->\n", (long) i
);
589 fpu2i (&val
, f
, is_64bit
, sim_fpu_round_zero
);
590 if (i
>= MIN_INT32
&& i
<= MAX_INT32
)
600 /* Convert a floating point into an integer. */
601 STATIC_INLINE_SIM_FPU (int)
602 fpu2u (unsigned64
*u
, const sim_fpu
*s
, int is_64bit
)
604 const int is_double
= 1;
607 if (sim_fpu_is_zero (s
))
612 if (sim_fpu_is_nan (s
))
617 /* It is a negative number. */
623 /* Get reasonable MAX_USI_INT... */
624 if (sim_fpu_is_infinity (s
))
629 /* It is a number, but a small one. */
630 if (s
->normal_exp
< 0)
636 if (s
->normal_exp
> (NR_INTBITS
- 1))
642 tmp
= (s
->fraction
& ~PADMASK
);
643 shift
= (s
->normal_exp
- (NR_FRACBITS
+ NR_GUARDS
));
657 /* Convert an unsigned integer into a floating point. */
658 STATIC_INLINE_SIM_FPU (int)
659 u2fpu (sim_fpu
*f
, unsigned64 u
, int is_64bit
)
663 f
->class = sim_fpu_class_zero
;
669 f
->class = sim_fpu_class_number
;
671 f
->normal_exp
= NR_FRAC_GUARD
;
674 while (f
->fraction
< IMPLICIT_1
)
684 /* register <-> sim_fpu */
686 INLINE_SIM_FPU (void)
687 sim_fpu_32to (sim_fpu
*f
, unsigned32 s
)
689 unpack_fpu (f
, s
, 0);
693 INLINE_SIM_FPU (void)
694 sim_fpu_232to (sim_fpu
*f
, unsigned32 h
, unsigned32 l
)
698 unpack_fpu (f
, s
, 1);
702 INLINE_SIM_FPU (void)
703 sim_fpu_64to (sim_fpu
*f
, unsigned64 s
)
705 unpack_fpu (f
, s
, 1);
709 INLINE_SIM_FPU (void)
710 sim_fpu_to32 (unsigned32
*s
,
713 *s
= pack_fpu (f
, 0);
717 INLINE_SIM_FPU (void)
718 sim_fpu_to232 (unsigned32
*h
, unsigned32
*l
,
721 unsigned64 s
= pack_fpu (f
, 1);
727 INLINE_SIM_FPU (void)
728 sim_fpu_to64 (unsigned64
*u
,
731 *u
= pack_fpu (f
, 1);
735 INLINE_SIM_FPU (void)
736 sim_fpu_fractionto (sim_fpu
*f
,
742 int shift
= (NR_FRAC_GUARD
- precision
);
743 f
->class = sim_fpu_class_number
;
745 f
->normal_exp
= normal_exp
;
746 /* Shift the fraction to where sim-fpu expects it. */
748 f
->fraction
= (fraction
<< shift
);
750 f
->fraction
= (fraction
>> -shift
);
751 f
->fraction
|= IMPLICIT_1
;
755 INLINE_SIM_FPU (unsigned64
)
756 sim_fpu_tofraction (const sim_fpu
*d
,
759 /* We have NR_FRAC_GUARD bits, we want only PRECISION bits. */
760 int shift
= (NR_FRAC_GUARD
- precision
);
761 unsigned64 fraction
= (d
->fraction
& ~IMPLICIT_1
);
763 return fraction
>> shift
;
765 return fraction
<< -shift
;
771 STATIC_INLINE_SIM_FPU (int)
772 do_normal_overflow (sim_fpu
*f
,
778 case sim_fpu_round_default
:
780 case sim_fpu_round_near
:
781 f
->class = sim_fpu_class_infinity
;
783 case sim_fpu_round_up
:
785 f
->class = sim_fpu_class_infinity
;
787 case sim_fpu_round_down
:
789 f
->class = sim_fpu_class_infinity
;
791 case sim_fpu_round_zero
:
794 f
->normal_exp
= NORMAL_EXPMAX
;
795 f
->fraction
= LSMASK64 (NR_FRAC_GUARD
, NR_GUARDS
);
796 return (sim_fpu_status_overflow
| sim_fpu_status_inexact
);
799 STATIC_INLINE_SIM_FPU (int)
800 do_normal_underflow (sim_fpu
*f
,
806 case sim_fpu_round_default
:
808 case sim_fpu_round_near
:
809 f
->class = sim_fpu_class_zero
;
811 case sim_fpu_round_up
:
813 f
->class = sim_fpu_class_zero
;
815 case sim_fpu_round_down
:
817 f
->class = sim_fpu_class_zero
;
819 case sim_fpu_round_zero
:
820 f
->class = sim_fpu_class_zero
;
823 f
->normal_exp
= NORMAL_EXPMIN
- NR_FRACBITS
;
824 f
->fraction
= IMPLICIT_1
;
825 return (sim_fpu_status_inexact
| sim_fpu_status_underflow
);
830 /* Round a number using NR_GUARDS.
831 Will return the rounded number or F->FRACTION == 0 when underflow. */
833 STATIC_INLINE_SIM_FPU (int)
834 do_normal_round (sim_fpu
*f
,
838 unsigned64 guardmask
= LSMASK64 (nr_guards
- 1, 0);
839 unsigned64 guardmsb
= LSBIT64 (nr_guards
- 1);
840 unsigned64 fraclsb
= guardmsb
<< 1;
841 if ((f
->fraction
& guardmask
))
843 int status
= sim_fpu_status_inexact
;
846 case sim_fpu_round_default
:
848 case sim_fpu_round_near
:
849 if ((f
->fraction
& guardmsb
))
851 if ((f
->fraction
& fraclsb
))
853 status
|= sim_fpu_status_rounded
;
855 else if ((f
->fraction
& (guardmask
>> 1)))
857 status
|= sim_fpu_status_rounded
;
861 case sim_fpu_round_up
:
863 status
|= sim_fpu_status_rounded
;
865 case sim_fpu_round_down
:
867 status
|= sim_fpu_status_rounded
;
869 case sim_fpu_round_zero
:
872 f
->fraction
&= ~guardmask
;
873 /* Round if needed, handle resulting overflow. */
874 if ((status
& sim_fpu_status_rounded
))
876 f
->fraction
+= fraclsb
;
877 if ((f
->fraction
& IMPLICIT_2
))
890 STATIC_INLINE_SIM_FPU (int)
891 do_round (sim_fpu
*f
,
894 sim_fpu_denorm denorm
)
898 case sim_fpu_class_qnan
:
899 case sim_fpu_class_zero
:
900 case sim_fpu_class_infinity
:
903 case sim_fpu_class_snan
:
904 /* Quieten a SignalingNaN. */
905 f
->class = sim_fpu_class_qnan
;
906 return sim_fpu_status_invalid_snan
;
908 case sim_fpu_class_number
:
909 case sim_fpu_class_denorm
:
912 ASSERT (f
->fraction
< IMPLICIT_2
);
913 ASSERT (f
->fraction
>= IMPLICIT_1
);
914 if (f
->normal_exp
< NORMAL_EXPMIN
)
916 /* This number's exponent is too low to fit into the bits
917 available in the number. Round off any bits that will be
918 discarded as a result of denormalization. Edge case is
919 the implicit bit shifted to GUARD0 and then rounded
921 int shift
= NORMAL_EXPMIN
- f
->normal_exp
;
922 if (shift
+ NR_GUARDS
<= NR_FRAC_GUARD
+ 1
923 && !(denorm
& sim_fpu_denorm_zero
))
925 status
= do_normal_round (f
, shift
+ NR_GUARDS
, round
);
926 if (f
->fraction
== 0) /* Rounding underflowed. */
928 status
|= do_normal_underflow (f
, is_double
, round
);
930 else if (f
->normal_exp
< NORMAL_EXPMIN
) /* still underflow? */
932 status
|= sim_fpu_status_denorm
;
933 /* Any loss of precision when denormalizing is
934 underflow. Some processors check for underflow
935 before rounding, some after! */
936 if (status
& sim_fpu_status_inexact
)
937 status
|= sim_fpu_status_underflow
;
938 /* Flag that resultant value has been denormalized. */
939 f
->class = sim_fpu_class_denorm
;
941 else if ((denorm
& sim_fpu_denorm_underflow_inexact
))
943 if ((status
& sim_fpu_status_inexact
))
944 status
|= sim_fpu_status_underflow
;
949 status
= do_normal_underflow (f
, is_double
, round
);
952 else if (f
->normal_exp
> NORMAL_EXPMAX
)
955 status
= do_normal_overflow (f
, is_double
, round
);
959 status
= do_normal_round (f
, NR_GUARDS
, round
);
960 if (f
->fraction
== 0)
961 /* f->class = sim_fpu_class_zero; */
962 status
|= do_normal_underflow (f
, is_double
, round
);
963 else if (f
->normal_exp
> NORMAL_EXPMAX
)
964 /* Oops! rounding caused overflow. */
965 status
|= do_normal_overflow (f
, is_double
, round
);
967 ASSERT ((f
->class == sim_fpu_class_number
968 || f
->class == sim_fpu_class_denorm
)
969 <= (f
->fraction
< IMPLICIT_2
&& f
->fraction
>= IMPLICIT_1
));
977 sim_fpu_round_32 (sim_fpu
*f
,
979 sim_fpu_denorm denorm
)
981 return do_round (f
, 0, round
, denorm
);
985 sim_fpu_round_64 (sim_fpu
*f
,
987 sim_fpu_denorm denorm
)
989 return do_round (f
, 1, round
, denorm
);
997 sim_fpu_add (sim_fpu
*f
,
1001 if (sim_fpu_is_snan (l
))
1004 f
->class = sim_fpu_class_qnan
;
1005 return sim_fpu_status_invalid_snan
;
1007 if (sim_fpu_is_snan (r
))
1010 f
->class = sim_fpu_class_qnan
;
1011 return sim_fpu_status_invalid_snan
;
1013 if (sim_fpu_is_qnan (l
))
1018 if (sim_fpu_is_qnan (r
))
1023 if (sim_fpu_is_infinity (l
))
1025 if (sim_fpu_is_infinity (r
)
1026 && l
->sign
!= r
->sign
)
1029 return sim_fpu_status_invalid_isi
;
1034 if (sim_fpu_is_infinity (r
))
1039 if (sim_fpu_is_zero (l
))
1041 if (sim_fpu_is_zero (r
))
1044 f
->sign
= l
->sign
& r
->sign
;
1050 if (sim_fpu_is_zero (r
))
1057 int shift
= l
->normal_exp
- r
->normal_exp
;
1058 unsigned64 lfraction
;
1059 unsigned64 rfraction
;
1060 /* use exp of larger */
1061 if (shift
>= NR_FRAC_GUARD
)
1063 /* left has much bigger magnitude */
1065 return sim_fpu_status_inexact
;
1067 if (shift
<= - NR_FRAC_GUARD
)
1069 /* right has much bigger magnitude */
1071 return sim_fpu_status_inexact
;
1073 lfraction
= l
->fraction
;
1074 rfraction
= r
->fraction
;
1077 f
->normal_exp
= l
->normal_exp
;
1078 if (rfraction
& LSMASK64 (shift
- 1, 0))
1080 status
|= sim_fpu_status_inexact
;
1081 rfraction
|= LSBIT64 (shift
); /* Stick LSBit. */
1083 rfraction
>>= shift
;
1087 f
->normal_exp
= r
->normal_exp
;
1088 if (lfraction
& LSMASK64 (- shift
- 1, 0))
1090 status
|= sim_fpu_status_inexact
;
1091 lfraction
|= LSBIT64 (- shift
); /* Stick LSBit. */
1093 lfraction
>>= -shift
;
1097 f
->normal_exp
= r
->normal_exp
;
1100 /* Perform the addition. */
1102 lfraction
= - lfraction
;
1104 rfraction
= - rfraction
;
1105 f
->fraction
= lfraction
+ rfraction
;
1108 if (f
->fraction
== 0)
1115 f
->class = sim_fpu_class_number
;
1116 if (((signed64
) f
->fraction
) >= 0)
1121 f
->fraction
= - f
->fraction
;
1125 if ((f
->fraction
& IMPLICIT_2
))
1127 f
->fraction
= (f
->fraction
>> 1) | (f
->fraction
& 1);
1130 else if (f
->fraction
< IMPLICIT_1
)
1137 while (f
->fraction
< IMPLICIT_1
);
1139 ASSERT (f
->fraction
>= IMPLICIT_1
&& f
->fraction
< IMPLICIT_2
);
1145 INLINE_SIM_FPU (int)
1146 sim_fpu_sub (sim_fpu
*f
,
1150 if (sim_fpu_is_snan (l
))
1153 f
->class = sim_fpu_class_qnan
;
1154 return sim_fpu_status_invalid_snan
;
1156 if (sim_fpu_is_snan (r
))
1159 f
->class = sim_fpu_class_qnan
;
1160 return sim_fpu_status_invalid_snan
;
1162 if (sim_fpu_is_qnan (l
))
1167 if (sim_fpu_is_qnan (r
))
1172 if (sim_fpu_is_infinity (l
))
1174 if (sim_fpu_is_infinity (r
)
1175 && l
->sign
== r
->sign
)
1178 return sim_fpu_status_invalid_isi
;
1183 if (sim_fpu_is_infinity (r
))
1189 if (sim_fpu_is_zero (l
))
1191 if (sim_fpu_is_zero (r
))
1194 f
->sign
= l
->sign
& !r
->sign
;
1203 if (sim_fpu_is_zero (r
))
1210 int shift
= l
->normal_exp
- r
->normal_exp
;
1211 unsigned64 lfraction
;
1212 unsigned64 rfraction
;
1213 /* use exp of larger */
1214 if (shift
>= NR_FRAC_GUARD
)
1216 /* left has much bigger magnitude */
1218 return sim_fpu_status_inexact
;
1220 if (shift
<= - NR_FRAC_GUARD
)
1222 /* right has much bigger magnitude */
1225 return sim_fpu_status_inexact
;
1227 lfraction
= l
->fraction
;
1228 rfraction
= r
->fraction
;
1231 f
->normal_exp
= l
->normal_exp
;
1232 if (rfraction
& LSMASK64 (shift
- 1, 0))
1234 status
|= sim_fpu_status_inexact
;
1235 rfraction
|= LSBIT64 (shift
); /* Stick LSBit. */
1237 rfraction
>>= shift
;
1241 f
->normal_exp
= r
->normal_exp
;
1242 if (lfraction
& LSMASK64 (- shift
- 1, 0))
1244 status
|= sim_fpu_status_inexact
;
1245 lfraction
|= LSBIT64 (- shift
); /* Stick LSBit. */
1247 lfraction
>>= -shift
;
1251 f
->normal_exp
= r
->normal_exp
;
1254 /* Perform the subtraction. */
1256 lfraction
= - lfraction
;
1258 rfraction
= - rfraction
;
1259 f
->fraction
= lfraction
+ rfraction
;
1262 if (f
->fraction
== 0)
1269 f
->class = sim_fpu_class_number
;
1270 if (((signed64
) f
->fraction
) >= 0)
1275 f
->fraction
= - f
->fraction
;
1279 if ((f
->fraction
& IMPLICIT_2
))
1281 f
->fraction
= (f
->fraction
>> 1) | (f
->fraction
& 1);
1284 else if (f
->fraction
< IMPLICIT_1
)
1291 while (f
->fraction
< IMPLICIT_1
);
1293 ASSERT (f
->fraction
>= IMPLICIT_1
&& f
->fraction
< IMPLICIT_2
);
1299 INLINE_SIM_FPU (int)
1300 sim_fpu_mul (sim_fpu
*f
,
1304 if (sim_fpu_is_snan (l
))
1307 f
->class = sim_fpu_class_qnan
;
1308 return sim_fpu_status_invalid_snan
;
1310 if (sim_fpu_is_snan (r
))
1313 f
->class = sim_fpu_class_qnan
;
1314 return sim_fpu_status_invalid_snan
;
1316 if (sim_fpu_is_qnan (l
))
1321 if (sim_fpu_is_qnan (r
))
1326 if (sim_fpu_is_infinity (l
))
1328 if (sim_fpu_is_zero (r
))
1331 return sim_fpu_status_invalid_imz
;
1334 f
->sign
= l
->sign
^ r
->sign
;
1337 if (sim_fpu_is_infinity (r
))
1339 if (sim_fpu_is_zero (l
))
1342 return sim_fpu_status_invalid_imz
;
1345 f
->sign
= l
->sign
^ r
->sign
;
1348 if (sim_fpu_is_zero (l
) || sim_fpu_is_zero (r
))
1351 f
->sign
= l
->sign
^ r
->sign
;
1354 /* Calculate the mantissa by multiplying both 64bit numbers to get a
1359 unsigned64 nl
= l
->fraction
& 0xffffffff;
1360 unsigned64 nh
= l
->fraction
>> 32;
1361 unsigned64 ml
= r
->fraction
& 0xffffffff;
1362 unsigned64 mh
= r
->fraction
>>32;
1363 unsigned64 pp_ll
= ml
* nl
;
1364 unsigned64 pp_hl
= mh
* nl
;
1365 unsigned64 pp_lh
= ml
* nh
;
1366 unsigned64 pp_hh
= mh
* nh
;
1367 unsigned64 res2
= 0;
1368 unsigned64 res0
= 0;
1369 unsigned64 ps_hh__
= pp_hl
+ pp_lh
;
1370 if (ps_hh__
< pp_hl
)
1371 res2
+= UNSIGNED64 (0x100000000);
1372 pp_hl
= (ps_hh__
<< 32) & UNSIGNED64 (0xffffffff00000000);
1373 res0
= pp_ll
+ pp_hl
;
1376 res2
+= ((ps_hh__
>> 32) & 0xffffffff) + pp_hh
;
1380 f
->normal_exp
= l
->normal_exp
+ r
->normal_exp
;
1381 f
->sign
= l
->sign
^ r
->sign
;
1382 f
->class = sim_fpu_class_number
;
1384 /* Input is bounded by [1,2) ; [2^60,2^61)
1385 Output is bounded by [1,4) ; [2^120,2^122) */
1387 /* Adjust the exponent according to where the decimal point ended
1388 up in the high 64 bit word. In the source the decimal point
1389 was at NR_FRAC_GUARD. */
1390 f
->normal_exp
+= NR_FRAC_GUARD
+ 64 - (NR_FRAC_GUARD
* 2);
1392 /* The high word is bounded according to the above. Consequently
1393 it has never overflowed into IMPLICIT_2. */
1394 ASSERT (high
< LSBIT64 (((NR_FRAC_GUARD
+ 1) * 2) - 64));
1395 ASSERT (high
>= LSBIT64 ((NR_FRAC_GUARD
* 2) - 64));
1396 ASSERT (LSBIT64 (((NR_FRAC_GUARD
+ 1) * 2) - 64) < IMPLICIT_1
);
1403 if (low
& LSBIT64 (63))
1407 while (high
< IMPLICIT_1
);
1409 ASSERT (high
>= IMPLICIT_1
&& high
< IMPLICIT_2
);
1412 f
->fraction
= (high
| 1); /* sticky */
1413 return sim_fpu_status_inexact
;
1424 INLINE_SIM_FPU (int)
1425 sim_fpu_div (sim_fpu
*f
,
1429 if (sim_fpu_is_snan (l
))
1432 f
->class = sim_fpu_class_qnan
;
1433 return sim_fpu_status_invalid_snan
;
1435 if (sim_fpu_is_snan (r
))
1438 f
->class = sim_fpu_class_qnan
;
1439 return sim_fpu_status_invalid_snan
;
1441 if (sim_fpu_is_qnan (l
))
1444 f
->class = sim_fpu_class_qnan
;
1447 if (sim_fpu_is_qnan (r
))
1450 f
->class = sim_fpu_class_qnan
;
1453 if (sim_fpu_is_infinity (l
))
1455 if (sim_fpu_is_infinity (r
))
1458 return sim_fpu_status_invalid_idi
;
1463 f
->sign
= l
->sign
^ r
->sign
;
1467 if (sim_fpu_is_zero (l
))
1469 if (sim_fpu_is_zero (r
))
1472 return sim_fpu_status_invalid_zdz
;
1477 f
->sign
= l
->sign
^ r
->sign
;
1481 if (sim_fpu_is_infinity (r
))
1484 f
->sign
= l
->sign
^ r
->sign
;
1487 if (sim_fpu_is_zero (r
))
1489 f
->class = sim_fpu_class_infinity
;
1490 f
->sign
= l
->sign
^ r
->sign
;
1491 return sim_fpu_status_invalid_div0
;
1494 /* Calculate the mantissa by multiplying both 64bit numbers to get a
1497 /* quotient = ( ( numerator / denominator)
1498 x 2^(numerator exponent - denominator exponent)
1500 unsigned64 numerator
;
1501 unsigned64 denominator
;
1502 unsigned64 quotient
;
1505 f
->class = sim_fpu_class_number
;
1506 f
->sign
= l
->sign
^ r
->sign
;
1507 f
->normal_exp
= l
->normal_exp
- r
->normal_exp
;
1509 numerator
= l
->fraction
;
1510 denominator
= r
->fraction
;
1512 /* Fraction will be less than 1.0 */
1513 if (numerator
< denominator
)
1518 ASSERT (numerator
>= denominator
);
1520 /* Gain extra precision, already used one spare bit. */
1521 numerator
<<= NR_SPARE
;
1522 denominator
<<= NR_SPARE
;
1524 /* Does divide one bit at a time. Optimize??? */
1526 bit
= (IMPLICIT_1
<< NR_SPARE
);
1529 if (numerator
>= denominator
)
1532 numerator
-= denominator
;
1538 /* Discard (but save) the extra bits. */
1539 if ((quotient
& LSMASK64 (NR_SPARE
-1, 0)))
1540 quotient
= (quotient
>> NR_SPARE
) | 1;
1542 quotient
= (quotient
>> NR_SPARE
);
1544 f
->fraction
= quotient
;
1545 ASSERT (f
->fraction
>= IMPLICIT_1
&& f
->fraction
< IMPLICIT_2
);
1548 f
->fraction
|= 1; /* Stick remaining bits. */
1549 return sim_fpu_status_inexact
;
1557 INLINE_SIM_FPU (int)
1558 sim_fpu_rem (sim_fpu
*f
,
1562 if (sim_fpu_is_snan (l
))
1565 f
->class = sim_fpu_class_qnan
;
1566 return sim_fpu_status_invalid_snan
;
1568 if (sim_fpu_is_snan (r
))
1571 f
->class = sim_fpu_class_qnan
;
1572 return sim_fpu_status_invalid_snan
;
1574 if (sim_fpu_is_qnan (l
))
1577 f
->class = sim_fpu_class_qnan
;
1580 if (sim_fpu_is_qnan (r
))
1583 f
->class = sim_fpu_class_qnan
;
1586 if (sim_fpu_is_infinity (l
))
1589 return sim_fpu_status_invalid_irx
;
1591 if (sim_fpu_is_zero (r
))
1594 return sim_fpu_status_invalid_div0
;
1596 if (sim_fpu_is_zero (l
))
1601 if (sim_fpu_is_infinity (r
))
1609 /* Remainder is calculated as l-n*r, where n is l/r rounded to the
1610 nearest integer. The variable n is rounded half even. */
1612 sim_fpu_div (&n
, l
, r
);
1613 sim_fpu_round_64 (&n
, 0, 0);
1615 if (n
.normal_exp
< -1) /* If n looks like zero just return l. */
1620 else if (n
.class == sim_fpu_class_number
1621 && n
.normal_exp
<= (NR_FRAC_GUARD
)) /* If not too large round. */
1622 do_normal_round (&n
, (NR_FRAC_GUARD
) - n
.normal_exp
, sim_fpu_round_near
);
1624 /* Mark 0's as zero so multiply can detect zero. */
1625 if (n
.fraction
== 0)
1626 n
.class = sim_fpu_class_zero
;
1628 /* Calculate n*r. */
1629 sim_fpu_mul (&tmp
, &n
, r
);
1630 sim_fpu_round_64 (&tmp
, 0, 0);
1632 /* Finally calculate l-n*r. */
1633 sim_fpu_sub (f
, l
, &tmp
);
1640 INLINE_SIM_FPU (int)
1641 sim_fpu_max (sim_fpu
*f
,
1645 if (sim_fpu_is_snan (l
))
1648 f
->class = sim_fpu_class_qnan
;
1649 return sim_fpu_status_invalid_snan
;
1651 if (sim_fpu_is_snan (r
))
1654 f
->class = sim_fpu_class_qnan
;
1655 return sim_fpu_status_invalid_snan
;
1657 if (sim_fpu_is_qnan (l
))
1662 if (sim_fpu_is_qnan (r
))
1667 if (sim_fpu_is_infinity (l
))
1669 if (sim_fpu_is_infinity (r
)
1670 && l
->sign
== r
->sign
)
1673 return sim_fpu_status_invalid_isi
;
1676 *f
= *r
; /* -inf < anything */
1678 *f
= *l
; /* +inf > anything */
1681 if (sim_fpu_is_infinity (r
))
1684 *f
= *l
; /* anything > -inf */
1686 *f
= *r
; /* anything < +inf */
1689 if (l
->sign
> r
->sign
)
1691 *f
= *r
; /* -ve < +ve */
1694 if (l
->sign
< r
->sign
)
1696 *f
= *l
; /* +ve > -ve */
1699 ASSERT (l
->sign
== r
->sign
);
1700 if (l
->normal_exp
> r
->normal_exp
1701 || (l
->normal_exp
== r
->normal_exp
1702 && l
->fraction
> r
->fraction
))
1706 *f
= *r
; /* -ve < -ve */
1708 *f
= *l
; /* +ve > +ve */
1715 *f
= *l
; /* -ve > -ve */
1717 *f
= *r
; /* +ve < +ve */
1723 INLINE_SIM_FPU (int)
1724 sim_fpu_min (sim_fpu
*f
,
1728 if (sim_fpu_is_snan (l
))
1731 f
->class = sim_fpu_class_qnan
;
1732 return sim_fpu_status_invalid_snan
;
1734 if (sim_fpu_is_snan (r
))
1737 f
->class = sim_fpu_class_qnan
;
1738 return sim_fpu_status_invalid_snan
;
1740 if (sim_fpu_is_qnan (l
))
1745 if (sim_fpu_is_qnan (r
))
1750 if (sim_fpu_is_infinity (l
))
1752 if (sim_fpu_is_infinity (r
)
1753 && l
->sign
== r
->sign
)
1756 return sim_fpu_status_invalid_isi
;
1759 *f
= *l
; /* -inf < anything */
1761 *f
= *r
; /* +inf > anthing */
1764 if (sim_fpu_is_infinity (r
))
1767 *f
= *r
; /* anything > -inf */
1769 *f
= *l
; /* anything < +inf */
1772 if (l
->sign
> r
->sign
)
1774 *f
= *l
; /* -ve < +ve */
1777 if (l
->sign
< r
->sign
)
1779 *f
= *r
; /* +ve > -ve */
1782 ASSERT (l
->sign
== r
->sign
);
1783 if (l
->normal_exp
> r
->normal_exp
1784 || (l
->normal_exp
== r
->normal_exp
1785 && l
->fraction
> r
->fraction
))
1789 *f
= *l
; /* -ve < -ve */
1791 *f
= *r
; /* +ve > +ve */
1798 *f
= *r
; /* -ve > -ve */
1800 *f
= *l
; /* +ve < +ve */
1806 INLINE_SIM_FPU (int)
1807 sim_fpu_neg (sim_fpu
*f
,
1810 if (sim_fpu_is_snan (r
))
1813 f
->class = sim_fpu_class_qnan
;
1814 return sim_fpu_status_invalid_snan
;
1816 if (sim_fpu_is_qnan (r
))
1827 INLINE_SIM_FPU (int)
1828 sim_fpu_abs (sim_fpu
*f
,
1833 if (sim_fpu_is_snan (r
))
1835 f
->class = sim_fpu_class_qnan
;
1836 return sim_fpu_status_invalid_snan
;
1842 INLINE_SIM_FPU (int)
1843 sim_fpu_inv (sim_fpu
*f
,
1846 return sim_fpu_div (f
, &sim_fpu_one
, r
);
1850 INLINE_SIM_FPU (int)
1851 sim_fpu_sqrt (sim_fpu
*f
,
1854 if (sim_fpu_is_snan (r
))
1857 return sim_fpu_status_invalid_snan
;
1859 if (sim_fpu_is_qnan (r
))
1864 if (sim_fpu_is_zero (r
))
1866 f
->class = sim_fpu_class_zero
;
1871 if (sim_fpu_is_infinity (r
))
1876 return sim_fpu_status_invalid_sqrt
;
1880 f
->class = sim_fpu_class_infinity
;
1889 return sim_fpu_status_invalid_sqrt
;
1892 /* @(#)e_sqrt.c 5.1 93/09/24 */
1894 * ====================================================
1895 * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
1897 * Developed at SunPro, a Sun Microsystems, Inc. business.
1898 * Permission to use, copy, modify, and distribute this
1899 * software is freely granted, provided that this notice
1901 * ====================================================
1904 /* __ieee754_sqrt(x)
1905 * Return correctly rounded sqrt.
1906 * ------------------------------------------
1907 * | Use the hardware sqrt if you have one |
1908 * ------------------------------------------
1910 * Bit by bit method using integer arithmetic. (Slow, but portable)
1912 * Scale x to y in [1,4) with even powers of 2:
1913 * find an integer k such that 1 <= (y=x*2^(2k)) < 4, then
1914 * sqrt(x) = 2^k * sqrt(y)
1917 - sqrt ( x*2^(2m) ) = sqrt(x).2^m ; m even
1918 - sqrt ( x*2^(2m + 1) ) = sqrt(2.x).2^m ; m odd
1920 - y = ((m even) ? x : 2.x)
1922 - y in [1, 4) ; [IMPLICIT_1,IMPLICIT_4)
1924 - sqrt (y) in [1, 2) ; [IMPLICIT_1,IMPLICIT_2)
1926 * 2. Bit by bit computation
1927 * Let q = sqrt(y) truncated to i bit after binary point (q = 1),
1930 * s = 2*q , and y = 2 * ( y - q ). (1)
1933 * To compute q from q , one checks whether
1937 * (q + 2 ) <= y. (2)
1940 * If (2) is false, then q = q ; otherwise q = q + 2 .
1943 * With some algebraic manipulation, it is not difficult to see
1944 * that (2) is equivalent to
1949 * The advantage of (3) is that s and y can be computed by
1951 * the following recurrence formula:
1954 * s = s , y = y ; (4)
1963 * s = s + 2 , y = y - s - 2 (5)
1968 - NOTE: y = 2 (y - s - 2 )
1971 * One may easily use induction to prove (4) and (5).
1972 * Note. Since the left hand side of (3) contain only i+2 bits,
1973 * it does not necessary to do a full (53-bit) comparison
1976 * After generating the 53 bits result, we compute one more bit.
1977 * Together with the remainder, we can decide whether the
1978 * result is exact, bigger than 1/2ulp, or less than 1/2ulp
1979 * (it will never equal to 1/2ulp).
1980 * The rounding mode can be detected by checking whether
1981 * huge + tiny is equal to huge, and whether huge - tiny is
1982 * equal to huge for some floating point number "huge" and "tiny".
1985 * sqrt(+-0) = +-0 ... exact
1987 * sqrt(-ve) = NaN ... with invalid signal
1988 * sqrt(NaN) = NaN ... with invalid signal for signalling NaN
1990 * Other methods : see the appended file at the end of the program below.
1995 /* Generate sqrt(x) bit by bit. */
2001 f
->class = sim_fpu_class_number
;
2004 f
->normal_exp
= (r
->normal_exp
>> 1); /* exp = [exp/2] */
2006 /* Odd exp, double x to make it even. */
2007 ASSERT (y
>= IMPLICIT_1
&& y
< IMPLICIT_4
);
2008 if ((r
->normal_exp
& 1))
2012 ASSERT (y
>= IMPLICIT_1
&& y
< (IMPLICIT_2
<< 1));
2014 /* Let loop determine first value of s (either 1 or 2) */
2021 unsigned64 t
= s
+ b
;
2032 ASSERT (q
>= IMPLICIT_1
&& q
< IMPLICIT_2
);
2036 f
->fraction
|= 1; /* Stick remaining bits. */
2037 return sim_fpu_status_inexact
;
2045 /* int/long <-> sim_fpu */
2047 INLINE_SIM_FPU (int)
2048 sim_fpu_i32to (sim_fpu
*f
,
2050 sim_fpu_round round
)
2056 INLINE_SIM_FPU (int)
2057 sim_fpu_u32to (sim_fpu
*f
,
2059 sim_fpu_round round
)
2065 INLINE_SIM_FPU (int)
2066 sim_fpu_i64to (sim_fpu
*f
,
2068 sim_fpu_round round
)
2074 INLINE_SIM_FPU (int)
2075 sim_fpu_u64to (sim_fpu
*f
,
2077 sim_fpu_round round
)
2084 INLINE_SIM_FPU (int)
2085 sim_fpu_to32i (signed32
*i
,
2087 sim_fpu_round round
)
2090 int status
= fpu2i (&i64
, f
, 0, round
);
2095 INLINE_SIM_FPU (int)
2096 sim_fpu_to32u (unsigned32
*u
,
2098 sim_fpu_round round
)
2101 int status
= fpu2u (&u64
, f
, 0);
2106 INLINE_SIM_FPU (int)
2107 sim_fpu_to64i (signed64
*i
,
2109 sim_fpu_round round
)
2111 return fpu2i (i
, f
, 1, round
);
2115 INLINE_SIM_FPU (int)
2116 sim_fpu_to64u (unsigned64
*u
,
2118 sim_fpu_round round
)
2120 return fpu2u (u
, f
, 1);
2125 /* sim_fpu -> host format */
2128 INLINE_SIM_FPU (float)
2129 sim_fpu_2f (const sim_fpu
*f
)
2136 INLINE_SIM_FPU (double)
2137 sim_fpu_2d (const sim_fpu
*s
)
2140 if (sim_fpu_is_snan (s
))
2144 n
.class = sim_fpu_class_qnan
;
2145 val
.i
= pack_fpu (&n
, 1);
2149 val
.i
= pack_fpu (s
, 1);
2156 INLINE_SIM_FPU (void)
2157 sim_fpu_f2 (sim_fpu
*f
,
2162 unpack_fpu (f
, val
.i
, 1);
2167 INLINE_SIM_FPU (void)
2168 sim_fpu_d2 (sim_fpu
*f
,
2173 unpack_fpu (f
, val
.i
, 1);
2179 INLINE_SIM_FPU (int)
2180 sim_fpu_is_nan (const sim_fpu
*d
)
2184 case sim_fpu_class_qnan
:
2185 case sim_fpu_class_snan
:
2192 INLINE_SIM_FPU (int)
2193 sim_fpu_is_qnan (const sim_fpu
*d
)
2197 case sim_fpu_class_qnan
:
2204 INLINE_SIM_FPU (int)
2205 sim_fpu_is_snan (const sim_fpu
*d
)
2209 case sim_fpu_class_snan
:
2216 INLINE_SIM_FPU (int)
2217 sim_fpu_is_zero (const sim_fpu
*d
)
2221 case sim_fpu_class_zero
:
2228 INLINE_SIM_FPU (int)
2229 sim_fpu_is_infinity (const sim_fpu
*d
)
2233 case sim_fpu_class_infinity
:
2240 INLINE_SIM_FPU (int)
2241 sim_fpu_is_number (const sim_fpu
*d
)
2245 case sim_fpu_class_denorm
:
2246 case sim_fpu_class_number
:
2253 INLINE_SIM_FPU (int)
2254 sim_fpu_is_denorm (const sim_fpu
*d
)
2258 case sim_fpu_class_denorm
:
2266 INLINE_SIM_FPU (int)
2267 sim_fpu_sign (const sim_fpu
*d
)
2273 INLINE_SIM_FPU (int)
2274 sim_fpu_exp (const sim_fpu
*d
)
2276 return d
->normal_exp
;
2280 INLINE_SIM_FPU (unsigned64
)
2281 sim_fpu_fraction (const sim_fpu
*d
)
2287 INLINE_SIM_FPU (unsigned64
)
2288 sim_fpu_guard (const sim_fpu
*d
, int is_double
)
2291 unsigned64 guardmask
= LSMASK64 (NR_GUARDS
- 1, 0);
2292 rv
= (d
->fraction
& guardmask
) >> NR_PAD
;
2297 INLINE_SIM_FPU (int)
2298 sim_fpu_is (const sim_fpu
*d
)
2302 case sim_fpu_class_qnan
:
2303 return SIM_FPU_IS_QNAN
;
2304 case sim_fpu_class_snan
:
2305 return SIM_FPU_IS_SNAN
;
2306 case sim_fpu_class_infinity
:
2308 return SIM_FPU_IS_NINF
;
2310 return SIM_FPU_IS_PINF
;
2311 case sim_fpu_class_number
:
2313 return SIM_FPU_IS_NNUMBER
;
2315 return SIM_FPU_IS_PNUMBER
;
2316 case sim_fpu_class_denorm
:
2318 return SIM_FPU_IS_NDENORM
;
2320 return SIM_FPU_IS_PDENORM
;
2321 case sim_fpu_class_zero
:
2323 return SIM_FPU_IS_NZERO
;
2325 return SIM_FPU_IS_PZERO
;
2332 INLINE_SIM_FPU (int)
2333 sim_fpu_cmp (const sim_fpu
*l
, const sim_fpu
*r
)
2336 sim_fpu_sub (&res
, l
, r
);
2337 return sim_fpu_is (&res
);
2340 INLINE_SIM_FPU (int)
2341 sim_fpu_is_lt (const sim_fpu
*l
, const sim_fpu
*r
)
2344 sim_fpu_lt (&status
, l
, r
);
2348 INLINE_SIM_FPU (int)
2349 sim_fpu_is_le (const sim_fpu
*l
, const sim_fpu
*r
)
2352 sim_fpu_le (&is
, l
, r
);
2356 INLINE_SIM_FPU (int)
2357 sim_fpu_is_eq (const sim_fpu
*l
, const sim_fpu
*r
)
2360 sim_fpu_eq (&is
, l
, r
);
2364 INLINE_SIM_FPU (int)
2365 sim_fpu_is_ne (const sim_fpu
*l
, const sim_fpu
*r
)
2368 sim_fpu_ne (&is
, l
, r
);
2372 INLINE_SIM_FPU (int)
2373 sim_fpu_is_ge (const sim_fpu
*l
, const sim_fpu
*r
)
2376 sim_fpu_ge (&is
, l
, r
);
2380 INLINE_SIM_FPU (int)
2381 sim_fpu_is_gt (const sim_fpu
*l
, const sim_fpu
*r
)
2384 sim_fpu_gt (&is
, l
, r
);
2389 /* Compare operators */
2391 INLINE_SIM_FPU (int)
2392 sim_fpu_lt (int *is
,
2396 if (!sim_fpu_is_nan (l
) && !sim_fpu_is_nan (r
))
2400 lval
.i
= pack_fpu (l
, 1);
2401 rval
.i
= pack_fpu (r
, 1);
2402 (*is
) = (lval
.d
< rval
.d
);
2405 else if (sim_fpu_is_snan (l
) || sim_fpu_is_snan (r
))
2408 return sim_fpu_status_invalid_snan
;
2413 return sim_fpu_status_invalid_qnan
;
2417 INLINE_SIM_FPU (int)
2418 sim_fpu_le (int *is
,
2422 if (!sim_fpu_is_nan (l
) && !sim_fpu_is_nan (r
))
2426 lval
.i
= pack_fpu (l
, 1);
2427 rval
.i
= pack_fpu (r
, 1);
2428 *is
= (lval
.d
<= rval
.d
);
2431 else if (sim_fpu_is_snan (l
) || sim_fpu_is_snan (r
))
2434 return sim_fpu_status_invalid_snan
;
2439 return sim_fpu_status_invalid_qnan
;
2443 INLINE_SIM_FPU (int)
2444 sim_fpu_eq (int *is
,
2448 if (!sim_fpu_is_nan (l
) && !sim_fpu_is_nan (r
))
2452 lval
.i
= pack_fpu (l
, 1);
2453 rval
.i
= pack_fpu (r
, 1);
2454 (*is
) = (lval
.d
== rval
.d
);
2457 else if (sim_fpu_is_snan (l
) || sim_fpu_is_snan (r
))
2460 return sim_fpu_status_invalid_snan
;
2465 return sim_fpu_status_invalid_qnan
;
2469 INLINE_SIM_FPU (int)
2470 sim_fpu_ne (int *is
,
2474 if (!sim_fpu_is_nan (l
) && !sim_fpu_is_nan (r
))
2478 lval
.i
= pack_fpu (l
, 1);
2479 rval
.i
= pack_fpu (r
, 1);
2480 (*is
) = (lval
.d
!= rval
.d
);
2483 else if (sim_fpu_is_snan (l
) || sim_fpu_is_snan (r
))
2486 return sim_fpu_status_invalid_snan
;
2491 return sim_fpu_status_invalid_qnan
;
2495 INLINE_SIM_FPU (int)
2496 sim_fpu_ge (int *is
,
2500 return sim_fpu_le (is
, r
, l
);
2503 INLINE_SIM_FPU (int)
2504 sim_fpu_gt (int *is
,
2508 return sim_fpu_lt (is
, r
, l
);
2512 /* A number of useful constants */
2514 #if EXTERN_SIM_FPU_P
2515 const sim_fpu sim_fpu_zero
= {
2516 sim_fpu_class_zero
, 0, 0, 0
2518 const sim_fpu sim_fpu_qnan
= {
2519 sim_fpu_class_qnan
, 0, 0, 0
2521 const sim_fpu sim_fpu_one
= {
2522 sim_fpu_class_number
, 0, IMPLICIT_1
, 0
2524 const sim_fpu sim_fpu_two
= {
2525 sim_fpu_class_number
, 0, IMPLICIT_1
, 1
2527 const sim_fpu sim_fpu_max32
= {
2528 sim_fpu_class_number
, 0, LSMASK64 (NR_FRAC_GUARD
, NR_GUARDS32
), NORMAL_EXPMAX32
2530 const sim_fpu sim_fpu_max64
= {
2531 sim_fpu_class_number
, 0, LSMASK64 (NR_FRAC_GUARD
, NR_GUARDS64
), NORMAL_EXPMAX64
2538 INLINE_SIM_FPU (void)
2539 sim_fpu_print_fpu (const sim_fpu
*f
,
2540 sim_fpu_print_func
*print
,
2543 sim_fpu_printn_fpu (f
, print
, -1, arg
);
2546 INLINE_SIM_FPU (void)
2547 sim_fpu_printn_fpu (const sim_fpu
*f
,
2548 sim_fpu_print_func
*print
,
2552 print (arg
, "%s", f
->sign
? "-" : "+");
2555 case sim_fpu_class_qnan
:
2557 print_bits (f
->fraction
, NR_FRAC_GUARD
- 1, digits
, print
, arg
);
2558 print (arg
, "*QuietNaN");
2560 case sim_fpu_class_snan
:
2562 print_bits (f
->fraction
, NR_FRAC_GUARD
- 1, digits
, print
, arg
);
2563 print (arg
, "*SignalNaN");
2565 case sim_fpu_class_zero
:
2568 case sim_fpu_class_infinity
:
2571 case sim_fpu_class_number
:
2572 case sim_fpu_class_denorm
:
2574 print_bits (f
->fraction
, NR_FRAC_GUARD
- 1, digits
, print
, arg
);
2575 print (arg
, "*2^%+d", f
->normal_exp
);
2576 ASSERT (f
->fraction
>= IMPLICIT_1
);
2577 ASSERT (f
->fraction
< IMPLICIT_2
);
2582 INLINE_SIM_FPU (void)
2583 sim_fpu_print_status (int status
,
2584 sim_fpu_print_func
*print
,
2588 const char *prefix
= "";
2591 switch ((sim_fpu_status
) (status
& i
))
2593 case sim_fpu_status_denorm
:
2594 print (arg
, "%sD", prefix
);
2596 case sim_fpu_status_invalid_snan
:
2597 print (arg
, "%sSNaN", prefix
);
2599 case sim_fpu_status_invalid_qnan
:
2600 print (arg
, "%sQNaN", prefix
);
2602 case sim_fpu_status_invalid_isi
:
2603 print (arg
, "%sISI", prefix
);
2605 case sim_fpu_status_invalid_idi
:
2606 print (arg
, "%sIDI", prefix
);
2608 case sim_fpu_status_invalid_zdz
:
2609 print (arg
, "%sZDZ", prefix
);
2611 case sim_fpu_status_invalid_imz
:
2612 print (arg
, "%sIMZ", prefix
);
2614 case sim_fpu_status_invalid_cvi
:
2615 print (arg
, "%sCVI", prefix
);
2617 case sim_fpu_status_invalid_cmp
:
2618 print (arg
, "%sCMP", prefix
);
2620 case sim_fpu_status_invalid_sqrt
:
2621 print (arg
, "%sSQRT", prefix
);
2623 case sim_fpu_status_invalid_irx
:
2624 print (arg
, "%sIRX", prefix
);
2626 case sim_fpu_status_inexact
:
2627 print (arg
, "%sX", prefix
);
2629 case sim_fpu_status_overflow
:
2630 print (arg
, "%sO", prefix
);
2632 case sim_fpu_status_underflow
:
2633 print (arg
, "%sU", prefix
);
2635 case sim_fpu_status_invalid_div0
:
2636 print (arg
, "%s/", prefix
);
2638 case sim_fpu_status_rounded
:
2639 print (arg
, "%sR", prefix
);