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[thirdparty/binutils-gdb.git] / sim / cr16 / simops.c
1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2023 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 /* This must come before any other includes. */
21 #include "defs.h"
22
23 #include <signal.h>
24 #include <errno.h>
25 #include <sys/types.h>
26 #include <sys/stat.h>
27 #ifdef HAVE_UNISTD_H
28 #include <unistd.h>
29 #endif
30 #include <string.h>
31 #include <time.h>
32 #include <sys/time.h>
33
34 #include "bfd.h"
35
36 #include "sim-main.h"
37 #include "sim-signal.h"
38 #include "simops.h"
39 #include "target-newlib-syscall.h"
40
41 #include "cr16-sim.h"
42
43 #ifdef HAVE_UTIME_H
44 #include <utime.h>
45 #endif
46 #include <sys/wait.h>
47
48 #define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
49
50 enum op_types {
51 OP_VOID,
52 OP_CONSTANT3,
53 OP_UCONSTANT3,
54 OP_CONSTANT4,
55 OP_CONSTANT4_1,
56 OP_CONSTANT5,
57 OP_CONSTANT6,
58 OP_CONSTANT16,
59 OP_UCONSTANT16,
60 OP_CONSTANT20,
61 OP_UCONSTANT20,
62 OP_CONSTANT32,
63 OP_UCONSTANT32,
64 OP_MEMREF,
65 OP_MEMREF2,
66 OP_MEMREF3,
67
68 OP_DISP5,
69 OP_DISP17,
70 OP_DISP25,
71 OP_DISPE9,
72 //OP_ABS20,
73 OP_ABS20_OUTPUT,
74 //OP_ABS24,
75 OP_ABS24_OUTPUT,
76
77 OP_R_BASE_DISPS16,
78 OP_R_BASE_DISP20,
79 OP_R_BASE_DISPS20,
80 OP_R_BASE_DISPE20,
81
82 OP_RP_BASE_DISPE0,
83 OP_RP_BASE_DISP4,
84 OP_RP_BASE_DISPE4,
85 OP_RP_BASE_DISP14,
86 OP_RP_BASE_DISP16,
87 OP_RP_BASE_DISP20,
88 OP_RP_BASE_DISPS20,
89 OP_RP_BASE_DISPE20,
90
91 OP_R_INDEX7_ABS20,
92 OP_R_INDEX8_ABS20,
93
94 OP_RP_INDEX_DISP0,
95 OP_RP_INDEX_DISP14,
96 OP_RP_INDEX_DISP20,
97 OP_RP_INDEX_DISPS20,
98
99 OP_REG,
100 OP_REGP,
101 OP_PROC_REG,
102 OP_PROC_REGP,
103 OP_COND,
104 OP_RA
105 };
106
107
108 enum {
109 PSR_MASK = (PSR_I_BIT
110 | PSR_P_BIT
111 | PSR_E_BIT
112 | PSR_N_BIT
113 | PSR_Z_BIT
114 | PSR_F_BIT
115 | PSR_U_BIT
116 | PSR_L_BIT
117 | PSR_T_BIT
118 | PSR_C_BIT),
119 /* The following bits in the PSR _can't_ be set by instructions such
120 as mvtc. */
121 PSR_HW_MASK = (PSR_MASK)
122 };
123
124 /* cond Code Condition True State
125 * EQ Equal Z flag is 1
126 * NE Not Equal Z flag is 0
127 * CS Carry Set C flag is 1
128 * CC Carry Clear C flag is 0
129 * HI Higher L flag is 1
130 * LS Lower or Same L flag is 0
131 * GT Greater Than N flag is 1
132 * LE Less Than or Equal To N flag is 0
133 * FS Flag Set F flag is 1
134 * FC Flag Clear F flag is 0
135 * LO Lower Z and L flags are 0
136 * HS Higher or Same Z or L flag is 1
137 * LT Less Than Z and N flags are 0
138 * GE Greater Than or Equal To Z or N flag is 1. */
139
140 static int cond_stat(int cc)
141 {
142 switch (cc)
143 {
144 case 0: return PSR_Z; break;
145 case 1: return !PSR_Z; break;
146 case 2: return PSR_C; break;
147 case 3: return !PSR_C; break;
148 case 4: return PSR_L; break;
149 case 5: return !PSR_L; break;
150 case 6: return PSR_N; break;
151 case 7: return !PSR_N; break;
152 case 8: return PSR_F; break;
153 case 9: return !PSR_F; break;
154 case 10: return !PSR_Z && !PSR_L; break;
155 case 11: return PSR_Z || PSR_L; break;
156 case 12: return !PSR_Z && !PSR_N; break;
157 case 13: return PSR_Z || PSR_N; break;
158 case 14: return 1; break; /*ALWAYS. */
159 default:
160 // case NEVER: return false; break;
161 //case NO_COND_CODE:
162 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
163 return 0; break;
164 }
165 return 0;
166 }
167
168
169 creg_t
170 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p)
171 {
172 /* A MASK bit is set when the corresponding bit in the CR should
173 be left alone. */
174 /* This assumes that (VAL & MASK) == 0. */
175 switch (cr)
176 {
177 case PSR_CR:
178 if (psw_hw_p)
179 val &= PSR_HW_MASK;
180 #if 0
181 else
182 val &= PSR_MASK;
183 sim_io_printf
184 (sd,
185 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
186 EXCEPTION (SIM_SIGILL);
187 #endif
188 /* keep an up-to-date psw around for tracing. */
189 State.trace.psw = (State.trace.psw & mask) | val;
190 break;
191 default:
192 break;
193 }
194 /* only issue an update if the register is being changed. */
195 if ((State.cregs[cr] & ~mask) != val)
196 SLOT_PEND_MASK (State.cregs[cr], mask, val);
197
198 return val;
199 }
200
201 #ifdef DEBUG
202 static void trace_input_func (SIM_DESC sd,
203 const char *name,
204 enum op_types in1,
205 enum op_types in2,
206 enum op_types in3);
207
208 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
209
210 #ifndef SIZE_INSTRUCTION
211 #define SIZE_INSTRUCTION 8
212 #endif
213
214 #ifndef SIZE_OPERANDS
215 #define SIZE_OPERANDS 18
216 #endif
217
218 #ifndef SIZE_VALUES
219 #define SIZE_VALUES 13
220 #endif
221
222 #ifndef SIZE_LOCATION
223 #define SIZE_LOCATION 20
224 #endif
225
226 #ifndef SIZE_PC
227 #define SIZE_PC 4
228 #endif
229
230 #ifndef SIZE_LINE_NUMBER
231 #define SIZE_LINE_NUMBER 2
232 #endif
233
234 static void
235 trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
236 {
237 char *comma;
238 enum op_types in[3];
239 int i;
240 char buf[1024];
241 char *p;
242 long tmp;
243 char *type;
244 const char *filename;
245 const char *functionname;
246 unsigned int linenumber;
247 bfd_vma byte_pc;
248
249 if ((cr16_debug & DEBUG_TRACE) == 0)
250 return;
251
252 switch (State.ins_type)
253 {
254 default:
255 case INS_UNKNOWN: type = " ?"; break;
256 }
257
258 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
259 sim_io_printf (sd,
260 "0x%.*x %s: %-*s ",
261 SIZE_PC, (unsigned)PC,
262 type,
263 SIZE_INSTRUCTION, name);
264
265 else
266 {
267 buf[0] = '\0';
268 byte_pc = PC;
269 if (STATE_TEXT_SECTION (sd)
270 && byte_pc >= STATE_TEXT_START (sd)
271 && byte_pc < STATE_TEXT_END (sd))
272 {
273 filename = (const char *)0;
274 functionname = (const char *)0;
275 linenumber = 0;
276 if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
277 STATE_TEXT_SECTION (sd),
278 (struct bfd_symbol **)0,
279 byte_pc - STATE_TEXT_START (sd),
280 &filename, &functionname, &linenumber))
281 {
282 p = buf;
283 if (linenumber)
284 {
285 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
286 p += strlen (p);
287 }
288 else
289 {
290 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
291 p += SIZE_LINE_NUMBER+2;
292 }
293
294 if (functionname)
295 {
296 sprintf (p, "%s ", functionname);
297 p += strlen (p);
298 }
299 else if (filename)
300 {
301 char *q = strrchr (filename, '/');
302 sprintf (p, "%s ", (q) ? q+1 : filename);
303 p += strlen (p);
304 }
305
306 if (*p == ' ')
307 *p = '\0';
308 }
309 }
310
311 sim_io_printf (sd,
312 "0x%.*x %s: %-*.*s %-*s ",
313 SIZE_PC, (unsigned)PC,
314 type,
315 SIZE_LOCATION, SIZE_LOCATION, buf,
316 SIZE_INSTRUCTION, name);
317 }
318
319 in[0] = in1;
320 in[1] = in2;
321 in[2] = in3;
322 comma = "";
323 p = buf;
324 for (i = 0; i < 3; i++)
325 {
326 switch (in[i])
327 {
328 case OP_VOID:
329 break;
330
331 case OP_REG:
332 case OP_REGP:
333 sprintf (p, "%sr%d", comma, OP[i]);
334 p += strlen (p);
335 comma = ",";
336 break;
337
338 case OP_PROC_REG:
339 sprintf (p, "%scr%d", comma, OP[i]);
340 p += strlen (p);
341 comma = ",";
342 break;
343
344 case OP_CONSTANT16:
345 sprintf (p, "%s%d", comma, OP[i]);
346 p += strlen (p);
347 comma = ",";
348 break;
349
350 case OP_CONSTANT4:
351 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
352 p += strlen (p);
353 comma = ",";
354 break;
355
356 case OP_CONSTANT3:
357 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
358 p += strlen (p);
359 comma = ",";
360 break;
361
362 case OP_MEMREF:
363 sprintf (p, "%s@r%d", comma, OP[i]);
364 p += strlen (p);
365 comma = ",";
366 break;
367
368 case OP_MEMREF2:
369 sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]);
370 p += strlen (p);
371 comma = ",";
372 break;
373
374 case OP_MEMREF3:
375 sprintf (p, "%s@%d", comma, OP[i]);
376 p += strlen (p);
377 comma = ",";
378 break;
379 }
380 }
381
382 if ((cr16_debug & DEBUG_VALUES) == 0)
383 {
384 *p++ = '\n';
385 *p = '\0';
386 sim_io_printf (sd, "%s", buf);
387 }
388 else
389 {
390 *p = '\0';
391 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
392
393 p = buf;
394 for (i = 0; i < 3; i++)
395 {
396 buf[0] = '\0';
397 switch (in[i])
398 {
399 case OP_VOID:
400 sim_io_printf (sd, "%*s", SIZE_VALUES, "");
401 break;
402
403 case OP_REG:
404 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
405 (uint16_t) GPR (OP[i]));
406 break;
407
408 case OP_REGP:
409 tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1)));
410 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
411 break;
412
413 case OP_PROC_REG:
414 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
415 (uint16_t) CREG (OP[i]));
416 break;
417
418 case OP_CONSTANT16:
419 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
420 (uint16_t)OP[i]);
421 break;
422
423 case OP_CONSTANT4:
424 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
425 (uint16_t)SEXT4(OP[i]));
426 break;
427
428 case OP_CONSTANT3:
429 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
430 (uint16_t)SEXT3(OP[i]));
431 break;
432
433 case OP_MEMREF2:
434 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
435 (uint16_t)OP[i]);
436 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
437 (uint16_t)GPR (OP[i + 1]));
438 i++;
439 break;
440 }
441 }
442 }
443
444 sim_io_flush_stdout (sd);
445 }
446
447 static void
448 do_trace_output_flush (SIM_DESC sd)
449 {
450 sim_io_flush_stdout (sd);
451 }
452
453 static void
454 do_trace_output_finish (SIM_DESC sd)
455 {
456 sim_io_printf (sd,
457 " F0=%d F1=%d C=%d\n",
458 (State.trace.psw & PSR_F_BIT) != 0,
459 (State.trace.psw & PSR_F_BIT) != 0,
460 (State.trace.psw & PSR_C_BIT) != 0);
461 sim_io_flush_stdout (sd);
462 }
463
464 #if 0
465 static void
466 trace_output_40 (SIM_DESC sd, uint64_t val)
467 {
468 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
469 {
470 sim_io_printf (sd,
471 " :: %*s0x%.2x%.8lx",
472 SIZE_VALUES - 12,
473 "",
474 ((int)(val >> 32) & 0xff),
475 ((unsigned long) val) & 0xffffffff);
476 do_trace_output_finish ();
477 }
478 }
479 #endif
480
481 static void
482 trace_output_32 (SIM_DESC sd, uint32_t val)
483 {
484 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
485 {
486 sim_io_printf (sd,
487 " :: %*s0x%.8x",
488 SIZE_VALUES - 10,
489 "",
490 (int) val);
491 do_trace_output_finish (sd);
492 }
493 }
494
495 static void
496 trace_output_16 (SIM_DESC sd, uint16_t val)
497 {
498 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
499 {
500 sim_io_printf (sd,
501 " :: %*s0x%.4x",
502 SIZE_VALUES - 6,
503 "",
504 (int) val);
505 do_trace_output_finish (sd);
506 }
507 }
508
509 static void
510 trace_output_void (SIM_DESC sd)
511 {
512 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
513 {
514 sim_io_printf (sd, "\n");
515 do_trace_output_flush (sd);
516 }
517 }
518
519 static void
520 trace_output_flag (SIM_DESC sd)
521 {
522 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
523 {
524 sim_io_printf (sd,
525 " :: %*s",
526 SIZE_VALUES,
527 "");
528 do_trace_output_finish (sd);
529 }
530 }
531
532
533
534
535 #else
536 #define trace_input(NAME, IN1, IN2, IN3)
537 #define trace_output(RESULT)
538 #endif
539
540 /* addub. */
541 void
542 OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
543 {
544 uint8_t tmp;
545 uint8_t a = OP[0] & 0xff;
546 uint16_t b = (GPR (OP[1])) & 0xff;
547 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
548 tmp = (a + b) & 0xff;
549 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
550 trace_output_16 (sd, tmp);
551 }
552
553 /* addub. */
554 void
555 OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
556 {
557 uint16_t tmp;
558 uint8_t a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
559 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
560 tmp = (a + b) & 0xff;
561 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
562 trace_output_16 (sd, tmp);
563 }
564
565 /* addub. */
566 void
567 OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
568 {
569 uint8_t a = (GPR (OP[0])) & 0xff;
570 uint8_t b = (GPR (OP[1])) & 0xff;
571 uint16_t tmp = (a + b) & 0xff;
572 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
573 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
574 trace_output_16 (sd, tmp);
575 }
576
577 /* adduw. */
578 void
579 OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
580 {
581 uint16_t a = OP[0];
582 uint16_t b = GPR (OP[1]);
583 uint16_t tmp = (a + b);
584 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
585 SET_GPR (OP[1], tmp);
586 trace_output_16 (sd, tmp);
587 }
588
589 /* adduw. */
590 void
591 OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
592 {
593 uint16_t a = OP[0];
594 uint16_t b = GPR (OP[1]);
595 uint16_t tmp = (a + b);
596 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
597 SET_GPR (OP[1], tmp);
598 trace_output_16 (sd, tmp);
599 }
600
601 /* adduw. */
602 void
603 OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
604 {
605 uint16_t a = GPR (OP[0]);
606 uint16_t b = GPR (OP[1]);
607 uint16_t tmp = (a + b);
608 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
609 SET_GPR (OP[1], tmp);
610 trace_output_16 (sd, tmp);
611 }
612
613 /* addb. */
614 void
615 OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
616 {
617 uint8_t a = OP[0];
618 uint8_t b = (GPR (OP[1]) & 0xff);
619 uint16_t tmp = (a + b) & 0xff;
620 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
621 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
622 SET_PSR_C (tmp > 0xFF);
623 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
624 trace_output_16 (sd, tmp);
625 }
626
627 /* addb. */
628 void
629 OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
630 {
631 uint8_t a = (OP[0]) & 0xff;
632 uint8_t b = (GPR (OP[1]) & 0xff);
633 uint16_t tmp = (a + b) & 0xff;
634 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
635 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
636 SET_PSR_C (tmp > 0xFF);
637 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
638 trace_output_16 (sd, tmp);
639 }
640
641 /* addb. */
642 void
643 OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
644 {
645 uint8_t a = (GPR (OP[0]) & 0xff);
646 uint8_t b = (GPR (OP[1]) & 0xff);
647 uint16_t tmp = (a + b) & 0xff;
648 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
649 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
650 SET_PSR_C (tmp > 0xFF);
651 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
652 trace_output_16 (sd, tmp);
653 }
654
655 /* addw. */
656 void
657 OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
658 {
659 int16_t a = OP[0];
660 uint16_t tmp, b = GPR (OP[1]);
661 tmp = (a + b);
662 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
663 SET_GPR (OP[1], tmp);
664 SET_PSR_C (tmp > 0xFFFF);
665 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
666 trace_output_16 (sd, tmp);
667 }
668
669 /* addw. */
670 void
671 OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
672 {
673 int16_t a = OP[0];
674 uint16_t tmp, b = GPR (OP[1]);
675 tmp = (a + b);
676 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
677 SET_GPR (OP[1], tmp);
678 SET_PSR_C (tmp > 0xFFFF);
679 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
680 trace_output_16 (sd, tmp);
681 }
682
683 /* addw. */
684 void
685 OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
686 {
687 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
688 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
689 tmp = (a + b);
690 SET_GPR (OP[1], tmp);
691 SET_PSR_C (tmp > 0xFFFF);
692 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
693 trace_output_16 (sd, tmp);
694 }
695
696 /* addcb. */
697 void
698 OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
699 {
700 uint8_t tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
701 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
702 tmp = (a + b + PSR_C) & 0xff;
703 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
704 SET_PSR_C (tmp > 0xFF);
705 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
706 trace_output_16 (sd, tmp);
707 }
708
709 /* addcb. */
710 void
711 OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
712 {
713 int8_t a = OP[0] & 0xff;
714 uint8_t b = (GPR (OP[1])) & 0xff;
715 uint8_t tmp = (a + b + PSR_C) & 0xff;
716 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
717 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
718 SET_PSR_C (tmp > 0xFF);
719 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
720 trace_output_16 (sd, tmp);
721 }
722
723 /* addcb. */
724 void
725 OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
726 {
727 uint8_t a = (GPR (OP[0])) & 0xff;
728 uint8_t b = (GPR (OP[1])) & 0xff;
729 uint8_t tmp = (a + b + PSR_C) & 0xff;
730 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
731 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
732 SET_PSR_C (tmp > 0xFF);
733 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
734 trace_output_16 (sd, tmp);
735 }
736
737 /* addcw. */
738 void
739 OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
740 {
741 uint16_t a = OP[0];
742 uint16_t b = GPR (OP[1]);
743 uint16_t tmp = (a + b + PSR_C);
744 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
745 SET_GPR (OP[1], tmp);
746 SET_PSR_C (tmp > 0xFFFF);
747 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
748 trace_output_16 (sd, tmp);
749 }
750
751 /* addcw. */
752 void
753 OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
754 {
755 int16_t a = OP[0];
756 uint16_t b = GPR (OP[1]);
757 uint16_t tmp = (a + b + PSR_C);
758 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
759 SET_GPR (OP[1], tmp);
760 SET_PSR_C (tmp > 0xFFFF);
761 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
762 trace_output_16 (sd, tmp);
763 }
764
765 /* addcw. */
766 void
767 OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
768 {
769 uint16_t a = GPR (OP[1]);
770 uint16_t b = GPR (OP[1]);
771 uint16_t tmp = (a + b + PSR_C);
772 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
773 SET_GPR (OP[1], tmp);
774 SET_PSR_C (tmp > 0xFFFF);
775 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
776 trace_output_16 (sd, tmp);
777 }
778
779 /* addd. */
780 void
781 OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
782 {
783 int16_t a = (OP[0]);
784 uint32_t b = GPR32 (OP[1]);
785 uint32_t tmp = (a + b);
786 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
787 SET_GPR32 (OP[1], tmp);
788 SET_PSR_C (tmp > 0xFFFFFFFF);
789 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
790 trace_output_32 (sd, tmp);
791 }
792
793 /* addd. */
794 void
795 OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
796 {
797 int32_t a = (SEXT16(OP[0]));
798 uint32_t b = GPR32 (OP[1]);
799 uint32_t tmp = (a + b);
800 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
801 SET_GPR32 (OP[1], tmp);
802 SET_PSR_C (tmp > 0xFFFFFFFF);
803 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
804 trace_output_32 (sd, tmp);
805 }
806
807 /* addd. */
808 void
809 OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
810 {
811 uint32_t a = GPR32 (OP[0]);
812 uint32_t b = GPR32 (OP[1]);
813 uint32_t tmp = (a + b);
814 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
815 SET_GPR32 (OP[1], tmp);
816 trace_output_32 (sd, tmp);
817 SET_PSR_C (tmp > 0xFFFFFFFF);
818 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
819 }
820
821 /* addd. */
822 void
823 OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
824 {
825 uint32_t a = OP[0];
826 uint32_t b = GPR32 (OP[1]);
827 uint32_t tmp;
828 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
829 tmp = (a + b);
830 SET_GPR32 (OP[1], tmp);
831 SET_PSR_C (tmp > 0xFFFFFFFF);
832 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
833 trace_output_32 (sd, tmp);
834 }
835
836 /* addd. */
837 void
838 OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
839 {
840 int32_t a = OP[0];
841 uint32_t b = GPR32 (OP[1]);
842 uint32_t tmp;
843 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
844 tmp = (a + b);
845 SET_GPR32 (OP[1], tmp);
846 SET_PSR_C (tmp > 0xFFFFFFFF);
847 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
848 trace_output_32 (sd, tmp);
849 }
850
851 /* andb. */
852 void
853 OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
854 {
855 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
856 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
857 tmp = a & b;
858 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
859 trace_output_16 (sd, tmp);
860 }
861
862 /* andb. */
863 void
864 OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
865 {
866 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
867 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
868 tmp = a & b;
869 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
870 trace_output_16 (sd, tmp);
871 }
872
873 /* andb. */
874 void
875 OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
876 {
877 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
878 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
879 tmp = a & b;
880 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
881 trace_output_16 (sd, tmp);
882 }
883
884 /* andw. */
885 void
886 OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
887 {
888 uint16_t tmp, a = OP[0], b = GPR (OP[1]);
889 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
890 tmp = a & b;
891 SET_GPR (OP[1], tmp);
892 trace_output_16 (sd, tmp);
893 }
894
895 /* andw. */
896 void
897 OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
898 {
899 uint16_t tmp, a = OP[0], b = GPR (OP[1]);
900 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
901 tmp = a & b;
902 SET_GPR (OP[1], tmp);
903 trace_output_16 (sd, tmp);
904 }
905
906 /* andw. */
907 void
908 OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
909 {
910 uint16_t tmp, a = GPR (OP[0]), b = GPR (OP[1]);
911 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
912 tmp = a & b;
913 SET_GPR (OP[1], tmp);
914 trace_output_16 (sd, tmp);
915 }
916
917 /* andd. */
918 void
919 OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
920 {
921 uint32_t tmp, a = OP[0], b = GPR32 (OP[1]);
922 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
923 tmp = a & b;
924 SET_GPR32 (OP[1], tmp);
925 trace_output_32 (sd, tmp);
926 }
927
928 /* andd. */
929 void
930 OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
931 {
932 uint32_t tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
933 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
934 tmp = a & b;
935 SET_GPR32 (OP[1], tmp);
936 trace_output_32 (sd, tmp);
937 }
938
939 /* ord. */
940 void
941 OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
942 {
943 uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
944 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
945 tmp = a | b;
946 SET_GPR32 (OP[1], tmp);
947 trace_output_32 (sd, tmp);
948 }
949
950 /* ord. */
951 void
952 OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
953 {
954 uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
955 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
956 tmp = a | b;
957 SET_GPR32 (OP[1], tmp);
958 trace_output_32 (sd, tmp);
959 }
960
961 /* xord. */
962 void
963 OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
964 {
965 uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
966 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
967 tmp = a ^ b;
968 SET_GPR32 (OP[1], tmp);
969 trace_output_32 (sd, tmp);
970 }
971
972 /* xord. */
973 void
974 OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
975 {
976 uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
977 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
978 tmp = a ^ b;
979 SET_GPR32 (OP[1], tmp);
980 trace_output_32 (sd, tmp);
981 }
982
983
984 /* b. */
985 void
986 OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
987 {
988 uint32_t tmp = 0, cc = cond_stat (OP[0]);
989 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
990 if (cc)
991 {
992 if (sign_flag)
993 tmp = (PC - (OP[1]));
994 else
995 tmp = (PC + (OP[1]));
996 /* If the resulting PC value is less than 0x00_0000 or greater
997 than 0xFF_FFFF, this instruction causes an IAD trap.*/
998
999 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1000 {
1001 trace_output_void (sd);
1002 EXCEPTION (SIM_SIGBUS);
1003 }
1004 else
1005 JMP (tmp);
1006 }
1007 sign_flag = 0; /* Reset sign_flag. */
1008 trace_output_32 (sd, tmp);
1009 }
1010
1011 /* b. */
1012 void
1013 OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
1014 {
1015 uint32_t tmp = 0, cc = cond_stat (OP[0]);
1016 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1017 if (cc)
1018 {
1019 if (sign_flag)
1020 tmp = (PC - OP[1]);
1021 else
1022 tmp = (PC + OP[1]);
1023 /* If the resulting PC value is less than 0x00_0000 or greater
1024 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1025
1026 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1027 {
1028 trace_output_void (sd);
1029 EXCEPTION (SIM_SIGBUS);
1030 }
1031 else
1032 JMP (tmp);
1033 }
1034 sign_flag = 0; /* Reset sign_flag. */
1035 trace_output_32 (sd, tmp);
1036 }
1037
1038 /* b. */
1039 void
1040 OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
1041 {
1042 uint32_t tmp = 0, cc = cond_stat (OP[0]);
1043 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1044 if (cc)
1045 {
1046 if (sign_flag)
1047 tmp = (PC - (OP[1]));
1048 else
1049 tmp = (PC + (OP[1]));
1050 /* If the resulting PC value is less than 0x00_0000 or greater
1051 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1052
1053 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1054 {
1055 trace_output_void (sd);
1056 EXCEPTION (SIM_SIGBUS);
1057 }
1058 else
1059 JMP (tmp);
1060 }
1061 sign_flag = 0; /* Reset sign_flag. */
1062 trace_output_32 (sd, tmp);
1063 }
1064
1065 /* bal. */
1066 void
1067 OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
1068 {
1069 uint32_t tmp;
1070 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1071 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1072 SET_GPR32 (14, tmp);
1073 if (sign_flag)
1074 tmp = (PC - (OP[1]));
1075 else
1076 tmp = (PC + (OP[1]));
1077
1078 /* If the resulting PC value is less than 0x00_0000 or greater
1079 than 0xFF_FFFF, this instruction causes an IAD trap. */
1080
1081 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1082 {
1083 trace_output_void (sd);
1084 EXCEPTION (SIM_SIGBUS);
1085 }
1086 else
1087 JMP (tmp);
1088 sign_flag = 0; /* Reset sign_flag. */
1089 trace_output_32 (sd, tmp);
1090 }
1091
1092
1093 /* bal. */
1094 void
1095 OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
1096 {
1097 uint32_t tmp;
1098 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1099 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1100 SET_GPR32 (OP[0], tmp);
1101 if (sign_flag)
1102 tmp = ((PC) - (OP[1]));
1103 else
1104 tmp = ((PC) + (OP[1]));
1105 /* If the resulting PC value is less than 0x00_0000 or greater
1106 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1107
1108 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1109 {
1110 trace_output_void (sd);
1111 EXCEPTION (SIM_SIGBUS);
1112 }
1113 else
1114 JMP (tmp);
1115 sign_flag = 0; /* Reset sign_flag. */
1116 trace_output_32 (sd, tmp);
1117 }
1118
1119 /* jal. */
1120 void
1121 OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
1122 {
1123 uint32_t tmp;
1124 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1125 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1126 tmp = GPR32 (OP[1]);
1127 tmp = SEXT24(tmp << 1);
1128 /* If the resulting PC value is less than 0x00_0000 or greater
1129 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1130
1131 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1132 {
1133 trace_output_void (sd);
1134 EXCEPTION (SIM_SIGBUS);
1135 }
1136 else
1137 JMP (tmp);
1138
1139 trace_output_32 (sd, tmp);
1140 }
1141
1142
1143 /* jal. */
1144 void
1145 OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
1146 {
1147 uint32_t tmp;
1148 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1149 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1150 tmp = GPR32 (OP[0]);
1151 tmp = SEXT24(tmp << 1);
1152 /* If the resulting PC value is less than 0x00_0000 or greater
1153 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1154
1155 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1156 {
1157 trace_output_void (sd);
1158 EXCEPTION (SIM_SIGBUS);
1159 }
1160 else
1161 JMP (tmp);
1162
1163 trace_output_32 (sd, tmp);
1164 }
1165
1166
1167 /* beq0b. */
1168 void
1169 OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
1170 {
1171 uint32_t addr;
1172 uint8_t a = (GPR (OP[0]) & 0xFF);
1173 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1174 addr = OP[1];
1175 if (a == 0)
1176 {
1177 if (sign_flag)
1178 addr = (PC - OP[1]);
1179 else
1180 addr = (PC + OP[1]);
1181
1182 JMP (addr);
1183 }
1184 sign_flag = 0; /* Reset sign_flag. */
1185 trace_output_void (sd);
1186 }
1187
1188 /* bne0b. */
1189 void
1190 OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
1191 {
1192 uint32_t addr;
1193 uint8_t a = (GPR (OP[0]) & 0xFF);
1194 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1195 addr = OP[1];
1196 if (a != 0)
1197 {
1198 if (sign_flag)
1199 addr = (PC - OP[1]);
1200 else
1201 addr = (PC + OP[1]);
1202
1203 JMP (addr);
1204 }
1205 sign_flag = 0; /* Reset sign_flag. */
1206 trace_output_void (sd);
1207 }
1208
1209 /* beq0w. */
1210 void
1211 OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
1212 {
1213 uint32_t addr;
1214 uint16_t a = GPR (OP[0]);
1215 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1216 addr = OP[1];
1217 if (a == 0)
1218 {
1219 if (sign_flag)
1220 addr = (PC - OP[1]);
1221 else
1222 addr = (PC + OP[1]);
1223
1224 JMP (addr);
1225 }
1226 sign_flag = 0; /* Reset sign_flag. */
1227 trace_output_void (sd);
1228 }
1229
1230 /* bne0w. */
1231 void
1232 OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
1233 {
1234 uint32_t addr;
1235 uint16_t a = GPR (OP[0]);
1236 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1237 addr = OP[1];
1238 if (a != 0)
1239 {
1240 if (sign_flag)
1241 addr = (PC - OP[1]);
1242 else
1243 addr = (PC + OP[1]);
1244
1245 JMP (addr);
1246 }
1247 sign_flag = 0; /* Reset sign_flag. */
1248 trace_output_void (sd);
1249 }
1250
1251
1252 /* jeq. */
1253 void
1254 OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
1255 {
1256 uint32_t tmp = 0;
1257 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1258 if ((PSR_Z) == 1)
1259 {
1260 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1261 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1262 }
1263 trace_output_32 (sd, tmp);
1264 }
1265
1266 /* jne. */
1267 void
1268 OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
1269 {
1270 uint32_t tmp = 0;
1271 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1272 if ((PSR_Z) == 0)
1273 {
1274 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1275 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1276 }
1277 trace_output_32 (sd, tmp);
1278 }
1279
1280 /* jcs. */
1281 void
1282 OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
1283 {
1284 uint32_t tmp = 0;
1285 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1286 if ((PSR_C) == 1)
1287 {
1288 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1289 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1290 }
1291 trace_output_32 (sd, tmp);
1292 }
1293
1294 /* jcc. */
1295 void
1296 OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
1297 {
1298 uint32_t tmp = 0;
1299 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1300 if ((PSR_C) == 0)
1301 {
1302 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1303 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1304 }
1305 trace_output_32 (sd, tmp);
1306 }
1307
1308 /* jhi. */
1309 void
1310 OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
1311 {
1312 uint32_t tmp = 0;
1313 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1314 if ((PSR_L) == 1)
1315 {
1316 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1317 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1318 }
1319 trace_output_32 (sd, tmp);
1320 }
1321
1322 /* jls. */
1323 void
1324 OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
1325 {
1326 uint32_t tmp = 0;
1327 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1328 if ((PSR_L) == 0)
1329 {
1330 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1331 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1332 }
1333 trace_output_32 (sd, tmp);
1334 }
1335
1336 /* jgt. */
1337 void
1338 OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
1339 {
1340 uint32_t tmp = 0;
1341 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1342 if ((PSR_N) == 1)
1343 {
1344 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1345 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1346 }
1347 trace_output_32 (sd, tmp);
1348 }
1349
1350 /* jle. */
1351 void
1352 OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
1353 {
1354 uint32_t tmp = 0;
1355 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1356 if ((PSR_N) == 0)
1357 {
1358 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1359 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1360 }
1361 trace_output_32 (sd, tmp);
1362 }
1363
1364
1365 /* jfs. */
1366 void
1367 OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
1368 {
1369 uint32_t tmp = 0;
1370 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1371 if ((PSR_F) == 1)
1372 {
1373 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1374 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1375 }
1376 trace_output_32 (sd, tmp);
1377 }
1378
1379 /* jfc. */
1380 void
1381 OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
1382 {
1383 uint32_t tmp = 0;
1384 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1385 if ((PSR_F) == 0)
1386 {
1387 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1388 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1389 }
1390 trace_output_32 (sd, tmp);
1391 }
1392
1393 /* jlo. */
1394 void
1395 OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
1396 {
1397 uint32_t tmp = 0;
1398 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1399 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1400 {
1401 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1402 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1403 }
1404 trace_output_32 (sd, tmp);
1405 }
1406
1407 /* jhs. */
1408 void
1409 OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
1410 {
1411 uint32_t tmp = 0;
1412 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1413 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1414 {
1415 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1416 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1417 }
1418 trace_output_32 (sd, tmp);
1419 }
1420
1421 /* jlt. */
1422 void
1423 OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
1424 {
1425 uint32_t tmp = 0;
1426 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1427 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1428 {
1429 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1430 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1431 }
1432 trace_output_32 (sd, tmp);
1433 }
1434
1435 /* jge. */
1436 void
1437 OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
1438 {
1439 uint32_t tmp = 0;
1440 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1441 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1442 {
1443 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1444 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1445 }
1446 trace_output_32 (sd, tmp);
1447 }
1448
1449 /* jump. */
1450 void
1451 OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
1452 {
1453 uint32_t tmp;
1454 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1455 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1456 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1457 trace_output_32 (sd, tmp);
1458 }
1459
1460 /* jusr. */
1461 void
1462 OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
1463 {
1464 uint32_t tmp;
1465 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1466 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1467 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1468 SET_PSR_U(1);
1469 trace_output_32 (sd, tmp);
1470 }
1471
1472 /* seq. */
1473 void
1474 OP_80_C (SIM_DESC sd, SIM_CPU *cpu)
1475 {
1476 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1477 if ((PSR_Z) == 1)
1478 SET_GPR (OP[0], 1);
1479 else
1480 SET_GPR (OP[0], 0);
1481 trace_output_void (sd);
1482 }
1483 /* sne. */
1484 void
1485 OP_81_C (SIM_DESC sd, SIM_CPU *cpu)
1486 {
1487 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1488 if ((PSR_Z) == 0)
1489 SET_GPR (OP[0], 1);
1490 else
1491 SET_GPR (OP[0], 0);
1492 trace_output_void (sd);
1493 }
1494
1495 /* scs. */
1496 void
1497 OP_82_C (SIM_DESC sd, SIM_CPU *cpu)
1498 {
1499 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1500 if ((PSR_C) == 1)
1501 SET_GPR (OP[0], 1);
1502 else
1503 SET_GPR (OP[0], 0);
1504 trace_output_void (sd);
1505 }
1506
1507 /* scc. */
1508 void
1509 OP_83_C (SIM_DESC sd, SIM_CPU *cpu)
1510 {
1511 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1512 if ((PSR_C) == 0)
1513 SET_GPR (OP[0], 1);
1514 else
1515 SET_GPR (OP[0], 0);
1516 trace_output_void (sd);
1517 }
1518
1519 /* shi. */
1520 void
1521 OP_84_C (SIM_DESC sd, SIM_CPU *cpu)
1522 {
1523 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1524 if ((PSR_L) == 1)
1525 SET_GPR (OP[0], 1);
1526 else
1527 SET_GPR (OP[0], 0);
1528 trace_output_void (sd);
1529 }
1530
1531 /* sls. */
1532 void
1533 OP_85_C (SIM_DESC sd, SIM_CPU *cpu)
1534 {
1535 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1536 if ((PSR_L) == 0)
1537 SET_GPR (OP[0], 1);
1538 else
1539 SET_GPR (OP[0], 0);
1540 trace_output_void (sd);
1541 }
1542
1543 /* sgt. */
1544 void
1545 OP_86_C (SIM_DESC sd, SIM_CPU *cpu)
1546 {
1547 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1548 if ((PSR_N) == 1)
1549 SET_GPR (OP[0], 1);
1550 else
1551 SET_GPR (OP[0], 0);
1552 trace_output_void (sd);
1553 }
1554
1555 /* sle. */
1556 void
1557 OP_87_C (SIM_DESC sd, SIM_CPU *cpu)
1558 {
1559 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1560 if ((PSR_N) == 0)
1561 SET_GPR (OP[0], 1);
1562 else
1563 SET_GPR (OP[0], 0);
1564 trace_output_void (sd);
1565 }
1566
1567 /* sfs. */
1568 void
1569 OP_88_C (SIM_DESC sd, SIM_CPU *cpu)
1570 {
1571 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1572 if ((PSR_F) == 1)
1573 SET_GPR (OP[0], 1);
1574 else
1575 SET_GPR (OP[0], 0);
1576 trace_output_void (sd);
1577 }
1578
1579 /* sfc. */
1580 void
1581 OP_89_C (SIM_DESC sd, SIM_CPU *cpu)
1582 {
1583 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1584 if ((PSR_F) == 0)
1585 SET_GPR (OP[0], 1);
1586 else
1587 SET_GPR (OP[0], 0);
1588 trace_output_void (sd);
1589 }
1590
1591
1592 /* slo. */
1593 void
1594 OP_8A_C (SIM_DESC sd, SIM_CPU *cpu)
1595 {
1596 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1597 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1598 SET_GPR (OP[0], 1);
1599 else
1600 SET_GPR (OP[0], 0);
1601 trace_output_void (sd);
1602 }
1603
1604 /* shs. */
1605 void
1606 OP_8B_C (SIM_DESC sd, SIM_CPU *cpu)
1607 {
1608 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1609 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1610 SET_GPR (OP[0], 1);
1611 else
1612 SET_GPR (OP[0], 0);
1613 trace_output_void (sd);
1614 }
1615
1616 /* slt. */
1617 void
1618 OP_8C_C (SIM_DESC sd, SIM_CPU *cpu)
1619 {
1620 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1621 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1622 SET_GPR (OP[0], 1);
1623 else
1624 SET_GPR (OP[0], 0);
1625 trace_output_void (sd);
1626 }
1627
1628 /* sge. */
1629 void
1630 OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
1631 {
1632 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1633 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1634 SET_GPR (OP[0], 1);
1635 else
1636 SET_GPR (OP[0], 0);
1637 trace_output_void (sd);
1638 }
1639
1640 /* cbitb. */
1641 void
1642 OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
1643 {
1644 uint8_t a = OP[0] & 0xff;
1645 uint32_t addr = OP[1], tmp;
1646 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1647 tmp = RB (addr);
1648 SET_PSR_F (tmp & (1 << a));
1649 tmp = tmp & ~(1 << a);
1650 SB (addr, tmp);
1651 trace_output_32 (sd, tmp);
1652 }
1653
1654 /* cbitb. */
1655 void
1656 OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
1657 {
1658 uint8_t a = OP[0] & 0xff;
1659 uint32_t addr = OP[1], tmp;
1660 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1661 tmp = RB (addr);
1662 SET_PSR_F (tmp & (1 << a));
1663 tmp = tmp & ~(1 << a);
1664 SB (addr, tmp);
1665 trace_output_32 (sd, tmp);
1666 }
1667
1668 /* cbitb. */
1669 void
1670 OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
1671 {
1672 uint8_t a = (OP[0]) & 0xff;
1673 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
1674 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1675 tmp = RB (addr);
1676 SET_PSR_F (tmp & (1 << a));
1677 tmp = tmp & ~(1 << a);
1678 SB (addr, tmp);
1679 trace_output_32 (sd, addr);
1680 }
1681
1682 /* cbitb. */
1683 void
1684 OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
1685 {
1686 uint8_t a = (OP[0]) & 0xff;
1687 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1688 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1689 tmp = RB (addr);
1690 SET_PSR_F (tmp & (1 << a));
1691 tmp = tmp & ~(1 << a);
1692 SB (addr, tmp);
1693 trace_output_32 (sd, addr);
1694 }
1695
1696 /* cbitb. */
1697 void
1698 OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
1699 {
1700 uint8_t a = (OP[0]) & 0xff;
1701 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
1702 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1703 tmp = RB (addr);
1704 SET_PSR_F (tmp & (1 << a));
1705 tmp = tmp & ~(1 << a);
1706 SB (addr, tmp);
1707 trace_output_32 (sd, addr);
1708 }
1709
1710 /* cbitb. */
1711 void
1712 OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
1713 {
1714 uint8_t a = (OP[0]) & 0xff;
1715 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1716 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1717 tmp = RB (addr);
1718 SET_PSR_F (tmp & (1 << a));
1719 tmp = tmp & ~(1 << a);
1720 SB (addr, tmp);
1721 trace_output_32 (sd, addr);
1722 }
1723
1724 /* cbitb. */
1725 void
1726 OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
1727 {
1728 uint8_t a = (OP[0]) & 0xff;
1729 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1730 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1731 tmp = RB (addr);
1732 SET_PSR_F (tmp & (1 << a));
1733 tmp = tmp & ~(1 << a);
1734 SB (addr, tmp);
1735 trace_output_32 (sd, addr);
1736
1737 }
1738
1739 /* cbitb. */
1740 void
1741 OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
1742 {
1743 uint8_t a = (OP[0]) & 0xff;
1744 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1745 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1746 tmp = RB (addr);
1747 SET_PSR_F (tmp & (1 << a));
1748 tmp = tmp & ~(1 << a);
1749 SB (addr, tmp);
1750 trace_output_32 (sd, addr);
1751 }
1752
1753 /* cbitb. */
1754 void
1755 OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
1756 {
1757 uint8_t a = (OP[0]) & 0xff;
1758 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1759 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1760 tmp = RB (addr);
1761 SET_PSR_F (tmp & (1 << a));
1762 tmp = tmp & ~(1 << a);
1763 SB (addr, tmp);
1764 trace_output_32 (sd, addr);
1765 }
1766
1767
1768 /* cbitw. */
1769 void
1770 OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
1771 {
1772 uint16_t a = OP[0];
1773 uint32_t addr = OP[1], tmp;
1774 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1775 tmp = RW (addr);
1776 SET_PSR_F (tmp & (1 << a));
1777 tmp = tmp & ~(1 << a);
1778 SW (addr, tmp);
1779 trace_output_32 (sd, tmp);
1780 }
1781
1782 /* cbitw. */
1783 void
1784 OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
1785 {
1786 uint16_t a = OP[0];
1787 uint32_t addr = OP[1], tmp;
1788 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1789 tmp = RW (addr);
1790 SET_PSR_F (tmp & (1 << a));
1791 tmp = tmp & ~(1 << a);
1792 SW (addr, tmp);
1793 trace_output_32 (sd, tmp);
1794 }
1795
1796 /* cbitw. */
1797 void
1798 OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
1799 {
1800 uint32_t addr;
1801 uint16_t a = (OP[0]), tmp;
1802 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1803
1804 if (OP[1] == 0)
1805 addr = (GPR32 (12)) + OP[2];
1806 else
1807 addr = (GPR32 (13)) + OP[2];
1808
1809 tmp = RW (addr);
1810 SET_PSR_F (tmp & (1 << a));
1811 tmp = tmp & ~(1 << a);
1812 SW (addr, tmp);
1813 trace_output_32 (sd, addr);
1814
1815 }
1816
1817 /* cbitw. */
1818 void
1819 OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
1820 {
1821 uint16_t a = (OP[0]);
1822 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1823 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1824 tmp = RW (addr);
1825 SET_PSR_F (tmp & (1 << a));
1826 tmp = tmp & ~(1 << a);
1827 SW (addr, tmp);
1828 trace_output_32 (sd, addr);
1829 }
1830
1831 /* cbitw. */
1832 void
1833 OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
1834 {
1835 uint16_t a = (OP[0]);
1836 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
1837 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1838 tmp = RW (addr);
1839 SET_PSR_F (tmp & (1 << a));
1840 tmp = tmp & ~(1 << a);
1841 SW (addr, tmp);
1842 trace_output_32 (sd, addr);
1843 }
1844
1845
1846 /* cbitw. */
1847 void
1848 OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
1849 {
1850 uint16_t a = (OP[0]);
1851 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1852 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1853 tmp = RW (addr);
1854 SET_PSR_F (tmp & (1 << a));
1855 tmp = tmp & ~(1 << a);
1856 SW (addr, tmp);
1857 trace_output_32 (sd, addr);
1858 }
1859
1860 /* cbitw. */
1861 void
1862 OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
1863 {
1864 uint16_t a = (OP[0]);
1865 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1866 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1867 tmp = RW (addr);
1868 SET_PSR_F (tmp & (1 << a));
1869 tmp = tmp & ~(1 << a);
1870 SW (addr, tmp);
1871 trace_output_32 (sd, addr);
1872 }
1873
1874
1875 /* cbitw. */
1876 void
1877 OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
1878 {
1879 uint16_t a = (OP[0]);
1880 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1881 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1882 tmp = RW (addr);
1883 SET_PSR_F (tmp & (1 << a));
1884 tmp = tmp & ~(1 << a);
1885 SW (addr, tmp);
1886 trace_output_32 (sd, addr);
1887 }
1888
1889 /* cbitw. */
1890 void
1891 OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
1892 {
1893 uint16_t a = (OP[0]);
1894 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1895 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1896 tmp = RW (addr);
1897 SET_PSR_F (tmp & (1 << a));
1898 tmp = tmp & ~(1 << a);
1899 SW (addr, tmp);
1900 trace_output_32 (sd, addr);
1901 }
1902
1903 /* sbitb. */
1904 void
1905 OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
1906 {
1907 uint8_t a = OP[0] & 0xff;
1908 uint32_t addr = OP[1], tmp;
1909 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1910 tmp = RB (addr);
1911 SET_PSR_F (tmp & (1 << a));
1912 tmp = tmp | (1 << a);
1913 SB (addr, tmp);
1914 trace_output_32 (sd, tmp);
1915 }
1916
1917 /* sbitb. */
1918 void
1919 OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
1920 {
1921 uint8_t a = OP[0] & 0xff;
1922 uint32_t addr = OP[1], tmp;
1923 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1924 tmp = RB (addr);
1925 SET_PSR_F (tmp & (1 << a));
1926 tmp = tmp | (1 << a);
1927 SB (addr, tmp);
1928 trace_output_32 (sd, tmp);
1929 }
1930
1931 /* sbitb. */
1932 void
1933 OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
1934 {
1935 uint8_t a = OP[0] & 0xff;
1936 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
1937 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1938 tmp = RB (addr);
1939 SET_PSR_F (tmp & (1 << a));
1940 tmp = tmp | (1 << a);
1941 SB (addr, tmp);
1942 trace_output_32 (sd, tmp);
1943 }
1944
1945 /* sbitb. */
1946 void
1947 OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
1948 {
1949 uint8_t a = OP[0] & 0xff;
1950 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1951 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1952 tmp = RB (addr);
1953 SET_PSR_F (tmp & (1 << a));
1954 tmp = tmp | (1 << a);
1955 SB (addr, tmp);
1956 trace_output_32 (sd, tmp);
1957 }
1958
1959 /* sbitb. */
1960 void
1961 OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
1962 {
1963 uint8_t a = OP[0] & 0xff;
1964 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
1965 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1966 tmp = RB (addr);
1967 SET_PSR_F (tmp & (1 << a));
1968 tmp = tmp | (1 << a);
1969 SB (addr, tmp);
1970 trace_output_32 (sd, tmp);
1971 }
1972
1973
1974 /* sbitb. */
1975 void
1976 OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
1977 {
1978 uint8_t a = OP[0] & 0xff;
1979 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1980 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1981 tmp = RB (addr);
1982 SET_PSR_F (tmp & (1 << a));
1983 tmp = tmp | (1 << a);
1984 SB (addr, tmp);
1985 trace_output_32 (sd, tmp);
1986 }
1987
1988 /* sbitb. */
1989 void
1990 OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
1991 {
1992 uint8_t a = OP[0] & 0xff;
1993 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1994 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1995 tmp = RB (addr);
1996 SET_PSR_F (tmp & (1 << a));
1997 tmp = tmp | (1 << a);
1998 SB (addr, tmp);
1999 trace_output_32 (sd, tmp);
2000 }
2001
2002
2003 /* sbitb. */
2004 void
2005 OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
2006 {
2007 uint8_t a = OP[0] & 0xff;
2008 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2009 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2010 tmp = RB (addr);
2011 SET_PSR_F (tmp & (1 << a));
2012 tmp = tmp | (1 << a);
2013 SB (addr, tmp);
2014 trace_output_32 (sd, tmp);
2015 }
2016
2017
2018 /* sbitb. */
2019 void
2020 OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
2021 {
2022 uint8_t a = OP[0] & 0xff;
2023 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2024 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2025 tmp = RB (addr);
2026 SET_PSR_F (tmp & (1 << a));
2027 tmp = tmp | (1 << a);
2028 SB (addr, tmp);
2029 trace_output_32 (sd, tmp);
2030 }
2031
2032
2033 /* sbitw. */
2034 void
2035 OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
2036 {
2037 uint16_t a = OP[0];
2038 uint32_t addr = OP[1], tmp;
2039 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2040 tmp = RW (addr);
2041 SET_PSR_F (tmp & (1 << a));
2042 tmp = tmp | (1 << a);
2043 SW (addr, tmp);
2044 trace_output_32 (sd, tmp);
2045 }
2046
2047 /* sbitw. */
2048 void
2049 OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
2050 {
2051 uint16_t a = OP[0];
2052 uint32_t addr = OP[1], tmp;
2053 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2054 tmp = RW (addr);
2055 SET_PSR_F (tmp & (1 << a));
2056 tmp = tmp | (1 << a);
2057 SW (addr, tmp);
2058 trace_output_32 (sd, tmp);
2059 }
2060
2061 /* sbitw. */
2062 void
2063 OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
2064 {
2065 uint32_t addr;
2066 uint16_t a = (OP[0]), tmp;
2067 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2068
2069 if (OP[1] == 0)
2070 addr = (GPR32 (12)) + OP[2];
2071 else
2072 addr = (GPR32 (13)) + OP[2];
2073
2074 tmp = RW (addr);
2075 SET_PSR_F (tmp & (1 << a));
2076 tmp = tmp | (1 << a);
2077 SW (addr, tmp);
2078 trace_output_32 (sd, addr);
2079 }
2080
2081 /* sbitw. */
2082 void
2083 OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
2084 {
2085 uint16_t a = (OP[0]);
2086 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2087 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2088 tmp = RW (addr);
2089 SET_PSR_F (tmp & (1 << a));
2090 tmp = tmp | (1 << a);
2091 SW (addr, tmp);
2092 trace_output_32 (sd, addr);
2093 }
2094
2095 /* sbitw. */
2096 void
2097 OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
2098 {
2099 uint16_t a = (OP[0]);
2100 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
2101 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2102 tmp = RW (addr);
2103 SET_PSR_F (tmp & (1 << a));
2104 tmp = tmp | (1 << a);
2105 SW (addr, tmp);
2106 trace_output_32 (sd, addr);
2107 }
2108
2109 /* sbitw. */
2110 void
2111 OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
2112 {
2113 uint16_t a = (OP[0]);
2114 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2115 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2116 tmp = RW (addr);
2117 SET_PSR_F (tmp & (1 << a));
2118 tmp = tmp | (1 << a);
2119 SW (addr, tmp);
2120 trace_output_32 (sd, addr);
2121 }
2122
2123 /* sbitw. */
2124 void
2125 OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
2126 {
2127 uint16_t a = (OP[0]);
2128 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2129 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2130 tmp = RW (addr);
2131 SET_PSR_F (tmp & (1 << a));
2132 tmp = tmp | (1 << a);
2133 SW (addr, tmp);
2134 trace_output_32 (sd, addr);
2135 }
2136
2137 /* sbitw. */
2138 void
2139 OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
2140 {
2141 uint16_t a = (OP[0]);
2142 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2143 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2144 tmp = RW (addr);
2145 SET_PSR_F (tmp & (1 << a));
2146 tmp = tmp | (1 << a);
2147 SW (addr, tmp);
2148 trace_output_32 (sd, addr);
2149 }
2150
2151 /* sbitw. */
2152 void
2153 OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
2154 {
2155 uint16_t a = (OP[0]);
2156 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2157 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2158 tmp = RW (addr);
2159 SET_PSR_F (tmp & (1 << a));
2160 tmp = tmp | (1 << a);
2161 SW (addr, tmp);
2162 trace_output_32 (sd, addr);
2163 }
2164
2165
2166 /* tbitb. */
2167 void
2168 OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
2169 {
2170 uint8_t a = OP[0] & 0xff;
2171 uint32_t addr = OP[1], tmp;
2172 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2173 tmp = RB (addr);
2174 SET_PSR_F (tmp & (1 << a));
2175 trace_output_32 (sd, tmp);
2176 }
2177
2178 /* tbitb. */
2179 void
2180 OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
2181 {
2182 uint8_t a = OP[0] & 0xff;
2183 uint32_t addr = OP[1], tmp;
2184 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2185 tmp = RB (addr);
2186 SET_PSR_F (tmp & (1 << a));
2187 trace_output_32 (sd, tmp);
2188 }
2189
2190 /* tbitb. */
2191 void
2192 OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
2193 {
2194 uint8_t a = (OP[0]) & 0xff;
2195 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
2196 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2197 tmp = RB (addr);
2198 SET_PSR_F (tmp & (1 << a));
2199 trace_output_32 (sd, addr);
2200 }
2201
2202 /* tbitb. */
2203 void
2204 OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
2205 {
2206 uint8_t a = (OP[0]) & 0xff;
2207 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2208 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2209 tmp = RB (addr);
2210 SET_PSR_F (tmp & (1 << a));
2211 trace_output_32 (sd, addr);
2212 }
2213
2214 /* tbitb. */
2215 void
2216 OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
2217 {
2218 uint8_t a = (OP[0]) & 0xff;
2219 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
2220 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2221 tmp = RB (addr);
2222 SET_PSR_F (tmp & (1 << a));
2223 trace_output_32 (sd, addr);
2224 }
2225
2226 /* tbitb. */
2227 void
2228 OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
2229 {
2230 uint8_t a = (OP[0]) & 0xff;
2231 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2232 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2233 tmp = RB (addr);
2234 SET_PSR_F (tmp & (1 << a));
2235 trace_output_32 (sd, addr);
2236 }
2237
2238 /* tbitb. */
2239 void
2240 OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
2241 {
2242 uint8_t a = (OP[0]) & 0xff;
2243 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2244 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2245 tmp = RB (addr);
2246 SET_PSR_F (tmp & (1 << a));
2247 trace_output_32 (sd, addr);
2248 }
2249
2250 /* tbitb. */
2251 void
2252 OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
2253 {
2254 uint8_t a = (OP[0]) & 0xff;
2255 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2256 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2257 tmp = RB (addr);
2258 SET_PSR_F (tmp & (1 << a));
2259 trace_output_32 (sd, addr);
2260 }
2261
2262 /* tbitb. */
2263 void
2264 OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
2265 {
2266 uint8_t a = (OP[0]) & 0xff;
2267 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2268 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2269 tmp = RB (addr);
2270 SET_PSR_F (tmp & (1 << a));
2271 trace_output_32 (sd, addr);
2272 }
2273
2274
2275 /* tbitw. */
2276 void
2277 OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
2278 {
2279 uint16_t a = OP[0];
2280 uint32_t addr = OP[1], tmp;
2281 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2282 tmp = RW (addr);
2283 SET_PSR_F (tmp & (1 << a));
2284 trace_output_32 (sd, tmp);
2285 }
2286
2287 /* tbitw. */
2288 void
2289 OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
2290 {
2291 uint16_t a = OP[0];
2292 uint32_t addr = OP[1], tmp;
2293 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2294 tmp = RW (addr);
2295 SET_PSR_F (tmp & (1 << a));
2296 trace_output_32 (sd, tmp);
2297 }
2298
2299
2300 /* tbitw. */
2301 void
2302 OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
2303 {
2304 uint32_t addr;
2305 uint16_t a = (OP[0]), tmp;
2306 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2307
2308 if (OP[1] == 0)
2309 addr = (GPR32 (12)) + OP[2];
2310 else
2311 addr = (GPR32 (13)) + OP[2];
2312
2313 tmp = RW (addr);
2314 SET_PSR_F (tmp & (1 << a));
2315 trace_output_32 (sd, addr);
2316 }
2317
2318 /* tbitw. */
2319 void
2320 OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
2321 {
2322 uint16_t a = (OP[0]);
2323 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2324 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2325 tmp = RW (addr);
2326 SET_PSR_F (tmp & (1 << a));
2327 trace_output_32 (sd, addr);
2328 }
2329
2330 /* tbitw. */
2331 void
2332 OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
2333 {
2334 uint16_t a = (OP[0]);
2335 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
2336 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2337 tmp = RW (addr);
2338 SET_PSR_F (tmp & (1 << a));
2339 trace_output_32 (sd, addr);
2340 }
2341
2342 /* tbitw. */
2343 void
2344 OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
2345 {
2346 uint16_t a = (OP[0]);
2347 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2348 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2349 tmp = RW (addr);
2350 SET_PSR_F (tmp & (1 << a));
2351 trace_output_32 (sd, addr);
2352 }
2353
2354 /* tbitw. */
2355 void
2356 OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
2357 {
2358 uint16_t a = (OP[0]);
2359 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2360 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2361 tmp = RW (addr);
2362 SET_PSR_F (tmp & (1 << a));
2363 trace_output_32 (sd, addr);
2364 }
2365
2366 /* tbitw. */
2367 void
2368 OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
2369 {
2370 uint16_t a = (OP[0]);
2371 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2372 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2373 tmp = RW (addr);
2374 SET_PSR_F (tmp & (1 << a));
2375 trace_output_32 (sd, addr);
2376 }
2377
2378
2379 /* tbitw. */
2380 void
2381 OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
2382 {
2383 uint16_t a = (OP[0]);
2384 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2385 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2386 tmp = RW (addr);
2387 SET_PSR_F (tmp & (1 << a));
2388 trace_output_32 (sd, addr);
2389 }
2390
2391
2392 /* tbit. */
2393 void
2394 OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
2395 {
2396 uint16_t a = OP[0];
2397 uint16_t b = (GPR (OP[1]));
2398 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
2399 SET_PSR_F (b & (1 << a));
2400 trace_output_16 (sd, b);
2401 }
2402
2403 /* tbit. */
2404 void
2405 OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
2406 {
2407 uint16_t a = GPR (OP[0]);
2408 uint16_t b = (GPR (OP[1]));
2409 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
2410 SET_PSR_F (b & (1 << a));
2411 trace_output_16 (sd, b);
2412 }
2413
2414
2415 /* cmpb. */
2416 void
2417 OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
2418 {
2419 uint8_t a = (OP[0]) & 0xFF;
2420 uint8_t b = (GPR (OP[1])) & 0xFF;
2421 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2422 SET_PSR_Z (a == b);
2423 SET_PSR_N ((int8_t)a > (int8_t)b);
2424 SET_PSR_L (a > b);
2425 trace_output_flag (sd);
2426 }
2427
2428 /* cmpb. */
2429 void
2430 OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
2431 {
2432 uint8_t a = (OP[0]) & 0xFF;
2433 uint8_t b = (GPR (OP[1])) & 0xFF;
2434 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2435 SET_PSR_Z (a == b);
2436 SET_PSR_N ((int8_t)a > (int8_t)b);
2437 SET_PSR_L (a > b);
2438 trace_output_flag (sd);
2439 }
2440
2441 /* cmpb. */
2442 void
2443 OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
2444 {
2445 uint8_t a = (GPR (OP[0])) & 0xFF;
2446 uint8_t b = (GPR (OP[1])) & 0xFF;
2447 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2448 SET_PSR_Z (a == b);
2449 SET_PSR_N ((int8_t)a > (int8_t)b);
2450 SET_PSR_L (a > b);
2451 trace_output_flag (sd);
2452 }
2453
2454 /* cmpw. */
2455 void
2456 OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
2457 {
2458 uint16_t a = (OP[0]);
2459 uint16_t b = GPR (OP[1]);
2460 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2461 SET_PSR_Z (a == b);
2462 SET_PSR_N ((int16_t)a > (int16_t)b);
2463 SET_PSR_L (a > b);
2464 trace_output_flag (sd);
2465 }
2466
2467 /* cmpw. */
2468 void
2469 OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
2470 {
2471 uint16_t a = (OP[0]);
2472 uint16_t b = GPR (OP[1]);
2473 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2474 SET_PSR_Z (a == b);
2475 SET_PSR_N ((int16_t)a > (int16_t)b);
2476 SET_PSR_L (a > b);
2477 trace_output_flag (sd);
2478 }
2479
2480 /* cmpw. */
2481 void
2482 OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
2483 {
2484 uint16_t a = GPR (OP[0]) ;
2485 uint16_t b = GPR (OP[1]) ;
2486 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2487 SET_PSR_Z (a == b);
2488 SET_PSR_N ((int16_t)a > (int16_t)b);
2489 SET_PSR_L (a > b);
2490 trace_output_flag (sd);
2491 }
2492
2493 /* cmpd. */
2494 void
2495 OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
2496 {
2497 uint32_t a = (OP[0]);
2498 uint32_t b = GPR32 (OP[1]);
2499 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2500 SET_PSR_Z (a == b);
2501 SET_PSR_N ((int32_t)a > (int32_t)b);
2502 SET_PSR_L (a > b);
2503 trace_output_flag (sd);
2504 }
2505
2506 /* cmpd. */
2507 void
2508 OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
2509 {
2510 uint32_t a = (SEXT16(OP[0]));
2511 uint32_t b = GPR32 (OP[1]);
2512 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2513 SET_PSR_Z (a == b);
2514 SET_PSR_N ((int32_t)a > (int32_t)b);
2515 SET_PSR_L (a > b);
2516 trace_output_flag (sd);
2517 }
2518
2519 /* cmpd. */
2520 void
2521 OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
2522 {
2523 uint32_t a = GPR32 (OP[0]) ;
2524 uint32_t b = GPR32 (OP[1]) ;
2525 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2526 SET_PSR_Z (a == b);
2527 SET_PSR_N ((int32_t)a > (int32_t)b);
2528 SET_PSR_L (a > b);
2529 trace_output_flag (sd);
2530 }
2531
2532 /* cmpd. */
2533 void
2534 OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
2535 {
2536 uint32_t a = (OP[0]);
2537 uint32_t b = GPR32 (OP[1]);
2538 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2539 SET_PSR_Z (a == b);
2540 SET_PSR_N ((int32_t)a > (int32_t)b);
2541 SET_PSR_L (a > b);
2542 trace_output_flag (sd);
2543 }
2544
2545
2546 /* movb. */
2547 void
2548 OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
2549 {
2550 uint8_t tmp = OP[0] & 0xFF;
2551 uint16_t a = (GPR (OP[1])) & 0xFF00;
2552 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
2553 SET_GPR (OP[1], (a | tmp));
2554 trace_output_16 (sd, tmp);
2555 }
2556
2557 /* movb. */
2558 void
2559 OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
2560 {
2561 uint8_t tmp = OP[0] & 0xFF;
2562 uint16_t a = (GPR (OP[1])) & 0xFF00;
2563 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
2564 SET_GPR (OP[1], (a | tmp));
2565 trace_output_16 (sd, tmp);
2566 }
2567
2568 /* movb. */
2569 void
2570 OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
2571 {
2572 uint8_t tmp = (GPR (OP[0])) & 0xFF;
2573 uint16_t a = (GPR (OP[1])) & 0xFF00;
2574 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
2575 SET_GPR (OP[1], (a | tmp));
2576 trace_output_16 (sd, tmp);
2577 }
2578
2579 /* movw. */
2580 void
2581 OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
2582 {
2583 uint16_t tmp = OP[0];
2584 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2585 SET_GPR (OP[1], (tmp & 0xffff));
2586 trace_output_16 (sd, tmp);
2587 }
2588
2589 /* movw. */
2590 void
2591 OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
2592 {
2593 int16_t tmp = OP[0];
2594 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2595 SET_GPR (OP[1], (tmp & 0xffff));
2596 trace_output_16 (sd, tmp);
2597 }
2598
2599 /* movw. */
2600 void
2601 OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
2602 {
2603 uint16_t tmp = GPR (OP[0]);
2604 uint32_t a = GPR32 (OP[1]);
2605 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
2606 a = (a & 0xffff0000) | tmp;
2607 SET_GPR32 (OP[1], a);
2608 trace_output_16 (sd, tmp);
2609 }
2610
2611 /* movxb. */
2612 void
2613 OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
2614 {
2615 uint8_t tmp = (GPR (OP[0])) & 0xFF;
2616 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2617 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
2618 trace_output_16 (sd, tmp);
2619 }
2620
2621 /* movzb. */
2622 void
2623 OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
2624 {
2625 uint8_t tmp = (GPR (OP[0])) & 0xFF;
2626 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2627 SET_GPR (OP[1], tmp);
2628 trace_output_16 (sd, tmp);
2629 }
2630
2631 /* movxw. */
2632 void
2633 OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
2634 {
2635 uint16_t tmp = GPR (OP[0]);
2636 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2637 SET_GPR32 (OP[1], SEXT16(tmp));
2638 trace_output_16 (sd, tmp);
2639 }
2640
2641 /* movzw. */
2642 void
2643 OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
2644 {
2645 uint16_t tmp = GPR (OP[0]);
2646 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2647 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
2648 trace_output_16 (sd, tmp);
2649 }
2650
2651 /* movd. */
2652 void
2653 OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
2654 {
2655 int32_t tmp = OP[0];
2656 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2657 SET_GPR32 (OP[1], tmp);
2658 trace_output_32 (sd, tmp);
2659 }
2660
2661 /* movd. */
2662 void
2663 OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
2664 {
2665 int32_t tmp = SEXT16(OP[0]);
2666 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2667 SET_GPR32 (OP[1], tmp);
2668 trace_output_32 (sd, tmp);
2669 }
2670
2671 /* movd. */
2672 void
2673 OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
2674 {
2675 uint32_t tmp = GPR32 (OP[0]);
2676 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2677 SET_GPR32 (OP[1], tmp);
2678 trace_output_32 (sd, tmp);
2679 }
2680
2681 /* movd. */
2682 void
2683 OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
2684 {
2685 uint32_t tmp = OP[0];
2686 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2687 SET_GPR32 (OP[1], tmp);
2688 trace_output_32 (sd, tmp);
2689 }
2690
2691 /* movd. */
2692 void
2693 OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
2694 {
2695 int32_t tmp = OP[0];
2696 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2697 SET_GPR32 (OP[1], tmp);
2698 trace_output_32 (sd, tmp);
2699 }
2700
2701 /* loadm. */
2702 void
2703 OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
2704 {
2705 uint32_t addr = GPR (0);
2706 uint16_t count = OP[0], reg = 2, tmp;
2707 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2708 if ((addr & 1))
2709 {
2710 trace_output_void (sd);
2711 EXCEPTION (SIM_SIGBUS);
2712 }
2713
2714 while (count)
2715 {
2716 tmp = RW (addr);
2717 SET_GPR (reg, tmp);
2718 addr +=2;
2719 --count;
2720 reg++;
2721 if (reg == 6) reg = 8;
2722 };
2723
2724 SET_GPR (0, addr);
2725 trace_output_void (sd);
2726 }
2727
2728
2729 /* loadmp. */
2730 void
2731 OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
2732 {
2733 uint32_t addr = GPR32 (0);
2734 uint16_t count = OP[0], reg = 2, tmp;
2735 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2736 if ((addr & 1))
2737 {
2738 trace_output_void (sd);
2739 EXCEPTION (SIM_SIGBUS);
2740 }
2741
2742 while (count)
2743 {
2744 tmp = RW (addr);
2745 SET_GPR (reg, tmp);
2746 addr +=2;
2747 --count;
2748 reg++;
2749 if (reg == 6) reg = 8;
2750 };
2751
2752 SET_GPR32 (0, addr);
2753 trace_output_void (sd);
2754 }
2755
2756
2757 /* loadb. */
2758 void
2759 OP_88_8 (SIM_DESC sd, SIM_CPU *cpu)
2760 {
2761 /* loadb ABS20, REG
2762 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2763 * REG = [ADDR]
2764 * NOTE: remap is
2765 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2766 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2767 * by the core to 16M-64k to 16M. */
2768
2769 uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
2770 uint32_t addr = OP[0];
2771 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2772 if (addr > 0xEFFFF) addr |= 0xF00000;
2773 tmp = (RB (addr));
2774 SET_GPR (OP[1], (a | tmp));
2775 trace_output_16 (sd, tmp);
2776 }
2777
2778 /* loadb. */
2779 void
2780 OP_127_14 (SIM_DESC sd, SIM_CPU *cpu)
2781 {
2782 /* loadb ABS24, REG
2783 * ADDR = abs24
2784 * REGR = [ADDR]. */
2785
2786 uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
2787 uint32_t addr = OP[0];
2788 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2789 tmp = (RB (addr));
2790 SET_GPR (OP[1], (a | tmp));
2791 trace_output_16 (sd, tmp);
2792 }
2793
2794 /* loadb. */
2795 void
2796 OP_45_7 (SIM_DESC sd, SIM_CPU *cpu)
2797 {
2798 /* loadb [Rindex]ABS20 REG
2799 * ADDR = Rindex + zext24(disp20)
2800 * REGR = [ADDR]. */
2801
2802 uint32_t addr;
2803 uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
2804 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2805
2806 if (OP[0] == 0)
2807 addr = (GPR32 (12)) + OP[1];
2808 else
2809 addr = (GPR32 (13)) + OP[1];
2810
2811 tmp = (RB (addr));
2812 SET_GPR (OP[2], (a | tmp));
2813 trace_output_16 (sd, tmp);
2814 }
2815
2816
2817 /* loadb. */
2818 void
2819 OP_B_4 (SIM_DESC sd, SIM_CPU *cpu)
2820 {
2821 /* loadb DIPS4(REGP) REG
2822 * ADDR = RPBASE + zext24(DISP4)
2823 * REG = [ADDR]. */
2824 uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
2825 uint32_t addr = (GPR32 (OP[1])) + OP[0];
2826 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2827 tmp = (RB (addr));
2828 SET_GPR (OP[2], (a | tmp));
2829 trace_output_16 (sd, tmp);
2830 }
2831
2832 /* loadb. */
2833 void
2834 OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu)
2835 {
2836 /* loadb [Rindex]disp0(RPbasex) REG
2837 * ADDR = Rpbasex + Rindex
2838 * REGR = [ADDR] */
2839
2840 uint32_t addr;
2841 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
2842 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2843
2844 addr = (GPR32 (OP[2])) + OP[1];
2845
2846 if (OP[0] == 0)
2847 addr = (GPR32 (12)) + addr;
2848 else
2849 addr = (GPR32 (13)) + addr;
2850
2851 tmp = (RB (addr));
2852 SET_GPR (OP[3], (a | tmp));
2853 trace_output_16 (sd, tmp);
2854 }
2855
2856 /* loadb. */
2857 void
2858 OP_219_A (SIM_DESC sd, SIM_CPU *cpu)
2859 {
2860 /* loadb [Rindex]disp14(RPbasex) REG
2861 * ADDR = Rpbasex + Rindex + zext24(disp14)
2862 * REGR = [ADDR] */
2863
2864 uint32_t addr;
2865 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
2866
2867 addr = (GPR32 (OP[2])) + OP[1];
2868
2869 if (OP[0] == 0)
2870 addr = (GPR32 (12)) + addr;
2871 else
2872 addr = (GPR32 (13)) + addr;
2873
2874 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2875 tmp = (RB (addr));
2876 SET_GPR (OP[3], (a | tmp));
2877 trace_output_16 (sd, tmp);
2878 }
2879
2880
2881 /* loadb. */
2882 void
2883 OP_184_14 (SIM_DESC sd, SIM_CPU *cpu)
2884 {
2885 /* loadb DISPE20(REG) REG
2886 * zext24(Rbase) + zext24(dispe20)
2887 * REG = [ADDR] */
2888
2889 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2890 uint32_t addr = OP[0] + (GPR (OP[1]));
2891 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2892 tmp = (RB (addr));
2893 SET_GPR (OP[2], (a | tmp));
2894 trace_output_16 (sd, tmp);
2895 }
2896
2897 /* loadb. */
2898 void
2899 OP_124_14 (SIM_DESC sd, SIM_CPU *cpu)
2900 {
2901 /* loadb DISP20(REG) REG
2902 * ADDR = zext24(Rbase) + zext24(disp20)
2903 * REG = [ADDR] */
2904
2905 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2906 uint32_t addr = OP[0] + (GPR (OP[1]));
2907 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2908 tmp = (RB (addr));
2909 SET_GPR (OP[2], (a | tmp));
2910 trace_output_16 (sd, tmp);
2911 }
2912
2913 /* loadb. */
2914 void
2915 OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu)
2916 {
2917 /* loadb disp16(REGP) REG
2918 * ADDR = RPbase + zext24(disp16)
2919 * REGR = [ADDR] */
2920
2921 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2922 uint32_t addr = (GPR32 (OP[1])) + OP[0];
2923 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2924 tmp = (RB (addr));
2925 SET_GPR (OP[2], (a | tmp));
2926 trace_output_16 (sd, tmp);
2927 }
2928
2929 /* loadb. */
2930 void
2931 OP_125_14 (SIM_DESC sd, SIM_CPU *cpu)
2932 {
2933 /* loadb disp20(REGP) REG
2934 * ADDR = RPbase + zext24(disp20)
2935 * REGR = [ADDR] */
2936 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2937 uint32_t addr = (GPR32 (OP[1])) + OP[0];
2938 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2939 tmp = (RB (addr));
2940 SET_GPR (OP[2], (a | tmp));
2941 trace_output_16 (sd, tmp);
2942 }
2943
2944
2945 /* loadb. */
2946 void
2947 OP_185_14 (SIM_DESC sd, SIM_CPU *cpu)
2948 {
2949 /* loadb -disp20(REGP) REG
2950 * ADDR = RPbase + zext24(-disp20)
2951 * REGR = [ADDR] */
2952 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2953 uint32_t addr = (GPR32 (OP[1])) + OP[1];
2954 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2955 tmp = (RB (addr));
2956 SET_GPR (OP[2], (a | tmp));
2957 trace_output_16 (sd, tmp);
2958 }
2959
2960 /* loadb. */
2961 void
2962 OP_126_14 (SIM_DESC sd, SIM_CPU *cpu)
2963 {
2964 /* loadb [Rindex]disp20(RPbasexb) REG
2965 * ADDR = RPbasex + Rindex + zext24(disp20)
2966 * REGR = [ADDR] */
2967
2968 uint32_t addr;
2969 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
2970 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2971
2972 addr = (GPR32 (OP[2])) + OP[1];
2973
2974 if (OP[0] == 0)
2975 addr = (GPR32 (12)) + addr;
2976 else
2977 addr = (GPR32 (13)) + addr;
2978
2979 tmp = (RB (addr));
2980 SET_GPR (OP[3], (a | tmp));
2981 trace_output_16 (sd, tmp);
2982 }
2983
2984
2985 /* loadw. */
2986 void
2987 OP_89_8 (SIM_DESC sd, SIM_CPU *cpu)
2988 {
2989 /* loadw ABS20, REG
2990 * ADDR = zext24(abs20) | remap
2991 * REGR = [ADDR]
2992 * NOTE: remap is
2993 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2994 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2995 * by the core to 16M-64k to 16M. */
2996
2997 uint16_t tmp;
2998 uint32_t addr = OP[0];
2999 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
3000 if (addr > 0xEFFFF) addr |= 0xF00000;
3001 tmp = (RW (addr));
3002 SET_GPR (OP[1], tmp);
3003 trace_output_16 (sd, tmp);
3004 }
3005
3006
3007 /* loadw. */
3008 void
3009 OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu)
3010 {
3011 /* loadw ABS24, REG
3012 * ADDR = abs24
3013 * REGR = [ADDR] */
3014 uint16_t tmp;
3015 uint32_t addr = OP[0];
3016 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3017 tmp = (RW (addr));
3018 SET_GPR (OP[1], tmp);
3019 trace_output_16 (sd, tmp);
3020 }
3021
3022 /* loadw. */
3023 void
3024 OP_47_7 (SIM_DESC sd, SIM_CPU *cpu)
3025 {
3026 /* loadw [Rindex]ABS20 REG
3027 * ADDR = Rindex + zext24(disp20)
3028 * REGR = [ADDR] */
3029
3030 uint32_t addr;
3031 uint16_t tmp;
3032 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3033
3034 if (OP[0] == 0)
3035 addr = (GPR32 (12)) + OP[1];
3036 else
3037 addr = (GPR32 (13)) + OP[1];
3038
3039 tmp = (RW (addr));
3040 SET_GPR (OP[2], tmp);
3041 trace_output_16 (sd, tmp);
3042 }
3043
3044
3045 /* loadw. */
3046 void
3047 OP_9_4 (SIM_DESC sd, SIM_CPU *cpu)
3048 {
3049 /* loadw DIPS4(REGP) REGP
3050 * ADDR = RPBASE + zext24(DISP4)
3051 * REGP = [ADDR]. */
3052 uint16_t tmp;
3053 uint32_t addr, a;
3054 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3055 addr = (GPR32 (OP[1])) + OP[0];
3056 tmp = (RW (addr));
3057 if (OP[2] > 11)
3058 {
3059 a = (GPR32 (OP[2])) & 0xffff0000;
3060 SET_GPR32 (OP[2], (a | tmp));
3061 }
3062 else
3063 SET_GPR (OP[2], tmp);
3064
3065 trace_output_16 (sd, tmp);
3066 }
3067
3068
3069 /* loadw. */
3070 void
3071 OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu)
3072 {
3073 /* loadw [Rindex]disp0(RPbasex) REG
3074 * ADDR = Rpbasex + Rindex
3075 * REGR = [ADDR] */
3076
3077 uint32_t addr;
3078 uint16_t tmp;
3079 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3080
3081 addr = (GPR32 (OP[2])) + OP[1];
3082
3083 if (OP[0] == 0)
3084 addr = (GPR32 (12)) + addr;
3085 else
3086 addr = (GPR32 (13)) + addr;
3087
3088 tmp = RW (addr);
3089 SET_GPR (OP[3], tmp);
3090 trace_output_16 (sd, tmp);
3091 }
3092
3093
3094 /* loadw. */
3095 void
3096 OP_21B_A (SIM_DESC sd, SIM_CPU *cpu)
3097 {
3098 /* loadw [Rindex]disp14(RPbasex) REG
3099 * ADDR = Rpbasex + Rindex + zext24(disp14)
3100 * REGR = [ADDR] */
3101
3102 uint32_t addr;
3103 uint16_t tmp;
3104 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3105 addr = (GPR32 (OP[2])) + OP[1];
3106
3107 if (OP[0] == 0)
3108 addr = (GPR32 (12)) + addr;
3109 else
3110 addr = (GPR32 (13)) + addr;
3111
3112 tmp = (RW (addr));
3113 SET_GPR (OP[3], tmp);
3114 trace_output_16 (sd, tmp);
3115 }
3116
3117 /* loadw. */
3118 void
3119 OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu)
3120 {
3121 /* loadw dispe20(REG) REGP
3122 * REGP = [DISPE20+[REG]] */
3123
3124 uint16_t tmp;
3125 uint32_t addr, a;
3126 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3127 addr = OP[0] + (GPR (OP[1]));
3128 tmp = (RW (addr));
3129 if (OP[2] > 11)
3130 {
3131 a = (GPR32 (OP[2])) & 0xffff0000;
3132 SET_GPR32 (OP[2], (a | tmp));
3133 }
3134 else
3135 SET_GPR (OP[2], tmp);
3136
3137 trace_output_16 (sd, tmp);
3138 }
3139
3140
3141 /* loadw. */
3142 void
3143 OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu)
3144 {
3145 /* loadw DISP20(REG) REGP
3146 * ADDR = zext24(Rbase) + zext24(disp20)
3147 * REGP = [ADDR] */
3148
3149 uint16_t tmp;
3150 uint32_t addr, a;
3151 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3152 addr = OP[0] + (GPR (OP[1]));
3153 tmp = (RW (addr));
3154 if (OP[2] > 11)
3155 {
3156 a = (GPR32 (OP[2])) & 0xffff0000;
3157 SET_GPR32 (OP[2], (a | tmp));
3158 }
3159 else
3160 SET_GPR (OP[2], tmp);
3161
3162 trace_output_16 (sd, tmp);
3163 }
3164
3165 /* loadw. */
3166 void
3167 OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu)
3168 {
3169 /* loadw disp16(REGP) REGP
3170 * ADDR = RPbase + zext24(disp16)
3171 * REGP = [ADDR] */
3172 uint16_t tmp;
3173 uint32_t addr, a;
3174 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3175 addr = (GPR32 (OP[1])) + OP[0];
3176 tmp = (RW (addr));
3177 if (OP[2] > 11)
3178 {
3179 a = (GPR32 (OP[2])) & 0xffff0000;
3180 SET_GPR32 (OP[2], (a | tmp));
3181 }
3182 else
3183 SET_GPR (OP[2], tmp);
3184
3185 trace_output_16 (sd, tmp);
3186 }
3187
3188 /* loadw. */
3189 void
3190 OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu)
3191 {
3192 /* loadw disp20(REGP) REGP
3193 * ADDR = RPbase + zext24(disp20)
3194 * REGP = [ADDR] */
3195 uint16_t tmp;
3196 uint32_t addr, a;
3197 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3198 addr = (GPR32 (OP[1])) + OP[0];
3199 tmp = (RW (addr));
3200 if (OP[2] > 11)
3201 {
3202 a = (GPR32 (OP[2])) & 0xffff0000;
3203 SET_GPR32 (OP[2], (a | tmp));
3204 }
3205 else
3206 SET_GPR (OP[2], tmp);
3207
3208 trace_output_16 (sd, tmp);
3209 }
3210
3211 /* loadw. */
3212 void
3213 OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu)
3214 {
3215 /* loadw -disp20(REGP) REG
3216 * ADDR = RPbase + zext24(-disp20)
3217 * REGR = [ADDR] */
3218
3219 uint16_t tmp;
3220 uint32_t addr, a;
3221 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3222 addr = (GPR32 (OP[1])) + OP[0];
3223 tmp = (RB (addr));
3224 if (OP[2] > 11)
3225 {
3226 a = (GPR32 (OP[2])) & 0xffff0000;
3227 SET_GPR32 (OP[2], (a | tmp));
3228 }
3229 else
3230 SET_GPR (OP[2], tmp);
3231
3232 trace_output_16 (sd, tmp);
3233 }
3234
3235
3236 /* loadw. */
3237 void
3238 OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu)
3239 {
3240 /* loadw [Rindex]disp20(RPbasexb) REG
3241 * ADDR = RPbasex + Rindex + zext24(disp20)
3242 * REGR = [ADDR] */
3243
3244 uint32_t addr;
3245 uint16_t tmp;
3246 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3247
3248 if (OP[0] == 0)
3249 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3250 else
3251 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3252
3253 tmp = (RW (addr));
3254 SET_GPR (OP[3], tmp);
3255 trace_output_16 (sd, tmp);
3256 }
3257
3258
3259 /* loadd. */
3260 void
3261 OP_87_8 (SIM_DESC sd, SIM_CPU *cpu)
3262 {
3263 /* loadd ABS20, REGP
3264 * ADDR = zext24(abs20) | remap
3265 * REGP = [ADDR]
3266 * NOTE: remap is
3267 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3268 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3269 * by the core to 16M-64k to 16M. */
3270
3271 uint32_t addr, tmp;
3272 addr = OP[0];
3273 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3274 if (addr > 0xEFFFF) addr |= 0xF00000;
3275 tmp = RLW (addr);
3276 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3277 SET_GPR32 (OP[1], tmp);
3278 trace_output_32 (sd, tmp);
3279 }
3280
3281 /* loadd. */
3282 void
3283 OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu)
3284 {
3285 /* loadd ABS24, REGP
3286 * ADDR = abs24
3287 * REGP = [ADDR] */
3288
3289 uint32_t addr = OP[0];
3290 uint32_t tmp;
3291 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3292 tmp = RLW (addr);
3293 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3294 SET_GPR32 (OP[1],tmp);
3295 trace_output_32 (sd, tmp);
3296 }
3297
3298
3299 /* loadd. */
3300 void
3301 OP_46_7 (SIM_DESC sd, SIM_CPU *cpu)
3302 {
3303 /* loadd [Rindex]ABS20 REGP
3304 * ADDR = Rindex + zext24(disp20)
3305 * REGP = [ADDR] */
3306
3307 uint32_t addr, tmp;
3308 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3309
3310 if (OP[0] == 0)
3311 addr = (GPR32 (12)) + OP[1];
3312 else
3313 addr = (GPR32 (13)) + OP[1];
3314
3315 tmp = RLW (addr);
3316 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3317 SET_GPR32 (OP[2], tmp);
3318 trace_output_32 (sd, tmp);
3319 }
3320
3321
3322 /* loadd. */
3323 void
3324 OP_A_4 (SIM_DESC sd, SIM_CPU *cpu)
3325 {
3326 /* loadd dips4(regp) REGP
3327 * ADDR = Rpbase + zext24(disp4)
3328 * REGP = [ADDR] */
3329
3330 uint32_t tmp, addr = (GPR32 (OP[1])) + OP[0];
3331 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3332 tmp = RLW (addr);
3333 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3334 SET_GPR32 (OP[2], tmp);
3335 trace_output_32 (sd, tmp);
3336 }
3337
3338
3339 /* loadd. */
3340 void
3341 OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu)
3342 {
3343 /* loadd [Rindex]disp0(RPbasex) REGP
3344 * ADDR = Rpbasex + Rindex
3345 * REGP = [ADDR] */
3346
3347 uint32_t addr, tmp;
3348 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3349
3350 if (OP[0] == 0)
3351 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3352 else
3353 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3354
3355 tmp = RLW (addr);
3356 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3357 SET_GPR32 (OP[3], tmp);
3358 trace_output_32 (sd, tmp);
3359 }
3360
3361
3362 /* loadd. */
3363 void
3364 OP_21A_A (SIM_DESC sd, SIM_CPU *cpu)
3365 {
3366 /* loadd [Rindex]disp14(RPbasex) REGP
3367 * ADDR = Rpbasex + Rindex + zext24(disp14)
3368 * REGR = [ADDR] */
3369
3370 uint32_t addr, tmp;
3371 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3372
3373 if (OP[0] == 0)
3374 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3375 else
3376 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3377
3378 tmp = RLW (addr);
3379 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3380 SET_GPR (OP[3],tmp);
3381 trace_output_32 (sd, tmp);
3382 }
3383
3384
3385 /* loadd. */
3386 void
3387 OP_188_14 (SIM_DESC sd, SIM_CPU *cpu)
3388 {
3389 /* loadd dispe20(REG) REG
3390 * zext24(Rbase) + zext24(dispe20)
3391 * REG = [ADDR] */
3392
3393 uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
3394 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3395 tmp = RLW (addr);
3396 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3397 SET_GPR32 (OP[2], tmp);
3398 trace_output_32 (sd, tmp);
3399 }
3400
3401
3402 /* loadd. */
3403 void
3404 OP_128_14 (SIM_DESC sd, SIM_CPU *cpu)
3405 {
3406 /* loadd DISP20(REG) REG
3407 * ADDR = zext24(Rbase) + zext24(disp20)
3408 * REG = [ADDR] */
3409
3410 uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
3411 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3412 tmp = RLW (addr);
3413 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3414 SET_GPR32 (OP[2], tmp);
3415 trace_output_32 (sd, tmp);
3416 }
3417
3418 /* loadd. */
3419 void
3420 OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu)
3421 {
3422 /* loadd disp16(REGP) REGP
3423 * ADDR = RPbase + zext24(disp16)
3424 * REGR = [ADDR] */
3425 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
3426 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3427 tmp = RLW (addr);
3428 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3429 SET_GPR32 (OP[2], tmp);
3430 trace_output_32 (sd, tmp);
3431 }
3432
3433
3434 /* loadd. */
3435 void
3436 OP_129_14 (SIM_DESC sd, SIM_CPU *cpu)
3437 {
3438 /* loadd disp20(REGP) REGP
3439 * ADDR = RPbase + zext24(disp20)
3440 * REGP = [ADDR] */
3441 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
3442 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3443 tmp = RLW (addr);
3444 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3445 SET_GPR32 (OP[2], tmp);
3446 trace_output_32 (sd, tmp);
3447 }
3448
3449 /* loadd. */
3450 void
3451 OP_189_14 (SIM_DESC sd, SIM_CPU *cpu)
3452 {
3453 /* loadd -disp20(REGP) REGP
3454 * ADDR = RPbase + zext24(-disp20)
3455 * REGP = [ADDR] */
3456
3457 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
3458 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3459 tmp = RLW (addr);
3460 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3461 SET_GPR32 (OP[2], tmp);
3462 trace_output_32 (sd, tmp);
3463 }
3464
3465 /* loadd. */
3466 void
3467 OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu)
3468 {
3469 /* loadd [Rindex]disp20(RPbasexb) REGP
3470 * ADDR = RPbasex + Rindex + zext24(disp20)
3471 * REGP = [ADDR] */
3472
3473 uint32_t addr, tmp;
3474 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3475
3476 if (OP[0] == 0)
3477 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3478 else
3479 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3480
3481 tmp = RLW (addr);
3482 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3483 SET_GPR32 (OP[3], tmp);
3484 trace_output_32 (sd, tmp);
3485 }
3486
3487
3488 /* storb. */
3489 void
3490 OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu)
3491 {
3492 /* storb REG, ABS20
3493 * ADDR = zext24(abs20) | remap
3494 * [ADDR] = REGR
3495 * NOTE: remap is
3496 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3497 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3498 * by the core to 16M-64k to 16M. */
3499
3500 uint8_t a = ((GPR (OP[0])) & 0xff);
3501 uint32_t addr = OP[1];
3502 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3503 SB (addr, a);
3504 trace_output_32 (sd, addr);
3505 }
3506
3507 /* storb. */
3508 void
3509 OP_137_14 (SIM_DESC sd, SIM_CPU *cpu)
3510 {
3511 /* storb REG, ABS24
3512 * ADDR = abs24
3513 * [ADDR] = REGR. */
3514
3515 uint8_t a = ((GPR (OP[0])) & 0xff);
3516 uint32_t addr = OP[1];
3517 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3518 SB (addr, a);
3519 trace_output_32 (sd, addr);
3520 }
3521
3522 /* storb. */
3523 void
3524 OP_65_7 (SIM_DESC sd, SIM_CPU *cpu)
3525 {
3526 /* storb REG, [Rindex]ABS20
3527 * ADDR = Rindex + zext24(disp20)
3528 * [ADDR] = REGR */
3529
3530 uint32_t addr;
3531 uint8_t a = ((GPR (OP[0])) & 0xff);
3532 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3533
3534 if (OP[1] == 0)
3535 addr = (GPR32 (12)) + OP[2];
3536 else
3537 addr = (GPR32 (13)) + OP[2];
3538
3539 SB (addr, a);
3540 trace_output_32 (sd, addr);
3541 }
3542
3543 /* storb. */
3544 void
3545 OP_F_4 (SIM_DESC sd, SIM_CPU *cpu)
3546 {
3547 /* storb REG, DIPS4(REGP)
3548 * ADDR = RPBASE + zext24(DISP4)
3549 * [ADDR] = REG. */
3550
3551 uint16_t a = ((GPR (OP[0])) & 0xff);
3552 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3553 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
3554 SB (addr, a);
3555 trace_output_32 (sd, addr);
3556 }
3557
3558 /* storb. */
3559 void
3560 OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu)
3561 {
3562 /* storb [Rindex]disp0(RPbasex) REG
3563 * ADDR = Rpbasex + Rindex
3564 * [ADDR] = REGR */
3565
3566 uint32_t addr;
3567 uint8_t a = ((GPR (OP[0])) & 0xff);
3568 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3569
3570 if (OP[1] == 0)
3571 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3572 else
3573 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3574
3575 SB (addr, a);
3576 trace_output_32 (sd, addr);
3577 }
3578
3579 /* storb. */
3580 void
3581 OP_319_A (SIM_DESC sd, SIM_CPU *cpu)
3582 {
3583 /* storb REG, [Rindex]disp14(RPbasex)
3584 * ADDR = Rpbasex + Rindex + zext24(disp14)
3585 * [ADDR] = REGR */
3586
3587 uint8_t a = ((GPR (OP[0])) & 0xff);
3588 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3589 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3590 SB (addr, a);
3591 trace_output_32 (sd, addr);
3592 }
3593
3594 /* storb. */
3595 void
3596 OP_194_14 (SIM_DESC sd, SIM_CPU *cpu)
3597 {
3598 /* storb REG, DISPE20(REG)
3599 * zext24(Rbase) + zext24(dispe20)
3600 * [ADDR] = REG */
3601
3602 uint8_t a = ((GPR (OP[0])) & 0xff);
3603 uint32_t addr = OP[1] + (GPR (OP[2]));
3604 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
3605 SB (addr, a);
3606 trace_output_32 (sd, addr);
3607 }
3608
3609 /* storb. */
3610 void
3611 OP_134_14 (SIM_DESC sd, SIM_CPU *cpu)
3612 {
3613 /* storb REG, DISP20(REG)
3614 * ADDR = zext24(Rbase) + zext24(disp20)
3615 * [ADDR] = REG */
3616
3617 uint8_t a = (GPR (OP[0]) & 0xff);
3618 uint32_t addr = OP[1] + (GPR (OP[2]));
3619 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3620 SB (addr, a);
3621 trace_output_32 (sd, addr);
3622 }
3623
3624 /* storb. */
3625 void
3626 OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu)
3627 {
3628 /* storb REG, disp16(REGP)
3629 * ADDR = RPbase + zext24(disp16)
3630 * [ADDR] = REGP */
3631
3632 uint8_t a = ((GPR (OP[0])) & 0xff);
3633 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3634 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3635 SB (addr, a);
3636 trace_output_32 (sd, addr);
3637 }
3638
3639 /* storb. */
3640 void
3641 OP_135_14 (SIM_DESC sd, SIM_CPU *cpu)
3642 {
3643 /* storb REG, disp20(REGP)
3644 * ADDR = RPbase + zext24(disp20)
3645 * [ADDR] = REGP */
3646
3647 uint8_t a = ((GPR (OP[0])) & 0xff);
3648 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3649 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3650 SB (addr, a);
3651 trace_output_32 (sd, addr);
3652 }
3653
3654 /* storb. */
3655 void
3656 OP_195_14 (SIM_DESC sd, SIM_CPU *cpu)
3657 {
3658 /* storb REG, -disp20(REGP)
3659 * ADDR = RPbase + zext24(-disp20)
3660 * [ADDR] = REGP */
3661
3662 uint8_t a = (GPR (OP[0]) & 0xff);
3663 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3664 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3665 SB (addr, a);
3666 trace_output_32 (sd, addr);
3667 }
3668
3669 /* storb. */
3670 void
3671 OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
3672 {
3673 /* storb REG, [Rindex]disp20(RPbase)
3674 * ADDR = RPbasex + Rindex + zext24(disp20)
3675 * [ADDR] = REGP */
3676
3677 uint8_t a = (GPR (OP[0])) & 0xff;
3678 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3679 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3680 SB (addr, a);
3681 trace_output_32 (sd, addr);
3682 }
3683
3684 /* STR_IMM instructions. */
3685 /* storb . */
3686 void
3687 OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
3688 {
3689 uint8_t a = (OP[0]) & 0xff;
3690 uint32_t addr = OP[1];
3691 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3692 SB (addr, a);
3693 trace_output_32 (sd, addr);
3694 }
3695
3696 /* storb. */
3697 void
3698 OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
3699 {
3700 uint8_t a = (OP[0]) & 0xff;
3701 uint32_t addr = OP[1];
3702 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3703 SB (addr, a);
3704 trace_output_32 (sd, addr);
3705 }
3706
3707 /* storb. */
3708 void
3709 OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
3710 {
3711 uint32_t addr;
3712 uint8_t a = (OP[0]) & 0xff;
3713 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3714
3715 if (OP[1] == 0)
3716 addr = (GPR32 (12)) + OP[2];
3717 else
3718 addr = (GPR32 (13)) + OP[2];
3719
3720 SB (addr, a);
3721 trace_output_32 (sd, addr);
3722 }
3723
3724 /* storb. */
3725 void
3726 OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
3727 {
3728 uint8_t a = (OP[0]) & 0xff;
3729 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3730 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3731 SB (addr, a);
3732 trace_output_32 (sd, addr);
3733 }
3734
3735 /* storb. */
3736 void
3737 OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
3738 {
3739 uint8_t a = (OP[0]) & 0xff;
3740 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3741 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3742 SB (addr, a);
3743 trace_output_32 (sd, addr);
3744 }
3745
3746 /* storb. */
3747 void
3748 OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
3749 {
3750 uint8_t a = (OP[0]) & 0xff;
3751 uint32_t addr = (GPR (OP[2])) + OP[1];
3752 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3753 SB (addr, a);
3754 trace_output_32 (sd, addr);
3755 }
3756
3757 /* storb. */
3758 void
3759 OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
3760 {
3761 uint8_t a = (OP[0]) & 0xff;
3762 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3763 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
3764 SB (addr, a);
3765 trace_output_32 (sd, addr);
3766 }
3767
3768 /* storb. */
3769 void
3770 OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
3771 {
3772 uint8_t a = (OP[0]) & 0xff;
3773 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3774 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
3775 SB (addr, a);
3776 trace_output_32 (sd, addr);
3777 }
3778
3779 /* storb. */
3780 void
3781 OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
3782 {
3783 uint8_t a = (OP[0]) & 0xff;
3784 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3785 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
3786 SB (addr, a);
3787 trace_output_32 (sd, addr);
3788 }
3789 /* endif for STR_IMM. */
3790
3791 /* storw . */
3792 void
3793 OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
3794 {
3795 uint16_t a = GPR (OP[0]);
3796 uint32_t addr = OP[1];
3797 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3798 SW (addr, a);
3799 trace_output_32 (sd, addr);
3800 }
3801
3802 /* storw. */
3803 void
3804 OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
3805 {
3806 uint16_t a = GPR (OP[0]);
3807 uint32_t addr = OP[1];
3808 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3809 SW (addr, a);
3810 trace_output_32 (sd, addr);
3811 }
3812
3813 /* storw. */
3814 void
3815 OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
3816 {
3817 uint32_t addr;
3818 uint16_t a = GPR (OP[0]);
3819 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3820
3821 if (OP[1] == 0)
3822 addr = (GPR32 (12)) + OP[2];
3823 else
3824 addr = (GPR32 (13)) + OP[2];
3825
3826 SW (addr, a);
3827 trace_output_32 (sd, addr);
3828 }
3829
3830
3831 /* storw. */
3832 void
3833 OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
3834 {
3835 uint16_t a = (GPR (OP[0]));
3836 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3837 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
3838 SW (addr, a);
3839 trace_output_32 (sd, addr);
3840 }
3841
3842 /* storw. */
3843 void
3844 OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
3845 {
3846 uint16_t a = GPR (OP[0]);
3847 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3848 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3849 SW (addr, a);
3850 trace_output_32 (sd, addr);
3851 }
3852
3853 /* storw. */
3854 void
3855 OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
3856 {
3857 uint16_t a = GPR (OP[0]);
3858 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3859 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3860 SW (addr, a);
3861 trace_output_32 (sd, addr);
3862 }
3863
3864 /* storw. */
3865 void
3866 OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
3867 {
3868 uint16_t a = (GPR (OP[0]));
3869 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3870 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
3871 SW (addr, a);
3872 trace_output_32 (sd, addr);
3873 }
3874
3875 /* storw. */
3876 void
3877 OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
3878 {
3879 uint16_t a = (GPR (OP[0]));
3880 uint32_t addr = (GPR (OP[2])) + OP[1];
3881 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3882 SW (addr, a);
3883 trace_output_32 (sd, addr);
3884 }
3885
3886 /* storw. */
3887 void
3888 OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
3889 {
3890 uint16_t a = (GPR (OP[0]));
3891 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3892 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3893 SW (addr, a);
3894 trace_output_32 (sd, addr);
3895 }
3896
3897 /* storw. */
3898 void
3899 OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
3900 {
3901 uint16_t a = (GPR (OP[0]));
3902 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3903 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3904 SW (addr, a);
3905 trace_output_32 (sd, addr);
3906 }
3907
3908 /* storw. */
3909 void
3910 OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
3911 {
3912 uint16_t a = (GPR (OP[0]));
3913 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3914 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3915 SW (addr, a);
3916 trace_output_32 (sd, addr);
3917 }
3918
3919 /* storw. */
3920 void
3921 OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
3922 {
3923 uint16_t a = (GPR (OP[0]));
3924 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3925 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3926 SW (addr, a);
3927 trace_output_32 (sd, addr);
3928 }
3929
3930 /* STORE-w IMM instruction *****/
3931 /* storw . */
3932 void
3933 OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
3934 {
3935 uint16_t a = OP[0];
3936 uint32_t addr = OP[1];
3937 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3938 SW (addr, a);
3939 trace_output_32 (sd, addr);
3940 }
3941
3942 /* storw. */
3943 void
3944 OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
3945 {
3946 uint16_t a = OP[0];
3947 uint32_t addr = OP[1];
3948 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3949 SW (addr, a);
3950 trace_output_32 (sd, addr);
3951 }
3952
3953 /* storw. */
3954 void
3955 OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
3956 {
3957 uint32_t addr;
3958 uint16_t a = OP[0];
3959 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3960
3961 if (OP[1] == 0)
3962 addr = (GPR32 (12)) + OP[2];
3963 else
3964 addr = (GPR32 (13)) + OP[2];
3965
3966 SW (addr, a);
3967 trace_output_32 (sd, addr);
3968 }
3969
3970 /* storw. */
3971 void
3972 OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
3973 {
3974 uint16_t a = OP[0];
3975 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3976 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3977 SW (addr, a);
3978 trace_output_32 (sd, addr);
3979 }
3980
3981 /* storw. */
3982 void
3983 OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
3984 {
3985 uint16_t a = OP[0];
3986 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3987 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3988 SW (addr, a);
3989 trace_output_32 (sd, addr);
3990 }
3991
3992 /* storw. */
3993 void
3994 OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
3995 {
3996 uint16_t a = OP[0];
3997 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3998 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3999 SW (addr, a);
4000 trace_output_32 (sd, addr);
4001 }
4002
4003 /* storw. */
4004 void
4005 OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
4006 {
4007 uint16_t a = OP[0];
4008 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4009 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
4010 SW (addr, a);
4011 trace_output_32 (sd, addr);
4012 }
4013
4014
4015 /* storw. */
4016 void
4017 OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
4018 {
4019 uint16_t a = OP[0];
4020 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4021 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
4022 SW (addr, a);
4023 trace_output_32 (sd, addr);
4024 }
4025
4026 /* storw. */
4027 void
4028 OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
4029 {
4030 uint16_t a = OP[0];
4031 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4032 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
4033 SW (addr, a);
4034 trace_output_32 (sd, addr);
4035 }
4036
4037
4038 /* stord. */
4039 void
4040 OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
4041 {
4042 uint32_t a = GPR32 (OP[0]);
4043 uint32_t addr = OP[1];
4044 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
4045 SLW (addr, a);
4046 trace_output_32 (sd, addr);
4047 }
4048
4049 /* stord. */
4050 void
4051 OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
4052 {
4053 uint32_t a = GPR32 (OP[0]);
4054 uint32_t addr = OP[1];
4055 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
4056 SLW (addr, a);
4057 trace_output_32 (sd, addr);
4058 }
4059
4060 /* stord. */
4061 void
4062 OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
4063 {
4064 uint32_t addr, a = GPR32 (OP[0]);
4065 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4066
4067 if (OP[1] == 0)
4068 addr = (GPR32 (12)) + OP[2];
4069 else
4070 addr = (GPR32 (13)) + OP[2];
4071
4072 SLW (addr, a);
4073 trace_output_32 (sd, addr);
4074 }
4075
4076 /* stord. */
4077 void
4078 OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
4079 {
4080 uint32_t a = GPR32 (OP[0]);
4081 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4082 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
4083 SLW (addr, a);
4084 trace_output_32 (sd, addr);
4085 }
4086
4087 /* stord. */
4088 void
4089 OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
4090 {
4091 uint32_t a = GPR32 (OP[0]);
4092 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4093 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
4094 SLW (addr, a);
4095 trace_output_32 (sd, addr);
4096 }
4097
4098 /* stord. */
4099 void
4100 OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
4101 {
4102 uint32_t a = GPR32 (OP[0]);
4103 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4104 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
4105 SLW (addr, a);
4106 trace_output_32 (sd, addr);
4107 }
4108
4109 /* stord. */
4110 void
4111 OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
4112 {
4113 uint32_t a = GPR32 (OP[0]);
4114 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4115 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
4116 SLW (addr, a);
4117 trace_output_32 (sd, addr);
4118 }
4119
4120 /* stord. */
4121 void
4122 OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
4123 {
4124 uint32_t a = GPR32 (OP[0]);
4125 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4126 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
4127 SLW (addr, a);
4128 trace_output_32 (sd, addr);
4129 }
4130
4131 /* stord. */
4132 void
4133 OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
4134 {
4135 uint32_t a = GPR32 (OP[0]);
4136 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4137 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
4138 SLW (addr, a);
4139 trace_output_32 (sd, addr);
4140 }
4141
4142 /* stord. */
4143 void
4144 OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
4145 {
4146 uint32_t a = GPR32 (OP[0]);
4147 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4148 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
4149 SLW (addr, a);
4150 trace_output_32 (sd, addr);
4151 }
4152
4153 /* stord. */
4154 void
4155 OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
4156 {
4157 uint32_t a = GPR32 (OP[0]);
4158 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4159 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
4160 SLW (addr, a);
4161 trace_output_32 (sd, addr);
4162 }
4163
4164 /* stord. */
4165 void
4166 OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
4167 {
4168 uint32_t a = GPR32 (OP[0]);
4169 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4170 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
4171 SLW (addr, a);
4172 trace_output_32 (sd, addr);
4173 }
4174
4175 /* macqu. */
4176 void
4177 OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
4178 {
4179 int32_t tmp;
4180 int16_t src1, src2;
4181 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4182 src1 = GPR (OP[0]);
4183 src2 = GPR (OP[1]);
4184 tmp = src1 * src2;
4185 /*REVISIT FOR SATURATION and Q FORMAT. */
4186 SET_GPR32 (OP[2], tmp);
4187 trace_output_32 (sd, tmp);
4188 }
4189
4190 /* macuw. */
4191 void
4192 OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
4193 {
4194 uint32_t tmp;
4195 uint16_t src1, src2;
4196 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4197 src1 = GPR (OP[0]);
4198 src2 = GPR (OP[1]);
4199 tmp = src1 * src2;
4200 /*REVISIT FOR SATURATION. */
4201 SET_GPR32 (OP[2], tmp);
4202 trace_output_32 (sd, tmp);
4203 }
4204
4205 /* macsw. */
4206 void
4207 OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
4208 {
4209 int32_t tmp;
4210 int16_t src1, src2;
4211 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4212 src1 = GPR (OP[0]);
4213 src2 = GPR (OP[1]);
4214 tmp = src1 * src2;
4215 /*REVISIT FOR SATURATION. */
4216 SET_GPR32 (OP[2], tmp);
4217 trace_output_32 (sd, tmp);
4218 }
4219
4220
4221 /* mulb. */
4222 void
4223 OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
4224 {
4225 int16_t tmp;
4226 int8_t a = (OP[0]) & 0xff;
4227 int8_t b = (GPR (OP[1])) & 0xff;
4228 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4229 tmp = (a * b) & 0xff;
4230 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4231 trace_output_16 (sd, tmp);
4232 }
4233
4234 /* mulb. */
4235 void
4236 OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
4237 {
4238 int16_t tmp;
4239 int8_t a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4240 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4241 tmp = (a * b) & 0xff;
4242 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4243 trace_output_16 (sd, tmp);
4244 }
4245
4246
4247 /* mulb. */
4248 void
4249 OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
4250 {
4251 int16_t tmp;
4252 int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4253 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4254 tmp = (a * b) & 0xff;
4255 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4256 trace_output_16 (sd, tmp);
4257 }
4258
4259
4260 /* mulw. */
4261 void
4262 OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
4263 {
4264 int32_t tmp;
4265 uint16_t a = OP[0];
4266 int16_t b = (GPR (OP[1]));
4267 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4268 tmp = (a * b) & 0xffff;
4269 SET_GPR (OP[1], tmp);
4270 trace_output_32 (sd, tmp);
4271 }
4272
4273 /* mulw. */
4274 void
4275 OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
4276 {
4277 int32_t tmp;
4278 int16_t a = OP[0], b = (GPR (OP[1]));
4279 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4280 tmp = (a * b) & 0xffff;
4281 SET_GPR (OP[1], tmp);
4282 trace_output_32 (sd, tmp);
4283 }
4284
4285
4286 /* mulw. */
4287 void
4288 OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
4289 {
4290 int32_t tmp;
4291 int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
4292 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4293 tmp = (a * b) & 0xffff;
4294 SET_GPR (OP[1], tmp);
4295 trace_output_32 (sd, tmp);
4296 }
4297
4298
4299 /* mulsb. */
4300 void
4301 OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
4302 {
4303 int16_t tmp;
4304 int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4305 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4306 tmp = a * b;
4307 SET_GPR (OP[1], tmp);
4308 trace_output_32 (sd, tmp);
4309 }
4310
4311 /* mulsw. */
4312 void
4313 OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
4314 {
4315 int32_t tmp;
4316 int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
4317 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4318 tmp = a * b;
4319 SET_GPR32 (OP[1], tmp);
4320 trace_output_32 (sd, tmp);
4321 }
4322
4323 /* muluw. */
4324 void
4325 OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
4326 {
4327 uint32_t tmp;
4328 uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
4329 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4330 tmp = a * b;
4331 SET_GPR32 (OP[1], tmp);
4332 trace_output_32 (sd, tmp);
4333 }
4334
4335
4336 /* nop. */
4337 void
4338 OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu)
4339 {
4340 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4341
4342 #if 0
4343 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4344 switch (State.ins_type)
4345 {
4346 default:
4347 ins_type_counters[ (int)INS_UNKNOWN ]++;
4348 break;
4349
4350 }
4351 EXCEPTION (SIM_SIGTRAP);
4352 #endif
4353 trace_output_void (sd);
4354 }
4355
4356
4357 /* orb. */
4358 void
4359 OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
4360 {
4361 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4362 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4363 tmp = a | b;
4364 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4365 trace_output_16 (sd, tmp);
4366 }
4367
4368 /* orb. */
4369 void
4370 OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
4371 {
4372 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4373 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4374 tmp = a | b;
4375 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4376 trace_output_16 (sd, tmp);
4377 }
4378
4379 /* orb. */
4380 void
4381 OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
4382 {
4383 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4384 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4385 tmp = a | b;
4386 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4387 trace_output_16 (sd, tmp);
4388 }
4389
4390 /* orw. */
4391 void
4392 OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
4393 {
4394 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
4395 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4396 tmp = a | b;
4397 SET_GPR (OP[1], tmp);
4398 trace_output_16 (sd, tmp);
4399 }
4400
4401
4402 /* orw. */
4403 void
4404 OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
4405 {
4406 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
4407 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4408 tmp = a | b;
4409 SET_GPR (OP[1], tmp);
4410 trace_output_16 (sd, tmp);
4411 }
4412
4413 /* orw. */
4414 void
4415 OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
4416 {
4417 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
4418 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4419 tmp = a | b;
4420 SET_GPR (OP[1], tmp);
4421 trace_output_16 (sd, tmp);
4422 }
4423
4424
4425 /* lshb. */
4426 void
4427 OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
4428 {
4429 uint16_t a = OP[0];
4430 uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
4431 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4432 /* A positive count specifies a shift to the left;
4433 * A negative count specifies a shift to the right. */
4434 if (sign_flag)
4435 tmp = b >> a;
4436 else
4437 tmp = b << a;
4438
4439 sign_flag = 0; /* Reset sign_flag. */
4440
4441 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4442 trace_output_16 (sd, tmp);
4443 }
4444
4445 /* lshb. */
4446 void
4447 OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
4448 {
4449 uint16_t a = (GPR (OP[0])) & 0xff;
4450 uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
4451 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4452 if (a & ((long)1 << 3))
4453 {
4454 sign_flag = 1;
4455 a = ~(a) + 1;
4456 }
4457 a = (unsigned int) (a & 0x7);
4458
4459 /* A positive count specifies a shift to the left;
4460 * A negative count specifies a shift to the right. */
4461 if (sign_flag)
4462 tmp = b >> a;
4463 else
4464 tmp = b << a;
4465
4466 sign_flag = 0; /* Reset sign_flag. */
4467 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4468 trace_output_16 (sd, tmp);
4469 }
4470
4471 /* lshw. */
4472 void
4473 OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
4474 {
4475 uint16_t tmp, b = GPR (OP[1]);
4476 int16_t a = GPR (OP[0]);
4477 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4478 if (a & ((long)1 << 4))
4479 {
4480 sign_flag = 1;
4481 a = ~(a) + 1;
4482 }
4483 a = (unsigned int) (a & 0xf);
4484
4485 /* A positive count specifies a shift to the left;
4486 * A negative count specifies a shift to the right. */
4487 if (sign_flag)
4488 tmp = b >> a;
4489 else
4490 tmp = b << a;
4491
4492 sign_flag = 0; /* Reset sign_flag. */
4493 SET_GPR (OP[1], (tmp & 0xffff));
4494 trace_output_16 (sd, tmp);
4495 }
4496
4497 /* lshw. */
4498 void
4499 OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
4500 {
4501 uint16_t tmp, b = GPR (OP[1]);
4502 uint16_t a = OP[0];
4503 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4504 /* A positive count specifies a shift to the left;
4505 * A negative count specifies a shift to the right. */
4506 if (sign_flag)
4507 tmp = b >> a;
4508 else
4509 tmp = b << a;
4510
4511 sign_flag = 0; /* Reset sign_flag. */
4512 SET_GPR (OP[1], (tmp & 0xffff));
4513 trace_output_16 (sd, tmp);
4514 }
4515
4516 /* lshd. */
4517 void
4518 OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
4519 {
4520 uint32_t tmp, b = GPR32 (OP[1]);
4521 uint16_t a = OP[0];
4522 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4523 /* A positive count specifies a shift to the left;
4524 * A negative count specifies a shift to the right. */
4525 if (sign_flag)
4526 tmp = b >> a;
4527 else
4528 tmp = b << a;
4529
4530 sign_flag = 0; /* Reset sign flag. */
4531
4532 SET_GPR32 (OP[1], tmp);
4533 trace_output_32 (sd, tmp);
4534 }
4535
4536 /* lshd. */
4537 void
4538 OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
4539 {
4540 uint32_t tmp, b = GPR32 (OP[1]);
4541 uint16_t a = GPR (OP[0]);
4542 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4543 if (a & ((long)1 << 5))
4544 {
4545 sign_flag = 1;
4546 a = ~(a) + 1;
4547 }
4548 a = (unsigned int) (a & 0x1f);
4549 /* A positive count specifies a shift to the left;
4550 * A negative count specifies a shift to the right. */
4551 if (sign_flag)
4552 tmp = b >> a;
4553 else
4554 tmp = b << a;
4555
4556 sign_flag = 0; /* Reset sign flag. */
4557
4558 SET_GPR32 (OP[1], tmp);
4559 trace_output_32 (sd, tmp);
4560 }
4561
4562 /* ashub. */
4563 void
4564 OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
4565 {
4566 uint16_t a = OP[0];
4567 int8_t tmp, b = (GPR (OP[1])) & 0xFF;
4568 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4569 /* A positive count specifies a shift to the left;
4570 * A negative count specifies a shift to the right. */
4571 if (sign_flag)
4572 tmp = b >> a;
4573 else
4574 tmp = b << a;
4575
4576 sign_flag = 0; /* Reset sign flag. */
4577
4578 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
4579 trace_output_16 (sd, tmp);
4580 }
4581
4582 /* ashub. */
4583 void
4584 OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
4585 {
4586 uint16_t a = OP[0];
4587 int8_t tmp, b = (GPR (OP[1])) & 0xFF;
4588 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4589 /* A positive count specifies a shift to the left;
4590 * A negative count specifies a shift to the right. */
4591 if (sign_flag)
4592 tmp = b >> a;
4593 else
4594 tmp = b << a;
4595
4596 sign_flag = 0; /* Reset sign flag. */
4597
4598 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4599 trace_output_16 (sd, tmp);
4600 }
4601
4602
4603 /* ashub. */
4604 void
4605 OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
4606 {
4607 int16_t a = (GPR (OP[0]));
4608 int8_t tmp, b = (GPR (OP[1])) & 0xFF;
4609 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4610
4611 if (a & ((long)1 << 3))
4612 {
4613 sign_flag = 1;
4614 a = ~(a) + 1;
4615 }
4616 a = (unsigned int) (a & 0x7);
4617
4618 /* A positive count specifies a shift to the left;
4619 * A negative count specifies a shift to the right. */
4620 if (sign_flag)
4621 tmp = b >> a;
4622 else
4623 tmp = b << a;
4624
4625 sign_flag = 0; /* Reset sign flag. */
4626
4627 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4628 trace_output_16 (sd, tmp);
4629 }
4630
4631
4632 /* ashuw. */
4633 void
4634 OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
4635 {
4636 int16_t tmp, b = GPR (OP[1]);
4637 uint16_t a = OP[0];
4638 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4639 /* A positive count specifies a shift to the left;
4640 * A negative count specifies a shift to the right. */
4641 if (sign_flag)
4642 tmp = b >> a;
4643 else
4644 tmp = b << a;
4645
4646 sign_flag = 0; /* Reset sign flag. */
4647
4648 SET_GPR (OP[1], (tmp & 0xffff));
4649 trace_output_16 (sd, tmp);
4650 }
4651
4652 /* ashuw. */
4653 void
4654 OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
4655 {
4656 int16_t tmp, b = GPR (OP[1]);
4657 uint16_t a = OP[0];
4658 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4659 /* A positive count specifies a shift to the left;
4660 * A negative count specifies a shift to the right. */
4661 if (sign_flag)
4662 tmp = b >> a;
4663 else
4664 tmp = b << a;
4665
4666 sign_flag = 0; /* Reset sign flag. */
4667 SET_GPR (OP[1], (tmp & 0xffff));
4668 trace_output_16 (sd, tmp);
4669 }
4670
4671 /* ashuw. */
4672 void
4673 OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
4674 {
4675 int16_t tmp;
4676 int16_t a = GPR (OP[0]), b = GPR (OP[1]);
4677 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4678
4679 if (a & ((long)1 << 4))
4680 {
4681 sign_flag = 1;
4682 a = ~(a) + 1;
4683 }
4684 a = (unsigned int) (a & 0xf);
4685 /* A positive count specifies a shift to the left;
4686 * A negative count specifies a shift to the right. */
4687
4688 if (sign_flag)
4689 tmp = b >> a;
4690 else
4691 tmp = b << a;
4692
4693 sign_flag = 0; /* Reset sign flag. */
4694 SET_GPR (OP[1], (tmp & 0xffff));
4695 trace_output_16 (sd, tmp);
4696 }
4697
4698 /* ashud. */
4699 void
4700 OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
4701 {
4702 int32_t tmp,b = GPR32 (OP[1]);
4703 uint32_t a = OP[0];
4704 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4705 /* A positive count specifies a shift to the left;
4706 * A negative count specifies a shift to the right. */
4707 if (sign_flag)
4708 tmp = b >> a;
4709 else
4710 tmp = b << a;
4711
4712 sign_flag = 0; /* Reset sign flag. */
4713 SET_GPR32 (OP[1], tmp);
4714 trace_output_32 (sd, tmp);
4715 }
4716
4717 /* ashud. */
4718 void
4719 OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
4720 {
4721 int32_t tmp;
4722 int32_t a = OP[0], b = GPR32 (OP[1]);
4723 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4724 /* A positive count specifies a shift to the left;
4725 * A negative count specifies a shift to the right. */
4726 if (sign_flag)
4727 tmp = b >> a;
4728 else
4729 tmp = b << a;
4730
4731 sign_flag = 0; /* Reset sign flag. */
4732 SET_GPR32 (OP[1], tmp);
4733 trace_output_32 (sd, tmp);
4734 }
4735
4736 /* ashud. */
4737 void
4738 OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
4739 {
4740 int32_t tmp;
4741 int32_t a = GPR32 (OP[0]), b = GPR32 (OP[1]);
4742 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4743
4744 if (a & ((long)1 << 5))
4745 {
4746 sign_flag = 1;
4747 a = ~(a) + 1;
4748 }
4749 a = (unsigned int) (a & 0x1f);
4750 /* A positive count specifies a shift to the left;
4751 * A negative count specifies a shift to the right. */
4752 if (sign_flag)
4753 tmp = b >> a;
4754 else
4755 tmp = b << a;
4756
4757 sign_flag = 0; /* Reset sign flag. */
4758 SET_GPR32 (OP[1], tmp);
4759 trace_output_32 (sd, tmp);
4760 }
4761
4762
4763 /* storm. */
4764 void
4765 OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
4766 {
4767 uint32_t addr = GPR (1);
4768 uint16_t count = OP[0], reg = 2;
4769 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4770 if ((addr & 1))
4771 {
4772 trace_output_void (sd);
4773 EXCEPTION (SIM_SIGBUS);
4774 }
4775
4776 while (count)
4777 {
4778 SW (addr, (GPR (reg)));
4779 addr +=2;
4780 --count;
4781 reg++;
4782 if (reg == 6) reg = 8;
4783 };
4784
4785 SET_GPR (1, addr);
4786
4787 trace_output_void (sd);
4788 }
4789
4790
4791 /* stormp. */
4792 void
4793 OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
4794 {
4795 uint32_t addr = GPR32 (6);
4796 uint16_t count = OP[0], reg = 2;
4797 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4798 if ((addr & 1))
4799 {
4800 trace_output_void (sd);
4801 EXCEPTION (SIM_SIGBUS);
4802 }
4803
4804 while (count)
4805 {
4806 SW (addr, (GPR (reg)));
4807 addr +=2;
4808 --count;
4809 reg++;
4810 if (reg == 6) reg = 8;
4811 };
4812
4813 SET_GPR32 (6, addr);
4814 trace_output_void (sd);
4815 }
4816
4817 /* subb. */
4818 void
4819 OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
4820 {
4821 uint8_t a = OP[0];
4822 uint8_t b = (GPR (OP[1])) & 0xff;
4823 uint16_t tmp = (~a + 1 + b) & 0xff;
4824 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4825 /* see ../common/sim-alu.h for a more extensive discussion on how to
4826 compute the carry/overflow bits. */
4827 SET_PSR_C (tmp > 0xff);
4828 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4829 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4830 trace_output_16 (sd, tmp);
4831 }
4832
4833 /* subb. */
4834 void
4835 OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
4836 {
4837 uint8_t a = OP[0] & 0xFF;
4838 uint8_t b = (GPR (OP[1])) & 0xFF;
4839 uint16_t tmp = (~a + 1 + b) & 0xFF;
4840 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4841 /* see ../common/sim-alu.h for a more extensive discussion on how to
4842 compute the carry/overflow bits. */
4843 SET_PSR_C (tmp > 0xff);
4844 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4845 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4846 trace_output_16 (sd, tmp);
4847 }
4848
4849 /* subb. */
4850 void
4851 OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
4852 {
4853 uint8_t a = (GPR (OP[0])) & 0xFF;
4854 uint8_t b = (GPR (OP[1])) & 0xFF;
4855 uint16_t tmp = (~a + 1 + b) & 0xff;
4856 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4857 /* see ../common/sim-alu.h for a more extensive discussion on how to
4858 compute the carry/overflow bits. */
4859 SET_PSR_C (tmp > 0xff);
4860 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4861 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4862 trace_output_16 (sd, tmp);
4863 }
4864
4865 /* subw. */
4866 void
4867 OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
4868 {
4869 uint16_t a = OP[0];
4870 uint16_t b = GPR (OP[1]);
4871 uint16_t tmp = (~a + 1 + b);
4872 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4873 /* see ../common/sim-alu.h for a more extensive discussion on how to
4874 compute the carry/overflow bits. */
4875 SET_PSR_C (tmp > 0xffff);
4876 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4877 SET_GPR (OP[1], tmp);
4878 trace_output_16 (sd, tmp);
4879 }
4880
4881 /* subw. */
4882 void
4883 OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
4884 {
4885 uint16_t a = OP[0];
4886 uint16_t b = GPR (OP[1]);
4887 uint32_t tmp = (~a + 1 + b);
4888 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4889 /* see ../common/sim-alu.h for a more extensive discussion on how to
4890 compute the carry/overflow bits. */
4891 SET_PSR_C (tmp > 0xffff);
4892 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4893 SET_GPR (OP[1], tmp & 0xffff);
4894 trace_output_16 (sd, tmp);
4895 }
4896
4897 /* subw. */
4898 void
4899 OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
4900 {
4901 uint16_t a = GPR (OP[0]);
4902 uint16_t b = GPR (OP[1]);
4903 uint32_t tmp = (~a + 1 + b);
4904 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4905 /* see ../common/sim-alu.h for a more extensive discussion on how to
4906 compute the carry/overflow bits. */
4907 SET_PSR_C (tmp > 0xffff);
4908 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4909 SET_GPR (OP[1], tmp & 0xffff);
4910 trace_output_16 (sd, tmp);
4911 }
4912
4913 /* subcb. */
4914 void
4915 OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
4916 {
4917 uint8_t a = OP[0];
4918 uint8_t b = (GPR (OP[1])) & 0xff;
4919 //uint16_t tmp1 = a + 1;
4920 uint16_t tmp1 = a + (PSR_C);
4921 uint16_t tmp = (~tmp1 + 1 + b);
4922 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4923 /* see ../common/sim-alu.h for a more extensive discussion on how to
4924 compute the carry/overflow bits. */
4925 SET_PSR_C (tmp > 0xff);
4926 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4927 SET_GPR (OP[1], tmp);
4928 trace_output_16 (sd, tmp);
4929 }
4930
4931 /* subcb. */
4932 void
4933 OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
4934 {
4935 uint16_t a = OP[0];
4936 uint16_t b = (GPR (OP[1])) & 0xff;
4937 //uint16_t tmp1 = a + 1;
4938 uint16_t tmp1 = a + (PSR_C);
4939 uint16_t tmp = (~tmp1 + 1 + b);
4940 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4941 /* see ../common/sim-alu.h for a more extensive discussion on how to
4942 compute the carry/overflow bits. */
4943 SET_PSR_C (tmp > 0xff);
4944 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4945 SET_GPR (OP[1], tmp);
4946 trace_output_16 (sd, tmp);
4947 }
4948
4949 /* subcb. */
4950 void
4951 OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
4952 {
4953 uint16_t a = (GPR (OP[0])) & 0xff;
4954 uint16_t b = (GPR (OP[1])) & 0xff;
4955 uint16_t tmp1 = a + (PSR_C);
4956 uint16_t tmp = (~tmp1 + 1 + b);
4957 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4958 /* see ../common/sim-alu.h for a more extensive discussion on how to
4959 compute the carry/overflow bits. */
4960 SET_PSR_C (tmp > 0xff);
4961 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4962 SET_GPR (OP[1], tmp);
4963 trace_output_16 (sd, tmp);
4964 }
4965
4966 /* subcw. */
4967 void
4968 OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
4969 {
4970 uint16_t a = OP[0], b = (GPR (OP[1]));
4971 uint16_t tmp1 = a + (PSR_C);
4972 uint16_t tmp = (~tmp1 + 1 + b);
4973 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4974 /* see ../common/sim-alu.h for a more extensive discussion on how to
4975 compute the carry/overflow bits. */
4976 SET_PSR_C (tmp > 0xffff);
4977 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4978 SET_GPR (OP[1], tmp);
4979 trace_output_16 (sd, tmp);
4980 }
4981
4982 /* subcw. */
4983 void
4984 OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
4985 {
4986 int16_t a = OP[0];
4987 uint16_t b = GPR (OP[1]);
4988 uint16_t tmp1 = a + (PSR_C);
4989 uint16_t tmp = (~tmp1 + 1 + b);
4990 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
4991 /* see ../common/sim-alu.h for a more extensive discussion on how to
4992 compute the carry/overflow bits. */
4993 SET_PSR_C (tmp > 0xffff);
4994 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4995 SET_GPR (OP[1], tmp);
4996 trace_output_16 (sd, tmp);
4997 }
4998
4999 /* subcw. */
5000 void
5001 OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
5002 {
5003 uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
5004 uint16_t tmp1 = a + (PSR_C);
5005 uint16_t tmp = (~tmp1 + 1 + b);
5006 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5007 /* see ../common/sim-alu.h for a more extensive discussion on how to
5008 compute the carry/overflow bits. */
5009 SET_PSR_C (tmp > 0xffff);
5010 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5011 SET_GPR (OP[1], tmp);
5012 trace_output_16 (sd, tmp);
5013 }
5014
5015 /* subd. */
5016 void
5017 OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
5018 {
5019 int32_t a = OP[0];
5020 uint32_t b = GPR32 (OP[1]);
5021 uint32_t tmp = (~a + 1 + b);
5022 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5023 /* see ../common/sim-alu.h for a more extensive discussion on how to
5024 compute the carry/overflow bits. */
5025 SET_PSR_C (tmp > 0xffffffff);
5026 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5027 ((b & 0x80000000) != (tmp & 0x80000000)));
5028 SET_GPR32 (OP[1], tmp);
5029 trace_output_32 (sd, tmp);
5030 }
5031
5032 /* subd. */
5033 void
5034 OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
5035 {
5036 uint32_t a = GPR32 (OP[0]);
5037 uint32_t b = GPR32 (OP[1]);
5038 uint32_t tmp = (~a + 1 + b);
5039 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5040 /* see ../common/sim-alu.h for a more extensive discussion on how to
5041 compute the carry/overflow bits. */
5042 SET_PSR_C (tmp > 0xffffffff);
5043 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5044 ((b & 0x80000000) != (tmp & 0x80000000)));
5045 SET_GPR32 (OP[1], tmp);
5046 trace_output_32 (sd, tmp);
5047 }
5048
5049 /* excp. */
5050 void
5051 OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
5052 {
5053 host_callback *cb = STATE_CALLBACK (sd);
5054 uint32_t tmp;
5055 uint16_t a;
5056 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5057 switch (OP[0])
5058 {
5059 default:
5060 #if (DEBUG & DEBUG_TRAP) == 0
5061 {
5062 #if 0
5063 uint16_t vec = OP[0] + TRAP_VECTOR_START;
5064 SET_BPC (PC + 1);
5065 SET_BPSR (PSR);
5066 SET_PSR (PSR & PSR_SM_BIT);
5067 JMP (vec);
5068 break;
5069 #endif
5070 }
5071 #else /* if debugging use trap to print registers */
5072 {
5073 int i;
5074 static int first_time = 1;
5075
5076 if (first_time)
5077 {
5078 first_time = 0;
5079 sim_io_printf (sd, "Trap # PC ");
5080 for (i = 0; i < 16; i++)
5081 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i);
5082 sim_io_printf (sd, " a0 a1 f0 f1 c\n");
5083 }
5084
5085 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
5086
5087 for (i = 0; i < 16; i++)
5088 sim_io_printf (sd, " %.4x", (int) GPR (i));
5089
5090 for (i = 0; i < 2; i++)
5091 sim_io_printf (sd, " %.2x%.8lx",
5092 ((int)(ACC (i) >> 32) & 0xff),
5093 ((unsigned long) ACC (i)) & 0xffffffff);
5094
5095 sim_io_printf (sd, " %d %d %d\n",
5096 PSR_F != 0, PSR_F != 0, PSR_C != 0);
5097 sim_io_flush_stdout (sd);
5098 break;
5099 }
5100 #endif
5101 case 8: /* new system call trap */
5102 /* Trap 8 is used for simulating low-level I/O */
5103 {
5104 uint32_t result = 0;
5105 errno = 0;
5106
5107 /* Registers passed to trap 0. */
5108
5109 #define FUNC GPR (0) /* function number. */
5110 #define PARM1 GPR (2) /* optional parm 1. */
5111 #define PARM2 GPR (3) /* optional parm 2. */
5112 #define PARM3 GPR (4) /* optional parm 3. */
5113 #define PARM4 GPR (5) /* optional parm 4. */
5114
5115 /* Registers set by trap 0 */
5116
5117 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5118 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5119 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5120
5121 /* Turn a pointer in a register into a pointer into real memory. */
5122
5123 #define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x)
5124
5125 switch (FUNC)
5126 {
5127 #if !defined(__GO32__) && !defined(_WIN32)
5128 case TARGET_NEWLIB_CR16_SYS_fork:
5129 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5130 RETVAL (fork ());
5131 trace_output_16 (sd, result);
5132 break;
5133
5134 #define getpid() 47
5135 case TARGET_NEWLIB_CR16_SYS_getpid:
5136 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5137 RETVAL (getpid ());
5138 trace_output_16 (sd, result);
5139 break;
5140
5141 case TARGET_NEWLIB_CR16_SYS_kill:
5142 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5143 if (PARM1 == getpid ())
5144 {
5145 trace_output_void (sd);
5146 EXCEPTION (PARM2);
5147 }
5148 else
5149 {
5150 int os_sig = -1;
5151 switch (PARM2)
5152 {
5153 #ifdef SIGHUP
5154 case 1: os_sig = SIGHUP; break;
5155 #endif
5156 #ifdef SIGINT
5157 case 2: os_sig = SIGINT; break;
5158 #endif
5159 #ifdef SIGQUIT
5160 case 3: os_sig = SIGQUIT; break;
5161 #endif
5162 #ifdef SIGILL
5163 case 4: os_sig = SIGILL; break;
5164 #endif
5165 #ifdef SIGTRAP
5166 case 5: os_sig = SIGTRAP; break;
5167 #endif
5168 #ifdef SIGABRT
5169 case 6: os_sig = SIGABRT; break;
5170 #elif defined(SIGIOT)
5171 case 6: os_sig = SIGIOT; break;
5172 #endif
5173 #ifdef SIGEMT
5174 case 7: os_sig = SIGEMT; break;
5175 #endif
5176 #ifdef SIGFPE
5177 case 8: os_sig = SIGFPE; break;
5178 #endif
5179 #ifdef SIGKILL
5180 case 9: os_sig = SIGKILL; break;
5181 #endif
5182 #ifdef SIGBUS
5183 case 10: os_sig = SIGBUS; break;
5184 #endif
5185 #ifdef SIGSEGV
5186 case 11: os_sig = SIGSEGV; break;
5187 #endif
5188 #ifdef SIGSYS
5189 case 12: os_sig = SIGSYS; break;
5190 #endif
5191 #ifdef SIGPIPE
5192 case 13: os_sig = SIGPIPE; break;
5193 #endif
5194 #ifdef SIGALRM
5195 case 14: os_sig = SIGALRM; break;
5196 #endif
5197 #ifdef SIGTERM
5198 case 15: os_sig = SIGTERM; break;
5199 #endif
5200 #ifdef SIGURG
5201 case 16: os_sig = SIGURG; break;
5202 #endif
5203 #ifdef SIGSTOP
5204 case 17: os_sig = SIGSTOP; break;
5205 #endif
5206 #ifdef SIGTSTP
5207 case 18: os_sig = SIGTSTP; break;
5208 #endif
5209 #ifdef SIGCONT
5210 case 19: os_sig = SIGCONT; break;
5211 #endif
5212 #ifdef SIGCHLD
5213 case 20: os_sig = SIGCHLD; break;
5214 #elif defined(SIGCLD)
5215 case 20: os_sig = SIGCLD; break;
5216 #endif
5217 #ifdef SIGTTIN
5218 case 21: os_sig = SIGTTIN; break;
5219 #endif
5220 #ifdef SIGTTOU
5221 case 22: os_sig = SIGTTOU; break;
5222 #endif
5223 #ifdef SIGIO
5224 case 23: os_sig = SIGIO; break;
5225 #elif defined (SIGPOLL)
5226 case 23: os_sig = SIGPOLL; break;
5227 #endif
5228 #ifdef SIGXCPU
5229 case 24: os_sig = SIGXCPU; break;
5230 #endif
5231 #ifdef SIGXFSZ
5232 case 25: os_sig = SIGXFSZ; break;
5233 #endif
5234 #ifdef SIGVTALRM
5235 case 26: os_sig = SIGVTALRM; break;
5236 #endif
5237 #ifdef SIGPROF
5238 case 27: os_sig = SIGPROF; break;
5239 #endif
5240 #ifdef SIGWINCH
5241 case 28: os_sig = SIGWINCH; break;
5242 #endif
5243 #ifdef SIGLOST
5244 case 29: os_sig = SIGLOST; break;
5245 #endif
5246 #ifdef SIGUSR1
5247 case 30: os_sig = SIGUSR1; break;
5248 #endif
5249 #ifdef SIGUSR2
5250 case 31: os_sig = SIGUSR2; break;
5251 #endif
5252 }
5253
5254 if (os_sig == -1)
5255 {
5256 trace_output_void (sd);
5257 sim_io_printf (sd, "Unknown signal %d\n", PARM2);
5258 sim_io_flush_stdout (sd);
5259 EXCEPTION (SIM_SIGILL);
5260 }
5261 else
5262 {
5263 RETVAL (kill (PARM1, PARM2));
5264 trace_output_16 (sd, result);
5265 }
5266 }
5267 break;
5268
5269 case TARGET_NEWLIB_CR16_SYS_execve:
5270 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5271 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5272 (char **)MEMPTR (PARM4)));
5273 trace_output_16 (sd, result);
5274 break;
5275
5276 case TARGET_NEWLIB_CR16_SYS_execv:
5277 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5278 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
5279 trace_output_16 (sd, result);
5280 break;
5281
5282 case TARGET_NEWLIB_CR16_SYS_pipe:
5283 {
5284 reg_t buf;
5285 int host_fd[2];
5286
5287 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5288 buf = PARM1;
5289 RETVAL (pipe (host_fd));
5290 SW (buf, host_fd[0]);
5291 buf += sizeof(uint16_t);
5292 SW (buf, host_fd[1]);
5293 trace_output_16 (sd, result);
5294 }
5295 break;
5296
5297 case TARGET_NEWLIB_CR16_SYS_wait:
5298 {
5299 int status;
5300 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5301 RETVAL (wait (&status));
5302 if (PARM1)
5303 SW (PARM1, status);
5304 trace_output_16 (sd, result);
5305 }
5306 break;
5307 #else
5308 case TARGET_NEWLIB_CR16_SYS_getpid:
5309 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5310 RETVAL (1);
5311 trace_output_16 (sd, result);
5312 break;
5313
5314 case TARGET_NEWLIB_CR16_SYS_kill:
5315 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5316 trace_output_void (sd);
5317 EXCEPTION (PARM2);
5318 break;
5319 #endif
5320
5321 case TARGET_NEWLIB_CR16_SYS_read:
5322 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
5323 RETVAL (cb->read (cb, PARM1,
5324 MEMPTR (((unsigned long)PARM3 << 16)
5325 | ((unsigned long)PARM2)), PARM4));
5326 trace_output_16 (sd, result);
5327 break;
5328
5329 case TARGET_NEWLIB_CR16_SYS_write:
5330 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
5331 RETVAL ((int)cb->write (cb, PARM1,
5332 MEMPTR (((unsigned long)PARM3 << 16)
5333 | PARM2), PARM4));
5334 trace_output_16 (sd, result);
5335 break;
5336
5337 case TARGET_NEWLIB_CR16_SYS_lseek:
5338 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
5339 RETVAL32 (cb->lseek (cb, PARM1, ((((long) PARM3) << 16) | PARM2),
5340 PARM4));
5341 trace_output_32 (sd, result);
5342 break;
5343
5344 case TARGET_NEWLIB_CR16_SYS_close:
5345 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
5346 RETVAL (cb->close (cb, PARM1));
5347 trace_output_16 (sd, result);
5348 break;
5349
5350 case TARGET_NEWLIB_CR16_SYS_open:
5351 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
5352 RETVAL32 (cb->open (cb, MEMPTR ((((unsigned long)PARM2) << 16)
5353 | PARM1), PARM3));
5354 trace_output_32 (sd, result);
5355 break;
5356
5357 case TARGET_NEWLIB_CR16_SYS_rename:
5358 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
5359 RETVAL (cb->rename (cb, MEMPTR ((((unsigned long)PARM2) << 16) | PARM1),
5360 MEMPTR ((((unsigned long)PARM4) << 16) | PARM3)));
5361 trace_output_16 (sd, result);
5362 break;
5363
5364 case 0x408: /* REVISIT: Added a dummy getenv call. */
5365 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5366 RETVAL32 (0);
5367 trace_output_32 (sd, result);
5368 break;
5369
5370 case TARGET_NEWLIB_CR16_SYS_exit:
5371 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
5372 trace_output_void (sd);
5373 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5374 break;
5375
5376 case TARGET_NEWLIB_CR16_SYS_unlink:
5377 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
5378 RETVAL (cb->unlink (cb, MEMPTR (((unsigned long)PARM2 << 16) | PARM1)));
5379 trace_output_16 (sd, result);
5380 break;
5381
5382 case TARGET_NEWLIB_CR16_SYS_stat:
5383 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5384 /* stat system call. */
5385 {
5386 struct stat host_stat;
5387 reg_t buf;
5388
5389 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5390
5391 buf = PARM2;
5392
5393 /* The hard-coded offsets and sizes were determined by using
5394 * the CR16 compiler on a test program that used struct stat.
5395 */
5396 SW (buf, host_stat.st_dev);
5397 SW (buf+2, host_stat.st_ino);
5398 SW (buf+4, host_stat.st_mode);
5399 SW (buf+6, host_stat.st_nlink);
5400 SW (buf+8, host_stat.st_uid);
5401 SW (buf+10, host_stat.st_gid);
5402 SW (buf+12, host_stat.st_rdev);
5403 SLW (buf+16, host_stat.st_size);
5404 SLW (buf+20, host_stat.st_atime);
5405 SLW (buf+28, host_stat.st_mtime);
5406 SLW (buf+36, host_stat.st_ctime);
5407 }
5408 trace_output_16 (sd, result);
5409 break;
5410
5411 case TARGET_NEWLIB_CR16_SYS_chown:
5412 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5413 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
5414 trace_output_16 (sd, result);
5415 break;
5416
5417 case TARGET_NEWLIB_CR16_SYS_chmod:
5418 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5419 RETVAL (chmod (MEMPTR (PARM1), PARM2));
5420 trace_output_16 (sd, result);
5421 break;
5422
5423 case TARGET_NEWLIB_CR16_SYS_utime:
5424 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5425 /* Cast the second argument to void *, to avoid type mismatch
5426 if a prototype is present. */
5427 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
5428 trace_output_16 (sd, result);
5429 break;
5430
5431 case TARGET_NEWLIB_CR16_SYS_time:
5432 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5433 RETVAL32 (time (NULL));
5434 trace_output_32 (sd, result);
5435 break;
5436
5437 default:
5438 a = OP[0];
5439 switch (a)
5440 {
5441 case TRAP_BREAKPOINT:
5442 tmp = (PC);
5443 JMP(tmp);
5444 trace_output_void (sd);
5445 EXCEPTION (SIM_SIGTRAP);
5446 break;
5447 case SIGTRAP: /* supervisor call ? */
5448 trace_output_void (sd);
5449 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5450 break;
5451 default:
5452 cb->error (cb, "Unknown syscall %d", FUNC);
5453 break;
5454 }
5455 }
5456 if ((uint16_t) result == (uint16_t) -1)
5457 RETERR (cb->get_errno (cb));
5458 else
5459 RETERR (0);
5460 break;
5461 }
5462 }
5463 }
5464
5465
5466 /* push. */
5467 void
5468 OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
5469 {
5470 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5471 uint32_t tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
5472 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5473
5474 for (; i < a; ++i)
5475 {
5476 if ((b+i) <= 11)
5477 {
5478 SW (sp_addr, (GPR (b+i)));
5479 sp_addr +=2;
5480 }
5481 else
5482 {
5483 if (is_regp == 0)
5484 tmp = (GPR32 (b+i));
5485 else
5486 tmp = (GPR32 (b+i-1));
5487
5488 if ((a-i) > 1)
5489 {
5490 SLW (sp_addr, tmp);
5491 sp_addr +=4;
5492 }
5493 else
5494 {
5495 SW (sp_addr, tmp);
5496 sp_addr +=2;
5497 }
5498 ++i;
5499 is_regp = 1;
5500 }
5501 }
5502
5503 sp_addr +=4;
5504
5505 /* Store RA address. */
5506 tmp = (GPR32 (14));
5507 SLW(sp_addr,tmp);
5508
5509 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5510 SET_GPR32 (15, sp_addr); /* Update SP address. */
5511
5512 trace_output_void (sd);
5513 }
5514
5515 /* push. */
5516 void
5517 OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
5518 {
5519 uint32_t sp_addr, tmp, is_regp = 0;
5520 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5521 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5522
5523 if (c == 1)
5524 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5525 else
5526 sp_addr = (GPR32 (15)) - (a * 2);
5527
5528 for (; i < a; ++i)
5529 {
5530 if ((b+i) <= 11)
5531 {
5532 SW (sp_addr, (GPR (b+i)));
5533 sp_addr +=2;
5534 }
5535 else
5536 {
5537 if (is_regp == 0)
5538 tmp = (GPR32 (b+i));
5539 else
5540 tmp = (GPR32 (b+i-1));
5541
5542 if ((a-i) > 1)
5543 {
5544 SLW (sp_addr, tmp);
5545 sp_addr +=4;
5546 }
5547 else
5548 {
5549 SW (sp_addr, tmp);
5550 sp_addr +=2;
5551 }
5552 ++i;
5553 is_regp = 1;
5554 }
5555 }
5556
5557 if (c == 1)
5558 {
5559 /* Store RA address. */
5560 tmp = (GPR32 (14));
5561 SLW(sp_addr,tmp);
5562 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5563 }
5564 else
5565 sp_addr = (GPR32 (15)) - (a * 2);
5566
5567 SET_GPR32 (15, sp_addr); /* Update SP address. */
5568
5569 trace_output_void (sd);
5570 }
5571
5572
5573 /* push. */
5574 void
5575 OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
5576 {
5577 uint32_t sp_addr = (GPR32 (15)), tmp;
5578 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5579 tmp = (GPR32 (14));
5580 SLW(sp_addr-4,tmp); /* Store RA address. */
5581 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
5582 trace_output_void (sd);
5583 }
5584
5585
5586 /* pop. */
5587 void
5588 OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
5589 {
5590 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5591 uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
5592 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5593
5594 for (; i < a; ++i)
5595 {
5596 if ((b+i) <= 11)
5597 {
5598 SET_GPR ((b+i), RW(sp_addr));
5599 sp_addr +=2;
5600 }
5601 else
5602 {
5603 if ((a-i) > 1)
5604 {
5605 tmp = RLW(sp_addr);
5606 sp_addr +=4;
5607 }
5608 else
5609 {
5610 tmp = RW(sp_addr);
5611 sp_addr +=2;
5612
5613 if (is_regp == 0)
5614 tmp = (tmp << 16) | (GPR32 (b+i));
5615 else
5616 tmp = (tmp << 16) | (GPR32 (b+i-1));
5617 }
5618
5619 if (is_regp == 0)
5620 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5621 | ((tmp >> 16) & 0xffff)));
5622 else
5623 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5624 | ((tmp >> 16) & 0xffff)));
5625
5626 ++i;
5627 is_regp = 1;
5628 }
5629 }
5630
5631 tmp = RLW(sp_addr); /* store RA also. */
5632 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5633
5634 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5635
5636 trace_output_void (sd);
5637 }
5638
5639 /* pop. */
5640 void
5641 OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
5642 {
5643 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5644 uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;
5645 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5646
5647 for (; i < a; ++i)
5648 {
5649 if ((b+i) <= 11)
5650 {
5651 SET_GPR ((b+i), RW(sp_addr));
5652 sp_addr +=2;
5653 }
5654 else
5655 {
5656 if ((a-i) > 1)
5657 {
5658 tmp = RLW(sp_addr);
5659 sp_addr +=4;
5660 }
5661 else
5662 {
5663 tmp = RW(sp_addr);
5664 sp_addr +=2;
5665
5666 if (is_regp == 0)
5667 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5668 else
5669 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5670 }
5671
5672 if (is_regp == 0)
5673 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5674 else
5675 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5676 ++i;
5677 is_regp = 1;
5678 }
5679 }
5680
5681 if (c == 1)
5682 {
5683 tmp = RLW(sp_addr); /* Store RA Reg. */
5684 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5685 sp_addr +=4;
5686 }
5687
5688 SET_GPR32 (15, sp_addr); /* Update SP address. */
5689
5690 trace_output_void (sd);
5691 }
5692
5693 /* pop. */
5694 void
5695 OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
5696 {
5697 uint32_t sp_addr = GPR32 (15);
5698 uint32_t tmp;
5699 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5700
5701 tmp = RLW(sp_addr);
5702 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5703 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5704
5705 trace_output_void (sd);
5706 }
5707
5708 /* popret. */
5709 void
5710 OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
5711 {
5712 uint16_t a = OP[0], b = OP[1];
5713 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
5714 OP_5_9 (sd, cpu);
5715 JMP(((GPR32(14)) << 1) & 0xffffff);
5716
5717 trace_output_void (sd);
5718 }
5719
5720 /* popret. */
5721 void
5722 OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
5723 {
5724 uint16_t a = OP[0], b = OP[1];
5725 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
5726 OP_2_8 (sd, cpu);
5727 JMP(((GPR32(14)) << 1) & 0xffffff);
5728
5729 trace_output_void (sd);
5730 }
5731
5732 /* popret. */
5733 void
5734 OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
5735 {
5736 uint32_t tmp;
5737 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
5738 OP_21E_10 (sd, cpu);
5739 tmp = (((GPR32(14)) << 1) & 0xffffff);
5740 /* If the resulting PC value is less than 0x00_0000 or greater
5741 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5742
5743 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5744 {
5745 trace_output_void (sd);
5746 EXCEPTION (SIM_SIGBUS);
5747 }
5748 else
5749 JMP (tmp);
5750
5751 trace_output_32 (sd, tmp);
5752 }
5753
5754
5755 /* cinv[i]. */
5756 void
5757 OP_A_10 (SIM_DESC sd, SIM_CPU *cpu)
5758 {
5759 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5760 SET_PSR_I (1);
5761 trace_output_void (sd);
5762 }
5763
5764 /* cinv[i,u]. */
5765 void
5766 OP_B_10 (SIM_DESC sd, SIM_CPU *cpu)
5767 {
5768 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5769 SET_PSR_I (1);
5770 trace_output_void (sd);
5771 }
5772
5773 /* cinv[d]. */
5774 void
5775 OP_C_10 (SIM_DESC sd, SIM_CPU *cpu)
5776 {
5777 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5778 SET_PSR_I (1);
5779 trace_output_void (sd);
5780 }
5781
5782 /* cinv[d,u]. */
5783 void
5784 OP_D_10 (SIM_DESC sd, SIM_CPU *cpu)
5785 {
5786 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5787 SET_PSR_I (1);
5788 trace_output_void (sd);
5789 }
5790
5791 /* cinv[d,i]. */
5792 void
5793 OP_E_10 (SIM_DESC sd, SIM_CPU *cpu)
5794 {
5795 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5796 SET_PSR_I (1);
5797 trace_output_void (sd);
5798 }
5799
5800 /* cinv[d,i,u]. */
5801 void
5802 OP_F_10 (SIM_DESC sd, SIM_CPU *cpu)
5803 {
5804 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5805 SET_PSR_I (1);
5806 trace_output_void (sd);
5807 }
5808
5809 /* retx. */
5810 void
5811 OP_3_10 (SIM_DESC sd, SIM_CPU *cpu)
5812 {
5813 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5814 SET_PSR_I (1);
5815 trace_output_void (sd);
5816 }
5817
5818 /* di. */
5819 void
5820 OP_4_10 (SIM_DESC sd, SIM_CPU *cpu)
5821 {
5822 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5823 SET_PSR_I (1);
5824 trace_output_void (sd);
5825 }
5826
5827 /* ei. */
5828 void
5829 OP_5_10 (SIM_DESC sd, SIM_CPU *cpu)
5830 {
5831 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5832 SET_PSR_I (1);
5833 trace_output_void (sd);
5834 }
5835
5836 /* wait. */
5837 void
5838 OP_6_10 (SIM_DESC sd, SIM_CPU *cpu)
5839 {
5840 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
5841 trace_output_void (sd);
5842 EXCEPTION (SIM_SIGTRAP);
5843 }
5844
5845 /* ewait. */
5846 void
5847 OP_7_10 (SIM_DESC sd, SIM_CPU *cpu)
5848 {
5849 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5850 SET_PSR_I (1);
5851 trace_output_void (sd);
5852 }
5853
5854 /* xorb. */
5855 void
5856 OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
5857 {
5858 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5859 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5860 tmp = a ^ b;
5861 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5862 trace_output_16 (sd, tmp);
5863 }
5864
5865 /* xorb. */
5866 void
5867 OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
5868 {
5869 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5870 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5871 tmp = a ^ b;
5872 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5873 trace_output_16 (sd, tmp);
5874 }
5875
5876 /* xorb. */
5877 void
5878 OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
5879 {
5880 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
5881 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5882 tmp = a ^ b;
5883 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5884 trace_output_16 (sd, tmp);
5885 }
5886
5887 /* xorw. */
5888 void
5889 OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
5890 {
5891 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
5892 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5893 tmp = a ^ b;
5894 SET_GPR (OP[1], tmp);
5895 trace_output_16 (sd, tmp);
5896 }
5897
5898 /* xorw. */
5899 void
5900 OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
5901 {
5902 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
5903 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5904 tmp = a ^ b;
5905 SET_GPR (OP[1], tmp);
5906 trace_output_16 (sd, tmp);
5907 }
5908
5909 /* xorw. */
5910 void
5911 OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
5912 {
5913 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
5914 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5915 tmp = a ^ b;
5916 SET_GPR (OP[1], tmp);
5917 trace_output_16 (sd, tmp);
5918 }
5919
5920 /*REVISIT FOR LPR/SPR . */
5921
5922 /* lpr. */
5923 void
5924 OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
5925 {
5926 uint16_t a = GPR (OP[0]);
5927 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5928 SET_CREG (OP[1], a);
5929 trace_output_16 (sd, a);
5930 }
5931
5932 /* lprd. */
5933 void
5934 OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
5935 {
5936 uint32_t a = GPR32 (OP[0]);
5937 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5938 SET_CREG (OP[1], a);
5939 trace_output_flag (sd);
5940 }
5941
5942 /* spr. */
5943 void
5944 OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
5945 {
5946 uint16_t a = CREG (OP[0]);
5947 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5948 SET_GPR (OP[1], a);
5949 trace_output_16 (sd, a);
5950 }
5951
5952 /* sprd. */
5953 void
5954 OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
5955 {
5956 uint32_t a = CREG (OP[0]);
5957 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
5958 SET_GPR32 (OP[1], a);
5959 trace_output_32 (sd, a);
5960 }
5961
5962 /* null. */
5963 void
5964 OP_0_20 (SIM_DESC sd, SIM_CPU *cpu)
5965 {
5966 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
5967 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0);
5968 }
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