]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/interp.c
5 #include "sim/callback.h"
9 #include "sim-options.h"
11 #include "gdb/sim-d10v.h"
12 #include "gdb/signals.h"
18 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
24 /* Set this to true to get the previous segment layout. */
26 int old_segment_mapping
;
28 unsigned long ins_type_counters
[ (int)INS_MAX
];
32 static long hash (long insn
, int format
);
33 static struct hash_entry
*lookup_hash (SIM_DESC
, SIM_CPU
*, uint32 ins
, int size
);
34 static void get_operands (struct simops
*s
, uint32 ins
);
35 static void do_long (SIM_DESC
, SIM_CPU
*, uint32 ins
);
36 static void do_2_short (SIM_DESC
, SIM_CPU
*, uint16 ins1
, uint16 ins2
, enum _leftright leftright
);
37 static void do_parallel (SIM_DESC
, SIM_CPU
*, uint16 ins1
, uint16 ins2
);
38 static char *add_commas (char *buf
, int sizeof_buf
, unsigned long value
);
39 static INLINE uint8
*map_memory (SIM_DESC
, SIM_CPU
*, unsigned phys_addr
);
44 struct hash_entry
*next
;
51 struct hash_entry hash_table
[MAX_HASH
+1];
54 hash (long insn
, int format
)
56 if (format
& LONG_OPCODE
)
57 return ((insn
& 0x3F000000) >> 24);
59 return((insn
& 0x7E00) >> 9);
62 INLINE
static struct hash_entry
*
63 lookup_hash (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 ins
, int size
)
68 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
70 h
= &hash_table
[(ins
& 0x7E00) >> 9];
72 while ((ins
& h
->mask
) != h
->opcode
|| h
->size
!= size
)
75 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGILL
);
82 get_operands (struct simops
*s
, uint32 ins
)
84 int i
, shift
, bits
, flags
;
86 for (i
=0; i
< s
->numops
; i
++)
88 shift
= s
->operands
[3*i
];
89 bits
= s
->operands
[3*i
+1];
90 flags
= s
->operands
[3*i
+2];
91 mask
= 0x7FFFFFFF >> (31 - bits
);
92 OP
[i
] = (ins
>> shift
) & mask
;
94 /* FIXME: for tracing, update values that need to be updated each
95 instruction decode cycle */
96 State
.trace
.psw
= PSW
;
100 do_long (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 ins
)
102 struct hash_entry
*h
;
104 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
105 sim_io_printf (sd
, "do_long 0x%x\n", ins
);
107 h
= lookup_hash (sd
, cpu
, ins
, 1);
110 get_operands (h
->ops
, ins
);
111 State
.ins_type
= INS_LONG
;
112 ins_type_counters
[ (int)State
.ins_type
]++;
113 (h
->ops
->func
) (sd
, cpu
);
117 do_2_short (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 ins1
, uint16 ins2
, enum _leftright leftright
)
119 struct hash_entry
*h
;
120 enum _ins_type first
, second
;
123 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
124 sim_io_printf (sd
, "do_2_short 0x%x (%s) -> 0x%x\n", ins1
,
125 leftright
? "left" : "right", ins2
);
128 if (leftright
== LEFT_FIRST
)
132 ins_type_counters
[ (int)INS_LEFTRIGHT
]++;
138 ins_type_counters
[ (int)INS_RIGHTLEFT
]++;
141 /* Issue the first instruction */
142 h
= lookup_hash (sd
, cpu
, ins1
, 0);
145 get_operands (h
->ops
, ins1
);
146 State
.ins_type
= first
;
147 ins_type_counters
[ (int)State
.ins_type
]++;
148 (h
->ops
->func
) (sd
, cpu
);
150 /* Issue the second instruction (if the PC hasn't changed) */
151 if (!State
.pc_changed
)
153 /* finish any existing instructions */
155 h
= lookup_hash (sd
, cpu
, ins2
, 0);
158 get_operands (h
->ops
, ins2
);
159 State
.ins_type
= second
;
160 ins_type_counters
[ (int)State
.ins_type
]++;
161 ins_type_counters
[ (int)INS_CYCLES
]++;
162 (h
->ops
->func
) (sd
, cpu
);
165 ins_type_counters
[ (int)INS_COND_JUMP
]++;
169 do_parallel (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 ins1
, uint16 ins2
)
171 struct hash_entry
*h1
, *h2
;
173 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
174 sim_io_printf (sd
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
176 ins_type_counters
[ (int)INS_PARALLEL
]++;
177 h1
= lookup_hash (sd
, cpu
, ins1
, 0);
180 h2
= lookup_hash (sd
, cpu
, ins2
, 0);
184 if (h1
->ops
->exec_type
== PARONLY
)
186 get_operands (h1
->ops
, ins1
);
187 State
.ins_type
= INS_LEFT_COND_TEST
;
188 ins_type_counters
[ (int)State
.ins_type
]++;
189 (h1
->ops
->func
) (sd
, cpu
);
192 ins_type_counters
[ (int)INS_COND_TRUE
]++;
193 get_operands (h2
->ops
, ins2
);
194 State
.ins_type
= INS_RIGHT_COND_EXE
;
195 ins_type_counters
[ (int)State
.ins_type
]++;
196 (h2
->ops
->func
) (sd
, cpu
);
199 ins_type_counters
[ (int)INS_COND_FALSE
]++;
201 else if (h2
->ops
->exec_type
== PARONLY
)
203 get_operands (h2
->ops
, ins2
);
204 State
.ins_type
= INS_RIGHT_COND_TEST
;
205 ins_type_counters
[ (int)State
.ins_type
]++;
206 (h2
->ops
->func
) (sd
, cpu
);
209 ins_type_counters
[ (int)INS_COND_TRUE
]++;
210 get_operands (h1
->ops
, ins1
);
211 State
.ins_type
= INS_LEFT_COND_EXE
;
212 ins_type_counters
[ (int)State
.ins_type
]++;
213 (h1
->ops
->func
) (sd
, cpu
);
216 ins_type_counters
[ (int)INS_COND_FALSE
]++;
220 get_operands (h1
->ops
, ins1
);
221 State
.ins_type
= INS_LEFT_PARALLEL
;
222 ins_type_counters
[ (int)State
.ins_type
]++;
223 (h1
->ops
->func
) (sd
, cpu
);
224 get_operands (h2
->ops
, ins2
);
225 State
.ins_type
= INS_RIGHT_PARALLEL
;
226 ins_type_counters
[ (int)State
.ins_type
]++;
227 (h2
->ops
->func
) (sd
, cpu
);
232 add_commas (char *buf
, int sizeof_buf
, unsigned long value
)
235 char *endbuf
= buf
+ sizeof_buf
- 1;
245 *--endbuf
= (value
% 10) + '0';
246 } while ((value
/= 10) != 0);
255 for (i
= 0; i
< IMEM_SEGMENTS
; i
++)
257 if (State
.mem
.insn
[i
])
258 free (State
.mem
.insn
[i
]);
260 for (i
= 0; i
< DMEM_SEGMENTS
; i
++)
262 if (State
.mem
.data
[i
])
263 free (State
.mem
.data
[i
]);
265 for (i
= 0; i
< UMEM_SEGMENTS
; i
++)
267 if (State
.mem
.unif
[i
])
268 free (State
.mem
.unif
[i
]);
270 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
272 State
.mem
.data
[0] = calloc (1, SEGMENT_SIZE
);
275 /* For tracing - leave info on last access around. */
276 static char *last_segname
= "invalid";
277 static char *last_from
= "invalid";
278 static char *last_to
= "invalid";
282 IMAP0_OFFSET
= 0xff00,
283 DMAP0_OFFSET
= 0xff08,
284 DMAP2_SHADDOW
= 0xff04,
285 DMAP2_OFFSET
= 0xff0c
289 set_dmap_register (SIM_DESC sd
, int reg_nr
, unsigned long value
)
291 uint8
*raw
= map_memory (sd
, NULL
, SIM_D10V_MEMORY_DATA
292 + DMAP0_OFFSET
+ 2 * reg_nr
);
293 WRITE_16 (raw
, value
);
295 if ((d10v_debug
& DEBUG_MEMORY
))
297 sim_io_printf (sd
, "mem: dmap%d=0x%04lx\n", reg_nr
, value
);
303 dmap_register (SIM_DESC sd
, SIM_CPU
*cpu
, void *regcache
, int reg_nr
)
305 uint8
*raw
= map_memory (sd
, cpu
, SIM_D10V_MEMORY_DATA
306 + DMAP0_OFFSET
+ 2 * reg_nr
);
307 return READ_16 (raw
);
311 set_imap_register (SIM_DESC sd
, int reg_nr
, unsigned long value
)
313 uint8
*raw
= map_memory (sd
, NULL
, SIM_D10V_MEMORY_DATA
314 + IMAP0_OFFSET
+ 2 * reg_nr
);
315 WRITE_16 (raw
, value
);
317 if ((d10v_debug
& DEBUG_MEMORY
))
319 sim_io_printf (sd
, "mem: imap%d=0x%04lx\n", reg_nr
, value
);
325 imap_register (SIM_DESC sd
, SIM_CPU
*cpu
, void *regcache
, int reg_nr
)
327 uint8
*raw
= map_memory (sd
, cpu
, SIM_D10V_MEMORY_DATA
328 + IMAP0_OFFSET
+ 2 * reg_nr
);
329 return READ_16 (raw
);
344 return HELD_SP (HELD_SPU_IDX
);
353 return HELD_SP (HELD_SPI_IDX
);
357 set_spi_register (unsigned long value
)
360 SET_GPR (SP_IDX
, value
);
361 SET_HELD_SP (HELD_SPI_IDX
, value
);
365 set_spu_register (unsigned long value
)
368 SET_GPR (SP_IDX
, value
);
369 SET_HELD_SP (HELD_SPU_IDX
, value
);
372 /* Given a virtual address in the DMAP address space, translate it
373 into a physical address. */
376 sim_d10v_translate_dmap_addr (SIM_DESC sd
,
378 unsigned long offset
,
382 unsigned long (*dmap_register
) (SIM_DESC
,
389 last_from
= "logical-data";
390 if (offset
>= DMAP_BLOCK_SIZE
* SIM_D10V_NR_DMAP_REGS
)
392 /* Logical address out side of data segments, not supported */
395 regno
= (offset
/ DMAP_BLOCK_SIZE
);
396 offset
= (offset
% DMAP_BLOCK_SIZE
);
397 if ((offset
% DMAP_BLOCK_SIZE
) + nr_bytes
> DMAP_BLOCK_SIZE
)
399 /* Don't cross a BLOCK boundary */
400 nr_bytes
= DMAP_BLOCK_SIZE
- (offset
% DMAP_BLOCK_SIZE
);
402 map
= dmap_register (sd
, cpu
, regcache
, regno
);
405 /* Always maps to data memory */
406 int iospi
= (offset
/ 0x1000) % 4;
407 int iosp
= (map
>> (4 * (3 - iospi
))) % 0x10;
408 last_to
= "io-space";
409 *phys
= (SIM_D10V_MEMORY_DATA
+ (iosp
* 0x10000) + 0xc000 + offset
);
413 int sp
= ((map
& 0x3000) >> 12);
414 int segno
= (map
& 0x3ff);
417 case 0: /* 00: Unified memory */
418 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
421 case 1: /* 01: Instruction Memory */
422 *phys
= SIM_D10V_MEMORY_INSN
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
423 last_to
= "chip-insn";
425 case 2: /* 10: Internal data memory */
426 *phys
= SIM_D10V_MEMORY_DATA
+ (segno
<< 16) + (regno
* DMAP_BLOCK_SIZE
) + offset
;
427 last_to
= "chip-data";
429 case 3: /* 11: Reserved */
436 /* Given a virtual address in the IMAP address space, translate it
437 into a physical address. */
440 sim_d10v_translate_imap_addr (SIM_DESC sd
,
442 unsigned long offset
,
446 unsigned long (*imap_register
) (SIM_DESC
,
455 last_from
= "logical-insn";
456 if (offset
>= (IMAP_BLOCK_SIZE
* SIM_D10V_NR_IMAP_REGS
))
458 /* Logical address outside of IMAP segments, not supported */
461 regno
= (offset
/ IMAP_BLOCK_SIZE
);
462 offset
= (offset
% IMAP_BLOCK_SIZE
);
463 if (offset
+ nr_bytes
> IMAP_BLOCK_SIZE
)
465 /* Don't cross a BLOCK boundary */
466 nr_bytes
= IMAP_BLOCK_SIZE
- offset
;
468 map
= imap_register (sd
, cpu
, regcache
, regno
);
469 sp
= (map
& 0x3000) >> 12;
470 segno
= (map
& 0x007f);
473 case 0: /* 00: unified memory */
474 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
<< 17) + offset
;
477 case 1: /* 01: instruction memory */
478 *phys
= SIM_D10V_MEMORY_INSN
+ (IMAP_BLOCK_SIZE
* regno
) + offset
;
479 last_to
= "chip-insn";
484 case 3: /* 11: for testing - instruction memory */
485 offset
= (offset
% 0x800);
486 *phys
= SIM_D10V_MEMORY_INSN
+ offset
;
487 if (offset
+ nr_bytes
> 0x800)
488 /* don't cross VM boundary */
489 nr_bytes
= 0x800 - offset
;
490 last_to
= "test-insn";
497 sim_d10v_translate_addr (SIM_DESC sd
,
499 unsigned long memaddr
,
501 unsigned long *targ_addr
,
503 unsigned long (*dmap_register
) (SIM_DESC
,
507 unsigned long (*imap_register
) (SIM_DESC
,
516 last_from
= "unknown";
519 seg
= (memaddr
>> 24);
520 off
= (memaddr
& 0xffffffL
);
522 /* However, if we've asked to use the previous generation of segment
523 mapping, rearrange the segments as follows. */
525 if (old_segment_mapping
)
529 case 0x00: /* DMAP translated memory */
532 case 0x01: /* IMAP translated memory */
535 case 0x10: /* On-chip data memory */
538 case 0x11: /* On-chip insn memory */
541 case 0x12: /* Unified memory */
549 case 0x00: /* Physical unified memory */
550 last_from
= "phys-unified";
552 phys
= SIM_D10V_MEMORY_UNIFIED
+ off
;
553 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
554 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
557 case 0x01: /* Physical instruction memory */
558 last_from
= "phys-insn";
559 last_to
= "chip-insn";
560 phys
= SIM_D10V_MEMORY_INSN
+ off
;
561 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
562 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
565 case 0x02: /* Physical data memory segment */
566 last_from
= "phys-data";
567 last_to
= "chip-data";
568 phys
= SIM_D10V_MEMORY_DATA
+ off
;
569 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
570 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
573 case 0x10: /* in logical data address segment */
574 nr_bytes
= sim_d10v_translate_dmap_addr (sd
, cpu
, off
, nr_bytes
, &phys
,
575 regcache
, dmap_register
);
578 case 0x11: /* in logical instruction address segment */
579 nr_bytes
= sim_d10v_translate_imap_addr (sd
, cpu
, off
, nr_bytes
, &phys
,
580 regcache
, imap_register
);
591 /* Return a pointer into the raw buffer designated by phys_addr. It
592 is assumed that the client has already ensured that the access
593 isn't going to cross a segment boundary. */
596 map_memory (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned phys_addr
)
601 int segment
= ((phys_addr
>> 24) & 0xff);
606 case 0x00: /* Unified memory */
608 memory
= &State
.mem
.unif
[(phys_addr
/ SEGMENT_SIZE
) % UMEM_SEGMENTS
];
609 last_segname
= "umem";
613 case 0x01: /* On-chip insn memory */
615 memory
= &State
.mem
.insn
[(phys_addr
/ SEGMENT_SIZE
) % IMEM_SEGMENTS
];
616 last_segname
= "imem";
620 case 0x02: /* On-chip data memory */
622 if ((phys_addr
& 0xff00) == 0xff00)
624 phys_addr
= (phys_addr
& 0xffff);
625 if (phys_addr
== DMAP2_SHADDOW
)
627 phys_addr
= DMAP2_OFFSET
;
628 last_segname
= "dmap";
631 last_segname
= "reg";
634 last_segname
= "dmem";
635 memory
= &State
.mem
.data
[(phys_addr
/ SEGMENT_SIZE
) % DMEM_SEGMENTS
];
641 last_segname
= "scrap";
642 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
646 *memory
= xcalloc (1, SEGMENT_SIZE
);
648 offset
= (phys_addr
% SEGMENT_SIZE
);
649 raw
= *memory
+ offset
;
653 /* Transfer data to/from simulated memory. Since a bug in either the
654 simulated program or in gdb or the simulator itself may cause a
655 bogus address to be passed in, we need to do some sanity checking
656 on addresses to make sure they are within bounds. When an address
657 fails the bounds check, treat it as a zero length read/write rather
658 than aborting the entire run. */
661 xfer_mem (SIM_DESC sd
,
663 unsigned char *buffer
,
670 phys_size
= sim_d10v_translate_addr (sd
, NULL
, virt
, size
, &phys
, NULL
,
671 dmap_register
, imap_register
);
675 memory
= map_memory (sd
, NULL
, phys
);
678 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
682 "sim_%s %d bytes: 0x%08" PRIxTA
" (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
683 write_p
? "write" : "read",
684 phys_size
, virt
, last_from
,
686 (long) memory
, last_segname
);
692 memcpy (memory
, buffer
, phys_size
);
696 memcpy (buffer
, memory
, phys_size
);
704 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
706 /* FIXME: this should be performing a virtual transfer */
707 /* FIXME: We cast the const away, but it's safe because xfer_mem only reads
708 when write_p==1. This is still ugly. */
709 return xfer_mem (sd
, addr
, (void *) buffer
, size
, 1);
713 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
715 /* FIXME: this should be performing a virtual transfer */
716 return xfer_mem (sd
, addr
, buffer
, size
, 0);
720 d10v_pc_get (sim_cpu
*cpu
)
726 d10v_pc_set (sim_cpu
*cpu
, sim_cia pc
)
728 SIM_DESC sd
= CPU_STATE (cpu
);
733 free_state (SIM_DESC sd
)
735 if (STATE_MODULES (sd
) != NULL
)
736 sim_module_uninstall (sd
);
737 sim_cpu_free_all (sd
);
741 static int d10v_reg_fetch (SIM_CPU
*, int, unsigned char *, int);
742 static int d10v_reg_store (SIM_CPU
*, int, unsigned char *, int);
745 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
746 struct bfd
*abfd
, char * const *argv
)
749 struct hash_entry
*h
;
750 static int init_p
= 0;
753 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
754 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
756 /* The cpu data is kept in a separately allocated chunk of memory. */
757 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
763 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
769 /* The parser will print an error message for us, so we silently return. */
770 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
776 /* Check for/establish the a reference program image. */
777 if (sim_analyze_program (sd
,
778 (STATE_PROG_ARGV (sd
) != NULL
779 ? *STATE_PROG_ARGV (sd
)
780 : NULL
), abfd
) != SIM_RC_OK
)
786 /* Configure/verify the target byte order and other runtime
787 configuration options. */
788 if (sim_config (sd
) != SIM_RC_OK
)
790 sim_module_uninstall (sd
);
794 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
796 /* Uninstall the modules to avoid memory leaks,
797 file descriptor leaks, etc. */
798 sim_module_uninstall (sd
);
802 /* CPU specific initialization. */
803 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
805 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
807 CPU_REG_FETCH (cpu
) = d10v_reg_fetch
;
808 CPU_REG_STORE (cpu
) = d10v_reg_store
;
809 CPU_PC_FETCH (cpu
) = d10v_pc_get
;
810 CPU_PC_STORE (cpu
) = d10v_pc_set
;
813 old_segment_mapping
= 0;
815 /* NOTE: This argument parsing is only effective when this function
816 is called by GDB. Standalone argument parsing is handled by
818 for (p
= argv
+ 1; *p
; ++p
)
820 if (strcmp (*p
, "-oldseg") == 0)
821 old_segment_mapping
= 1;
823 else if (strcmp (*p
, "-t") == 0)
825 else if (strncmp (*p
, "-t", 2) == 0)
826 d10v_debug
= atoi (*p
+ 2);
830 /* put all the opcodes in the hash table */
833 for (s
= Simops
; s
->func
; s
++)
835 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
837 /* go to the last entry in the chain */
843 h
->next
= (struct hash_entry
*) calloc(1,sizeof(struct hash_entry
));
845 perror ("malloc failure");
851 h
->opcode
= s
->opcode
;
852 h
->size
= s
->is_long
;
856 /* reset the processor state */
857 if (!State
.mem
.data
[0])
864 dmem_addr (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 offset
)
870 /* Note: DMEM address range is 0..0x10000. Calling code can compute
871 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
872 is uint16 this is modulo'ed onto 0x0e5d. */
874 phys_size
= sim_d10v_translate_dmap_addr (sd
, cpu
, offset
, 1, &phys
, NULL
,
877 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
878 mem
= map_memory (sd
, cpu
, phys
);
880 if ((d10v_debug
& DEBUG_MEMORY
))
884 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
886 phys
, phys_size
, last_to
,
887 (long) mem
, last_segname
);
894 imem_addr (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 offset
)
898 int phys_size
= sim_d10v_translate_imap_addr (sd
, cpu
, offset
, 1, &phys
, NULL
,
901 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
902 mem
= map_memory (sd
, cpu
, phys
);
904 if ((d10v_debug
& DEBUG_MEMORY
))
908 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
910 phys
, phys_size
, last_to
,
911 (long) mem
, last_segname
);
918 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
923 /* TODO: Unindent this block. */
925 iaddr
= imem_addr (sd
, cpu
, (uint32
)PC
<< 2);
927 inst
= get_longword( iaddr
);
929 State
.pc_changed
= 0;
930 ins_type_counters
[ (int)INS_CYCLES
]++;
932 switch (inst
& 0xC0000000)
935 /* long instruction */
936 do_long (sd
, cpu
, inst
& 0x3FFFFFFF);
940 do_2_short (sd
, cpu
, inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, RIGHT_FIRST
);
944 do_2_short (sd
, cpu
, (inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, LEFT_FIRST
);
947 do_parallel (sd
, cpu
, (inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
951 /* If the PC of the current instruction matches RPT_E then
952 schedule a branch to the loop start. If one of those
953 instructions happens to be a branch, than that instruction
955 if (!State
.pc_changed
)
957 if (PSW_RP
&& PC
== RPT_E
)
959 /* Note: The behavour of a branch instruction at RPT_E
960 is implementation dependant, this simulator takes the
961 branch. Branching to RPT_E is valid, the instruction
962 must be executed before the loop is taken. */
971 SET_RPT_C (RPT_C
- 1);
979 /* Check for a breakpoint trap on this instruction. This
980 overrides any pending branches or loops */
981 if (PSW_DB
&& PC
== IBA
)
985 SET_PSW (PSW
& PSW_SM_BIT
);
986 SET_PC (SDBT_VECTOR_START
);
989 /* Writeback all the DATA / PC changes */
995 sim_engine_run (SIM_DESC sd
,
996 int next_cpu_nr
, /* ignore */
997 int nr_cpus
, /* ignore */
1002 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1004 cpu
= STATE_CPU (sd
, 0);
1010 case GDB_SIGNAL_BUS
:
1013 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1014 JMP (AE_VECTOR_START
);
1017 case GDB_SIGNAL_ILL
:
1020 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1021 JMP (RIE_VECTOR_START
);
1025 /* just ignore it */
1031 step_once (sd
, cpu
);
1032 if (sim_events_tick (sd
))
1033 sim_events_process (sd
);
1038 sim_info (SIM_DESC sd
, int verbose
)
1045 unsigned long left
= ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_COND_EXE
];
1046 unsigned long left_nops
= ins_type_counters
[ (int)INS_LEFT_NOPS
];
1047 unsigned long left_parallel
= ins_type_counters
[ (int)INS_LEFT_PARALLEL
];
1048 unsigned long left_cond
= ins_type_counters
[ (int)INS_LEFT_COND_TEST
];
1049 unsigned long left_total
= left
+ left_parallel
+ left_cond
+ left_nops
;
1051 unsigned long right
= ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_COND_EXE
];
1052 unsigned long right_nops
= ins_type_counters
[ (int)INS_RIGHT_NOPS
];
1053 unsigned long right_parallel
= ins_type_counters
[ (int)INS_RIGHT_PARALLEL
];
1054 unsigned long right_cond
= ins_type_counters
[ (int)INS_RIGHT_COND_TEST
];
1055 unsigned long right_total
= right
+ right_parallel
+ right_cond
+ right_nops
;
1057 unsigned long unknown
= ins_type_counters
[ (int)INS_UNKNOWN
];
1058 unsigned long ins_long
= ins_type_counters
[ (int)INS_LONG
];
1059 unsigned long parallel
= ins_type_counters
[ (int)INS_PARALLEL
];
1060 unsigned long leftright
= ins_type_counters
[ (int)INS_LEFTRIGHT
];
1061 unsigned long rightleft
= ins_type_counters
[ (int)INS_RIGHTLEFT
];
1062 unsigned long cond_true
= ins_type_counters
[ (int)INS_COND_TRUE
];
1063 unsigned long cond_false
= ins_type_counters
[ (int)INS_COND_FALSE
];
1064 unsigned long cond_jump
= ins_type_counters
[ (int)INS_COND_JUMP
];
1065 unsigned long cycles
= ins_type_counters
[ (int)INS_CYCLES
];
1066 unsigned long total
= (unknown
+ left_total
+ right_total
+ ins_long
);
1068 int size
= strlen (add_commas (buf1
, sizeof (buf1
), total
));
1069 int parallel_size
= strlen (add_commas (buf1
, sizeof (buf1
),
1070 (left_parallel
> right_parallel
) ? left_parallel
: right_parallel
));
1071 int cond_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_cond
> right_cond
) ? left_cond
: right_cond
));
1072 int nop_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_nops
> right_nops
) ? left_nops
: right_nops
));
1073 int normal_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left
> right
) ? left
: right
));
1076 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1077 size
, add_commas (buf1
, sizeof (buf1
), left_total
),
1078 normal_size
, add_commas (buf2
, sizeof (buf2
), left
),
1079 parallel_size
, add_commas (buf3
, sizeof (buf3
), left_parallel
),
1080 cond_size
, add_commas (buf4
, sizeof (buf4
), left_cond
),
1081 nop_size
, add_commas (buf5
, sizeof (buf5
), left_nops
));
1084 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1085 size
, add_commas (buf1
, sizeof (buf1
), right_total
),
1086 normal_size
, add_commas (buf2
, sizeof (buf2
), right
),
1087 parallel_size
, add_commas (buf3
, sizeof (buf3
), right_parallel
),
1088 cond_size
, add_commas (buf4
, sizeof (buf4
), right_cond
),
1089 nop_size
, add_commas (buf5
, sizeof (buf5
), right_nops
));
1093 "executed %*s long instruction(s)\n",
1094 size
, add_commas (buf1
, sizeof (buf1
), ins_long
));
1098 "executed %*s parallel instruction(s)\n",
1099 size
, add_commas (buf1
, sizeof (buf1
), parallel
));
1103 "executed %*s instruction(s) encoded L->R\n",
1104 size
, add_commas (buf1
, sizeof (buf1
), leftright
));
1108 "executed %*s instruction(s) encoded R->L\n",
1109 size
, add_commas (buf1
, sizeof (buf1
), rightleft
));
1113 "executed %*s unknown instruction(s)\n",
1114 size
, add_commas (buf1
, sizeof (buf1
), unknown
));
1118 "executed %*s instruction(s) due to EXExxx condition being true\n",
1119 size
, add_commas (buf1
, sizeof (buf1
), cond_true
));
1123 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1124 size
, add_commas (buf1
, sizeof (buf1
), cond_false
));
1128 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1129 size
, add_commas (buf1
, sizeof (buf1
), cond_jump
));
1132 "executed %*s cycle(s)\n",
1133 size
, add_commas (buf1
, sizeof (buf1
), cycles
));
1136 "executed %*s total instructions\n",
1137 size
, add_commas (buf1
, sizeof (buf1
), total
));
1141 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
1142 char * const *argv
, char * const *env
)
1144 bfd_vma start_address
;
1146 /* Make sure we have the right structure for the following memset. */
1147 static_assert ((uintptr_t) &State
== (uintptr_t) &State
.regs
,
1148 "&State != &State.regs");
1150 /* Reset state from the regs field until the mem field. */
1151 memset (&State
, 0, (uintptr_t) &State
.mem
- (uintptr_t) &State
.regs
);
1153 /* There was a hack here to copy the values of argc and argv into r0
1154 and r1. The values were also saved into some high memory that
1155 won't be overwritten by the stack (0x7C00). The reason for doing
1156 this was to allow the 'run' program to accept arguments. Without
1157 the hack, this is not possible anymore. If the simulator is run
1158 from the debugger, arguments cannot be passed in, so this makes
1163 start_address
= bfd_get_start_address (abfd
);
1165 start_address
= 0xffc0 << 2;
1168 sim_io_printf (sd
, "sim_create_inferior: PC=0x%" BFD_VMA_FMT
"x\n",
1172 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1173 SET_CREG (PC_CR
, start_address
>> 2);
1176 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
1177 initializes imap0 and imap1 to 0x1000 as part of its ROM
1179 if (old_segment_mapping
)
1181 /* External memory startup. This is the HARD reset state. */
1182 set_imap_register (sd
, 0, 0x0000);
1183 set_imap_register (sd
, 1, 0x007f);
1184 set_dmap_register (sd
, 0, 0x2000);
1185 set_dmap_register (sd
, 1, 0x2000);
1186 set_dmap_register (sd
, 2, 0x0000); /* Old DMAP */
1187 set_dmap_register (sd
, 3, 0x0000);
1191 /* Internal memory startup. This is the ROM intialized state. */
1192 set_imap_register (sd
, 0, 0x1000);
1193 set_imap_register (sd
, 1, 0x1000);
1194 set_dmap_register (sd
, 0, 0x2000);
1195 set_dmap_register (sd
, 1, 0x2000);
1196 set_dmap_register (sd
, 2, 0x2000); /* DMAP2 initial internal value is
1197 0x2000 on the new board. */
1198 set_dmap_register (sd
, 3, 0x0000);
1206 d10v_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1208 SIM_DESC sd
= CPU_STATE (cpu
);
1210 switch ((enum sim_d10v_regs
) rn
)
1212 case SIM_D10V_R0_REGNUM
:
1213 case SIM_D10V_R1_REGNUM
:
1214 case SIM_D10V_R2_REGNUM
:
1215 case SIM_D10V_R3_REGNUM
:
1216 case SIM_D10V_R4_REGNUM
:
1217 case SIM_D10V_R5_REGNUM
:
1218 case SIM_D10V_R6_REGNUM
:
1219 case SIM_D10V_R7_REGNUM
:
1220 case SIM_D10V_R8_REGNUM
:
1221 case SIM_D10V_R9_REGNUM
:
1222 case SIM_D10V_R10_REGNUM
:
1223 case SIM_D10V_R11_REGNUM
:
1224 case SIM_D10V_R12_REGNUM
:
1225 case SIM_D10V_R13_REGNUM
:
1226 case SIM_D10V_R14_REGNUM
:
1227 case SIM_D10V_R15_REGNUM
:
1228 WRITE_16 (memory
, GPR (rn
- SIM_D10V_R0_REGNUM
));
1231 case SIM_D10V_CR0_REGNUM
:
1232 case SIM_D10V_CR1_REGNUM
:
1233 case SIM_D10V_CR2_REGNUM
:
1234 case SIM_D10V_CR3_REGNUM
:
1235 case SIM_D10V_CR4_REGNUM
:
1236 case SIM_D10V_CR5_REGNUM
:
1237 case SIM_D10V_CR6_REGNUM
:
1238 case SIM_D10V_CR7_REGNUM
:
1239 case SIM_D10V_CR8_REGNUM
:
1240 case SIM_D10V_CR9_REGNUM
:
1241 case SIM_D10V_CR10_REGNUM
:
1242 case SIM_D10V_CR11_REGNUM
:
1243 case SIM_D10V_CR12_REGNUM
:
1244 case SIM_D10V_CR13_REGNUM
:
1245 case SIM_D10V_CR14_REGNUM
:
1246 case SIM_D10V_CR15_REGNUM
:
1247 WRITE_16 (memory
, CREG (rn
- SIM_D10V_CR0_REGNUM
));
1250 case SIM_D10V_A0_REGNUM
:
1251 case SIM_D10V_A1_REGNUM
:
1252 WRITE_64 (memory
, ACC (rn
- SIM_D10V_A0_REGNUM
));
1255 case SIM_D10V_SPI_REGNUM
:
1256 /* PSW_SM indicates that the current SP is the USER
1258 WRITE_16 (memory
, spi_register ());
1261 case SIM_D10V_SPU_REGNUM
:
1262 /* PSW_SM indicates that the current SP is the USER
1264 WRITE_16 (memory
, spu_register ());
1267 case SIM_D10V_IMAP0_REGNUM
:
1268 case SIM_D10V_IMAP1_REGNUM
:
1269 WRITE_16 (memory
, imap_register (sd
, cpu
, NULL
, rn
- SIM_D10V_IMAP0_REGNUM
));
1272 case SIM_D10V_DMAP0_REGNUM
:
1273 case SIM_D10V_DMAP1_REGNUM
:
1274 case SIM_D10V_DMAP2_REGNUM
:
1275 case SIM_D10V_DMAP3_REGNUM
:
1276 WRITE_16 (memory
, dmap_register (sd
, cpu
, NULL
, rn
- SIM_D10V_DMAP0_REGNUM
));
1279 case SIM_D10V_TS2_DMAP_REGNUM
:
1290 d10v_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1292 SIM_DESC sd
= CPU_STATE (cpu
);
1294 switch ((enum sim_d10v_regs
) rn
)
1296 case SIM_D10V_R0_REGNUM
:
1297 case SIM_D10V_R1_REGNUM
:
1298 case SIM_D10V_R2_REGNUM
:
1299 case SIM_D10V_R3_REGNUM
:
1300 case SIM_D10V_R4_REGNUM
:
1301 case SIM_D10V_R5_REGNUM
:
1302 case SIM_D10V_R6_REGNUM
:
1303 case SIM_D10V_R7_REGNUM
:
1304 case SIM_D10V_R8_REGNUM
:
1305 case SIM_D10V_R9_REGNUM
:
1306 case SIM_D10V_R10_REGNUM
:
1307 case SIM_D10V_R11_REGNUM
:
1308 case SIM_D10V_R12_REGNUM
:
1309 case SIM_D10V_R13_REGNUM
:
1310 case SIM_D10V_R14_REGNUM
:
1311 case SIM_D10V_R15_REGNUM
:
1312 SET_GPR (rn
- SIM_D10V_R0_REGNUM
, READ_16 (memory
));
1315 case SIM_D10V_CR0_REGNUM
:
1316 case SIM_D10V_CR1_REGNUM
:
1317 case SIM_D10V_CR2_REGNUM
:
1318 case SIM_D10V_CR3_REGNUM
:
1319 case SIM_D10V_CR4_REGNUM
:
1320 case SIM_D10V_CR5_REGNUM
:
1321 case SIM_D10V_CR6_REGNUM
:
1322 case SIM_D10V_CR7_REGNUM
:
1323 case SIM_D10V_CR8_REGNUM
:
1324 case SIM_D10V_CR9_REGNUM
:
1325 case SIM_D10V_CR10_REGNUM
:
1326 case SIM_D10V_CR11_REGNUM
:
1327 case SIM_D10V_CR12_REGNUM
:
1328 case SIM_D10V_CR13_REGNUM
:
1329 case SIM_D10V_CR14_REGNUM
:
1330 case SIM_D10V_CR15_REGNUM
:
1331 SET_CREG (rn
- SIM_D10V_CR0_REGNUM
, READ_16 (memory
));
1334 case SIM_D10V_A0_REGNUM
:
1335 case SIM_D10V_A1_REGNUM
:
1336 SET_ACC (rn
- SIM_D10V_A0_REGNUM
, READ_64 (memory
) & MASK40
);
1339 case SIM_D10V_SPI_REGNUM
:
1340 /* PSW_SM indicates that the current SP is the USER
1342 set_spi_register (READ_16 (memory
));
1345 case SIM_D10V_SPU_REGNUM
:
1346 set_spu_register (READ_16 (memory
));
1349 case SIM_D10V_IMAP0_REGNUM
:
1350 case SIM_D10V_IMAP1_REGNUM
:
1351 set_imap_register (sd
, rn
- SIM_D10V_IMAP0_REGNUM
, READ_16(memory
));
1354 case SIM_D10V_DMAP0_REGNUM
:
1355 case SIM_D10V_DMAP1_REGNUM
:
1356 case SIM_D10V_DMAP2_REGNUM
:
1357 case SIM_D10V_DMAP3_REGNUM
:
1358 set_dmap_register (sd
, rn
- SIM_D10V_DMAP0_REGNUM
, READ_16(memory
));
1361 case SIM_D10V_TS2_DMAP_REGNUM
: