]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/interp.c
4 #include "gdb/callback.h"
5 #include "gdb/remote-sim.h"
8 #include "gdb/sim-d10v.h"
10 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
13 static SIM_OPEN_KIND sim_kind
;
16 /* Set this to true to get the previous segment layout. */
18 int old_segment_mapping
;
20 host_callback
*d10v_callback
;
21 unsigned long ins_type_counters
[ (int)INS_MAX
];
25 static int init_text_p
= 0;
26 /* non-zero if we opened prog_bfd */
27 static int prog_bfd_was_opened_p
;
33 static long hash
PARAMS ((long insn
, int format
));
34 static struct hash_entry
*lookup_hash
PARAMS ((uint32 ins
, int size
));
35 static void get_operands
PARAMS ((struct simops
*s
, uint32 ins
));
36 static void do_long
PARAMS ((uint32 ins
));
37 static void do_2_short
PARAMS ((uint16 ins1
, uint16 ins2
, enum _leftright leftright
));
38 static void do_parallel
PARAMS ((uint16 ins1
, uint16 ins2
));
39 static char *add_commas
PARAMS ((char *buf
, int sizeof_buf
, unsigned long value
));
40 extern void sim_set_profile
PARAMS ((int n
));
41 extern void sim_set_profile_size
PARAMS ((int n
));
42 static INLINE uint8
*map_memory (unsigned phys_addr
);
44 #ifdef NEED_UI_LOOP_HOOK
45 /* How often to run the ui_loop update, when in use */
46 #define UI_LOOP_POLL_INTERVAL 0x14000
48 /* Counter for the ui_loop_hook update */
49 static long ui_loop_hook_counter
= UI_LOOP_POLL_INTERVAL
;
51 /* Actual hook to call to run through gdb's gui event loop */
52 extern int (*ui_loop_hook
) PARAMS ((int signo
));
53 #endif /* NEED_UI_LOOP_HOOK */
56 #if defined(__GNUC__) && defined(__OPTIMIZE__)
57 #define INLINE __inline__
66 struct hash_entry
*next
;
73 struct hash_entry hash_table
[MAX_HASH
+1];
80 if (format
& LONG_OPCODE
)
81 return ((insn
& 0x3F000000) >> 24);
83 return((insn
& 0x7E00) >> 9);
86 INLINE
static struct hash_entry
*
87 lookup_hash (ins
, size
)
94 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
96 h
= &hash_table
[(ins
& 0x7E00) >> 9];
98 while ((ins
& h
->mask
) != h
->opcode
|| h
->size
!= size
)
102 State
.exception
= SIGILL
;
103 State
.pc_changed
= 1; /* Don't increment the PC. */
112 get_operands (struct simops
*s
, uint32 ins
)
114 int i
, shift
, bits
, flags
;
116 for (i
=0; i
< s
->numops
; i
++)
118 shift
= s
->operands
[3*i
];
119 bits
= s
->operands
[3*i
+1];
120 flags
= s
->operands
[3*i
+2];
121 mask
= 0x7FFFFFFF >> (31 - bits
);
122 OP
[i
] = (ins
>> shift
) & mask
;
124 /* FIXME: for tracing, update values that need to be updated each
125 instruction decode cycle */
126 State
.trace
.psw
= PSW
;
133 if (!init_text_p
&& prog_bfd
!= NULL
)
136 for (s
= prog_bfd
->sections
; s
; s
= s
->next
)
137 if (strcmp (bfd_get_section_name (prog_bfd
, s
), ".text") == 0)
140 text_start
= bfd_get_section_vma (prog_bfd
, s
);
141 text_end
= text_start
+ bfd_section_size (prog_bfd
, s
);
146 return (PC
<< 2) + text_start
;
153 struct hash_entry
*h
;
155 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
156 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_long 0x%x\n", ins
);
158 h
= lookup_hash (ins
, 1);
161 get_operands (h
->ops
, ins
);
162 State
.ins_type
= INS_LONG
;
163 ins_type_counters
[ (int)State
.ins_type
]++;
168 do_2_short (ins1
, ins2
, leftright
)
170 enum _leftright leftright
;
172 struct hash_entry
*h
;
173 enum _ins_type first
, second
;
176 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
177 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_2_short 0x%x (%s) -> 0x%x\n",
178 ins1
, (leftright
) ? "left" : "right", ins2
);
181 if (leftright
== LEFT_FIRST
)
185 ins_type_counters
[ (int)INS_LEFTRIGHT
]++;
191 ins_type_counters
[ (int)INS_RIGHTLEFT
]++;
194 /* Issue the first instruction */
195 h
= lookup_hash (ins1
, 0);
198 get_operands (h
->ops
, ins1
);
199 State
.ins_type
= first
;
200 ins_type_counters
[ (int)State
.ins_type
]++;
203 /* Issue the second instruction (if the PC hasn't changed) */
204 if (!State
.pc_changed
&& !State
.exception
)
206 /* finish any existing instructions */
208 h
= lookup_hash (ins2
, 0);
211 get_operands (h
->ops
, ins2
);
212 State
.ins_type
= second
;
213 ins_type_counters
[ (int)State
.ins_type
]++;
214 ins_type_counters
[ (int)INS_CYCLES
]++;
217 else if (!State
.exception
)
218 ins_type_counters
[ (int)INS_COND_JUMP
]++;
222 do_parallel (ins1
, ins2
)
225 struct hash_entry
*h1
, *h2
;
227 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
228 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
230 ins_type_counters
[ (int)INS_PARALLEL
]++;
231 h1
= lookup_hash (ins1
, 0);
234 h2
= lookup_hash (ins2
, 0);
238 if (h1
->ops
->exec_type
== PARONLY
)
240 get_operands (h1
->ops
, ins1
);
241 State
.ins_type
= INS_LEFT_COND_TEST
;
242 ins_type_counters
[ (int)State
.ins_type
]++;
246 ins_type_counters
[ (int)INS_COND_TRUE
]++;
247 get_operands (h2
->ops
, ins2
);
248 State
.ins_type
= INS_RIGHT_COND_EXE
;
249 ins_type_counters
[ (int)State
.ins_type
]++;
253 ins_type_counters
[ (int)INS_COND_FALSE
]++;
255 else if (h2
->ops
->exec_type
== PARONLY
)
257 get_operands (h2
->ops
, ins2
);
258 State
.ins_type
= INS_RIGHT_COND_TEST
;
259 ins_type_counters
[ (int)State
.ins_type
]++;
263 ins_type_counters
[ (int)INS_COND_TRUE
]++;
264 get_operands (h1
->ops
, ins1
);
265 State
.ins_type
= INS_LEFT_COND_EXE
;
266 ins_type_counters
[ (int)State
.ins_type
]++;
270 ins_type_counters
[ (int)INS_COND_FALSE
]++;
274 get_operands (h1
->ops
, ins1
);
275 State
.ins_type
= INS_LEFT_PARALLEL
;
276 ins_type_counters
[ (int)State
.ins_type
]++;
278 if (!State
.exception
)
280 get_operands (h2
->ops
, ins2
);
281 State
.ins_type
= INS_RIGHT_PARALLEL
;
282 ins_type_counters
[ (int)State
.ins_type
]++;
289 add_commas(buf
, sizeof_buf
, value
)
295 char *endbuf
= buf
+ sizeof_buf
- 1;
305 *--endbuf
= (value
% 10) + '0';
306 } while ((value
/= 10) != 0);
317 for (i
= 0; i
< IMEM_SEGMENTS
; i
++)
319 if (State
.mem
.insn
[i
])
320 free (State
.mem
.insn
[i
]);
322 for (i
= 0; i
< DMEM_SEGMENTS
; i
++)
324 if (State
.mem
.data
[i
])
325 free (State
.mem
.data
[i
]);
327 for (i
= 0; i
< UMEM_SEGMENTS
; i
++)
329 if (State
.mem
.unif
[i
])
330 free (State
.mem
.unif
[i
]);
332 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
334 State
.mem
.data
[0] = calloc (1, SEGMENT_SIZE
);
337 /* For tracing - leave info on last access around. */
338 static char *last_segname
= "invalid";
339 static char *last_from
= "invalid";
340 static char *last_to
= "invalid";
344 IMAP0_OFFSET
= 0xff00,
345 DMAP0_OFFSET
= 0xff08,
346 DMAP2_SHADDOW
= 0xff04,
347 DMAP2_OFFSET
= 0xff0c
351 set_dmap_register (int reg_nr
, unsigned long value
)
353 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
354 + DMAP0_OFFSET
+ 2 * reg_nr
);
355 WRITE_16 (raw
, value
);
357 if ((d10v_debug
& DEBUG_MEMORY
))
359 (*d10v_callback
->printf_filtered
)
360 (d10v_callback
, "mem: dmap%d=0x%04lx\n", reg_nr
, value
);
366 dmap_register (void *regcache
, int reg_nr
)
368 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
369 + DMAP0_OFFSET
+ 2 * reg_nr
);
370 return READ_16 (raw
);
374 set_imap_register (int reg_nr
, unsigned long value
)
376 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
377 + IMAP0_OFFSET
+ 2 * reg_nr
);
378 WRITE_16 (raw
, value
);
380 if ((d10v_debug
& DEBUG_MEMORY
))
382 (*d10v_callback
->printf_filtered
)
383 (d10v_callback
, "mem: imap%d=0x%04lx\n", reg_nr
, value
);
389 imap_register (void *regcache
, int reg_nr
)
391 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
392 + IMAP0_OFFSET
+ 2 * reg_nr
);
393 return READ_16 (raw
);
408 return HELD_SP (HELD_SPU_IDX
);
417 return HELD_SP (HELD_SPI_IDX
);
421 set_spi_register (unsigned long value
)
424 SET_GPR (SP_IDX
, value
);
425 SET_HELD_SP (HELD_SPI_IDX
, value
);
429 set_spu_register (unsigned long value
)
432 SET_GPR (SP_IDX
, value
);
433 SET_HELD_SP (HELD_SPU_IDX
, value
);
436 /* Given a virtual address in the DMAP address space, translate it
437 into a physical address. */
440 sim_d10v_translate_dmap_addr (unsigned long offset
,
444 unsigned long (*dmap_register
) (void *regcache
,
449 last_from
= "logical-data";
450 if (offset
>= DMAP_BLOCK_SIZE
* SIM_D10V_NR_DMAP_REGS
)
452 /* Logical address out side of data segments, not supported */
455 regno
= (offset
/ DMAP_BLOCK_SIZE
);
456 offset
= (offset
% DMAP_BLOCK_SIZE
);
457 if ((offset
% DMAP_BLOCK_SIZE
) + nr_bytes
> DMAP_BLOCK_SIZE
)
459 /* Don't cross a BLOCK boundary */
460 nr_bytes
= DMAP_BLOCK_SIZE
- (offset
% DMAP_BLOCK_SIZE
);
462 map
= dmap_register (regcache
, regno
);
465 /* Always maps to data memory */
466 int iospi
= (offset
/ 0x1000) % 4;
467 int iosp
= (map
>> (4 * (3 - iospi
))) % 0x10;
468 last_to
= "io-space";
469 *phys
= (SIM_D10V_MEMORY_DATA
+ (iosp
* 0x10000) + 0xc000 + offset
);
473 int sp
= ((map
& 0x3000) >> 12);
474 int segno
= (map
& 0x3ff);
477 case 0: /* 00: Unified memory */
478 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
481 case 1: /* 01: Instruction Memory */
482 *phys
= SIM_D10V_MEMORY_INSN
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
483 last_to
= "chip-insn";
485 case 2: /* 10: Internal data memory */
486 *phys
= SIM_D10V_MEMORY_DATA
+ (segno
<< 16) + (regno
* DMAP_BLOCK_SIZE
) + offset
;
487 last_to
= "chip-data";
489 case 3: /* 11: Reserved */
496 /* Given a virtual address in the IMAP address space, translate it
497 into a physical address. */
500 sim_d10v_translate_imap_addr (unsigned long offset
,
504 unsigned long (*imap_register
) (void *regcache
,
511 last_from
= "logical-insn";
512 if (offset
>= (IMAP_BLOCK_SIZE
* SIM_D10V_NR_IMAP_REGS
))
514 /* Logical address outside of IMAP segments, not supported */
517 regno
= (offset
/ IMAP_BLOCK_SIZE
);
518 offset
= (offset
% IMAP_BLOCK_SIZE
);
519 if (offset
+ nr_bytes
> IMAP_BLOCK_SIZE
)
521 /* Don't cross a BLOCK boundary */
522 nr_bytes
= IMAP_BLOCK_SIZE
- offset
;
524 map
= imap_register (regcache
, regno
);
525 sp
= (map
& 0x3000) >> 12;
526 segno
= (map
& 0x007f);
529 case 0: /* 00: unified memory */
530 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
<< 17) + offset
;
533 case 1: /* 01: instruction memory */
534 *phys
= SIM_D10V_MEMORY_INSN
+ (IMAP_BLOCK_SIZE
* regno
) + offset
;
535 last_to
= "chip-insn";
540 case 3: /* 11: for testing - instruction memory */
541 offset
= (offset
% 0x800);
542 *phys
= SIM_D10V_MEMORY_INSN
+ offset
;
543 if (offset
+ nr_bytes
> 0x800)
544 /* don't cross VM boundary */
545 nr_bytes
= 0x800 - offset
;
546 last_to
= "test-insn";
553 sim_d10v_translate_addr (unsigned long memaddr
,
555 unsigned long *targ_addr
,
557 unsigned long (*dmap_register
) (void *regcache
,
559 unsigned long (*imap_register
) (void *regcache
,
566 last_from
= "unknown";
569 seg
= (memaddr
>> 24);
570 off
= (memaddr
& 0xffffffL
);
572 /* However, if we've asked to use the previous generation of segment
573 mapping, rearrange the segments as follows. */
575 if (old_segment_mapping
)
579 case 0x00: /* DMAP translated memory */
582 case 0x01: /* IMAP translated memory */
585 case 0x10: /* On-chip data memory */
588 case 0x11: /* On-chip insn memory */
591 case 0x12: /* Unified memory */
599 case 0x00: /* Physical unified memory */
600 last_from
= "phys-unified";
602 phys
= SIM_D10V_MEMORY_UNIFIED
+ off
;
603 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
604 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
607 case 0x01: /* Physical instruction memory */
608 last_from
= "phys-insn";
609 last_to
= "chip-insn";
610 phys
= SIM_D10V_MEMORY_INSN
+ off
;
611 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
612 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
615 case 0x02: /* Physical data memory segment */
616 last_from
= "phys-data";
617 last_to
= "chip-data";
618 phys
= SIM_D10V_MEMORY_DATA
+ off
;
619 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
620 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
623 case 0x10: /* in logical data address segment */
624 nr_bytes
= sim_d10v_translate_dmap_addr (off
, nr_bytes
, &phys
, regcache
,
628 case 0x11: /* in logical instruction address segment */
629 nr_bytes
= sim_d10v_translate_imap_addr (off
, nr_bytes
, &phys
, regcache
,
641 /* Return a pointer into the raw buffer designated by phys_addr. It
642 is assumed that the client has already ensured that the access
643 isn't going to cross a segment boundary. */
646 map_memory (unsigned phys_addr
)
651 int segment
= ((phys_addr
>> 24) & 0xff);
656 case 0x00: /* Unified memory */
658 memory
= &State
.mem
.unif
[(phys_addr
/ SEGMENT_SIZE
) % UMEM_SEGMENTS
];
659 last_segname
= "umem";
663 case 0x01: /* On-chip insn memory */
665 memory
= &State
.mem
.insn
[(phys_addr
/ SEGMENT_SIZE
) % IMEM_SEGMENTS
];
666 last_segname
= "imem";
670 case 0x02: /* On-chip data memory */
672 if ((phys_addr
& 0xff00) == 0xff00)
674 phys_addr
= (phys_addr
& 0xffff);
675 if (phys_addr
== DMAP2_SHADDOW
)
677 phys_addr
= DMAP2_OFFSET
;
678 last_segname
= "dmap";
681 last_segname
= "reg";
684 last_segname
= "dmem";
685 memory
= &State
.mem
.data
[(phys_addr
/ SEGMENT_SIZE
) % DMEM_SEGMENTS
];
691 last_segname
= "scrap";
692 return State
.mem
.fault
;
697 *memory
= calloc (1, SEGMENT_SIZE
);
700 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Malloc failed.\n");
701 return State
.mem
.fault
;
705 offset
= (phys_addr
% SEGMENT_SIZE
);
706 raw
= *memory
+ offset
;
710 /* Transfer data to/from simulated memory. Since a bug in either the
711 simulated program or in gdb or the simulator itself may cause a
712 bogus address to be passed in, we need to do some sanity checking
713 on addresses to make sure they are within bounds. When an address
714 fails the bounds check, treat it as a zero length read/write rather
715 than aborting the entire run. */
718 xfer_mem (SIM_ADDR virt
,
719 unsigned char *buffer
,
726 phys_size
= sim_d10v_translate_addr (virt
, size
, &phys
, NULL
,
727 dmap_register
, imap_register
);
731 memory
= map_memory (phys
);
734 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
736 (*d10v_callback
->printf_filtered
)
738 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
739 (write_p
? "write" : "read"),
740 phys_size
, virt
, last_from
,
742 (long) memory
, last_segname
);
748 memcpy (memory
, buffer
, phys_size
);
752 memcpy (buffer
, memory
, phys_size
);
760 sim_write (sd
, addr
, buffer
, size
)
763 unsigned char *buffer
;
766 /* FIXME: this should be performing a virtual transfer */
767 return xfer_mem( addr
, buffer
, size
, 1);
771 sim_read (sd
, addr
, buffer
, size
)
774 unsigned char *buffer
;
777 /* FIXME: this should be performing a virtual transfer */
778 return xfer_mem( addr
, buffer
, size
, 0);
783 sim_open (kind
, callback
, abfd
, argv
)
785 host_callback
*callback
;
790 struct hash_entry
*h
;
791 static int init_p
= 0;
795 d10v_callback
= callback
;
797 old_segment_mapping
= 0;
799 /* NOTE: This argument parsing is only effective when this function
800 is called by GDB. Standalone argument parsing is handled by
802 for (p
= argv
+ 1; *p
; ++p
)
804 if (strcmp (*p
, "-oldseg") == 0)
805 old_segment_mapping
= 1;
807 else if (strcmp (*p
, "-t") == 0)
809 else if (strncmp (*p
, "-t", 2) == 0)
810 d10v_debug
= atoi (*p
+ 2);
813 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: unsupported option(s): %s\n",*p
);
816 /* put all the opcodes in the hash table */
819 for (s
= Simops
; s
->func
; s
++)
821 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
823 /* go to the last entry in the chain */
829 h
->next
= (struct hash_entry
*) calloc(1,sizeof(struct hash_entry
));
831 perror ("malloc failure");
837 h
->opcode
= s
->opcode
;
838 h
->size
= s
->is_long
;
842 /* reset the processor state */
843 if (!State
.mem
.data
[0])
845 sim_create_inferior ((SIM_DESC
) 1, NULL
, NULL
, NULL
);
847 /* Fudge our descriptor. */
853 sim_close (sd
, quitting
)
857 if (prog_bfd
!= NULL
&& prog_bfd_was_opened_p
)
859 bfd_close (prog_bfd
);
861 prog_bfd_was_opened_p
= 0;
869 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_set_profile %d\n",n
);
873 sim_set_profile_size (n
)
876 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_set_profile_size %d\n",n
);
880 dmem_addr (uint16 offset
)
886 /* Note: DMEM address range is 0..0x10000. Calling code can compute
887 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
888 is uint16 this is modulo'ed onto 0x0e5d. */
890 phys_size
= sim_d10v_translate_dmap_addr (offset
, 1, &phys
, NULL
,
894 mem
= State
.mem
.fault
;
897 mem
= map_memory (phys
);
899 if ((d10v_debug
& DEBUG_MEMORY
))
901 (*d10v_callback
->printf_filtered
)
903 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
905 phys
, phys_size
, last_to
,
906 (long) mem
, last_segname
);
913 imem_addr (uint32 offset
)
917 int phys_size
= sim_d10v_translate_imap_addr (offset
, 1, &phys
, NULL
,
921 return State
.mem
.fault
;
923 mem
= map_memory (phys
);
925 if ((d10v_debug
& DEBUG_MEMORY
))
927 (*d10v_callback
->printf_filtered
)
929 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
931 phys
, phys_size
, last_to
,
932 (long) mem
, last_segname
);
938 static int stop_simulator
= 0;
949 /* Run (or resume) the program. */
951 sim_resume (sd
, step
, siggnal
)
958 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
973 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
974 JMP (AE_VECTOR_START
);
980 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
981 JMP (RIE_VECTOR_START
);
991 iaddr
= imem_addr ((uint32
)PC
<< 2);
992 if (iaddr
== State
.mem
.fault
)
994 State
.exception
= SIGBUS
;
998 inst
= get_longword( iaddr
);
1000 State
.pc_changed
= 0;
1001 ins_type_counters
[ (int)INS_CYCLES
]++;
1003 switch (inst
& 0xC0000000)
1006 /* long instruction */
1007 do_long (inst
& 0x3FFFFFFF);
1011 do_2_short ( inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, RIGHT_FIRST
);
1015 do_2_short ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, LEFT_FIRST
);
1018 do_parallel ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
1022 /* If the PC of the current instruction matches RPT_E then
1023 schedule a branch to the loop start. If one of those
1024 instructions happens to be a branch, than that instruction
1026 if (!State
.pc_changed
)
1028 if (PSW_RP
&& PC
== RPT_E
)
1030 /* Note: The behavour of a branch instruction at RPT_E
1031 is implementation dependant, this simulator takes the
1032 branch. Branching to RPT_E is valid, the instruction
1033 must be executed before the loop is taken. */
1042 SET_RPT_C (RPT_C
- 1);
1050 /* Check for a breakpoint trap on this instruction. This
1051 overrides any pending branches or loops */
1052 if (PSW_DB
&& PC
== IBA
)
1056 SET_PSW (PSW
& PSW_SM_BIT
);
1057 SET_PC (SDBT_VECTOR_START
);
1060 /* Writeback all the DATA / PC changes */
1063 #ifdef NEED_UI_LOOP_HOOK
1064 if (ui_loop_hook
!= NULL
&& ui_loop_hook_counter
-- < 0)
1066 ui_loop_hook_counter
= UI_LOOP_POLL_INTERVAL
;
1069 #endif /* NEED_UI_LOOP_HOOK */
1071 while ( !State
.exception
&& !stop_simulator
);
1073 if (step
&& !State
.exception
)
1074 State
.exception
= SIGTRAP
;
1078 sim_set_trace (void)
1086 sim_info (sd
, verbose
)
1095 unsigned long left
= ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_COND_EXE
];
1096 unsigned long left_nops
= ins_type_counters
[ (int)INS_LEFT_NOPS
];
1097 unsigned long left_parallel
= ins_type_counters
[ (int)INS_LEFT_PARALLEL
];
1098 unsigned long left_cond
= ins_type_counters
[ (int)INS_LEFT_COND_TEST
];
1099 unsigned long left_total
= left
+ left_parallel
+ left_cond
+ left_nops
;
1101 unsigned long right
= ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_COND_EXE
];
1102 unsigned long right_nops
= ins_type_counters
[ (int)INS_RIGHT_NOPS
];
1103 unsigned long right_parallel
= ins_type_counters
[ (int)INS_RIGHT_PARALLEL
];
1104 unsigned long right_cond
= ins_type_counters
[ (int)INS_RIGHT_COND_TEST
];
1105 unsigned long right_total
= right
+ right_parallel
+ right_cond
+ right_nops
;
1107 unsigned long unknown
= ins_type_counters
[ (int)INS_UNKNOWN
];
1108 unsigned long ins_long
= ins_type_counters
[ (int)INS_LONG
];
1109 unsigned long parallel
= ins_type_counters
[ (int)INS_PARALLEL
];
1110 unsigned long leftright
= ins_type_counters
[ (int)INS_LEFTRIGHT
];
1111 unsigned long rightleft
= ins_type_counters
[ (int)INS_RIGHTLEFT
];
1112 unsigned long cond_true
= ins_type_counters
[ (int)INS_COND_TRUE
];
1113 unsigned long cond_false
= ins_type_counters
[ (int)INS_COND_FALSE
];
1114 unsigned long cond_jump
= ins_type_counters
[ (int)INS_COND_JUMP
];
1115 unsigned long cycles
= ins_type_counters
[ (int)INS_CYCLES
];
1116 unsigned long total
= (unknown
+ left_total
+ right_total
+ ins_long
);
1118 int size
= strlen (add_commas (buf1
, sizeof (buf1
), total
));
1119 int parallel_size
= strlen (add_commas (buf1
, sizeof (buf1
),
1120 (left_parallel
> right_parallel
) ? left_parallel
: right_parallel
));
1121 int cond_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_cond
> right_cond
) ? left_cond
: right_cond
));
1122 int nop_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_nops
> right_nops
) ? left_nops
: right_nops
));
1123 int normal_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left
> right
) ? left
: right
));
1125 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1126 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1127 size
, add_commas (buf1
, sizeof (buf1
), left_total
),
1128 normal_size
, add_commas (buf2
, sizeof (buf2
), left
),
1129 parallel_size
, add_commas (buf3
, sizeof (buf3
), left_parallel
),
1130 cond_size
, add_commas (buf4
, sizeof (buf4
), left_cond
),
1131 nop_size
, add_commas (buf5
, sizeof (buf5
), left_nops
));
1133 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1134 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1135 size
, add_commas (buf1
, sizeof (buf1
), right_total
),
1136 normal_size
, add_commas (buf2
, sizeof (buf2
), right
),
1137 parallel_size
, add_commas (buf3
, sizeof (buf3
), right_parallel
),
1138 cond_size
, add_commas (buf4
, sizeof (buf4
), right_cond
),
1139 nop_size
, add_commas (buf5
, sizeof (buf5
), right_nops
));
1142 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1143 "executed %*s long instruction(s)\n",
1144 size
, add_commas (buf1
, sizeof (buf1
), ins_long
));
1147 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1148 "executed %*s parallel instruction(s)\n",
1149 size
, add_commas (buf1
, sizeof (buf1
), parallel
));
1152 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1153 "executed %*s instruction(s) encoded L->R\n",
1154 size
, add_commas (buf1
, sizeof (buf1
), leftright
));
1157 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1158 "executed %*s instruction(s) encoded R->L\n",
1159 size
, add_commas (buf1
, sizeof (buf1
), rightleft
));
1162 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1163 "executed %*s unknown instruction(s)\n",
1164 size
, add_commas (buf1
, sizeof (buf1
), unknown
));
1167 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1168 "executed %*s instruction(s) due to EXExxx condition being true\n",
1169 size
, add_commas (buf1
, sizeof (buf1
), cond_true
));
1172 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1173 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1174 size
, add_commas (buf1
, sizeof (buf1
), cond_false
));
1177 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1178 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1179 size
, add_commas (buf1
, sizeof (buf1
), cond_jump
));
1181 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1182 "executed %*s cycle(s)\n",
1183 size
, add_commas (buf1
, sizeof (buf1
), cycles
));
1185 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1186 "executed %*s total instructions\n",
1187 size
, add_commas (buf1
, sizeof (buf1
), total
));
1191 sim_create_inferior (sd
, abfd
, argv
, env
)
1197 bfd_vma start_address
;
1199 /* reset all state information */
1200 memset (&State
.regs
, 0, (int)&State
.mem
- (int)&State
.regs
);
1202 /* There was a hack here to copy the values of argc and argv into r0
1203 and r1. The values were also saved into some high memory that
1204 won't be overwritten by the stack (0x7C00). The reason for doing
1205 this was to allow the 'run' program to accept arguments. Without
1206 the hack, this is not possible anymore. If the simulator is run
1207 from the debugger, arguments cannot be passed in, so this makes
1212 start_address
= bfd_get_start_address (abfd
);
1214 start_address
= 0xffc0 << 2;
1217 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_create_inferior: PC=0x%lx\n", (long) start_address
);
1219 SET_CREG (PC_CR
, start_address
>> 2);
1221 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
1222 initializes imap0 and imap1 to 0x1000 as part of its ROM
1224 if (old_segment_mapping
)
1226 /* External memory startup. This is the HARD reset state. */
1227 set_imap_register (0, 0x0000);
1228 set_imap_register (1, 0x007f);
1229 set_dmap_register (0, 0x2000);
1230 set_dmap_register (1, 0x2000);
1231 set_dmap_register (2, 0x0000); /* Old DMAP */
1232 set_dmap_register (3, 0x0000);
1236 /* Internal memory startup. This is the ROM intialized state. */
1237 set_imap_register (0, 0x1000);
1238 set_imap_register (1, 0x1000);
1239 set_dmap_register (0, 0x2000);
1240 set_dmap_register (1, 0x2000);
1241 set_dmap_register (2, 0x2000); /* DMAP2 initial internal value is
1242 0x2000 on the new board. */
1243 set_dmap_register (3, 0x0000);
1252 sim_set_callbacks (p
)
1259 sim_stop_reason (sd
, reason
, sigrc
)
1261 enum sim_stop
*reason
;
1264 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
1266 switch (State
.exception
)
1268 case SIG_D10V_STOP
: /* stop instruction */
1269 *reason
= sim_exited
;
1273 case SIG_D10V_EXIT
: /* exit trap */
1274 *reason
= sim_exited
;
1279 *reason
= sim_stopped
;
1287 default: /* some signal */
1288 *reason
= sim_stopped
;
1289 if (stop_simulator
&& !State
.exception
)
1292 *sigrc
= State
.exception
;
1300 sim_fetch_register (sd
, rn
, memory
, length
)
1303 unsigned char *memory
;
1307 switch ((enum sim_d10v_regs
) rn
)
1309 case SIM_D10V_R0_REGNUM
:
1310 case SIM_D10V_R1_REGNUM
:
1311 case SIM_D10V_R2_REGNUM
:
1312 case SIM_D10V_R3_REGNUM
:
1313 case SIM_D10V_R4_REGNUM
:
1314 case SIM_D10V_R5_REGNUM
:
1315 case SIM_D10V_R6_REGNUM
:
1316 case SIM_D10V_R7_REGNUM
:
1317 case SIM_D10V_R8_REGNUM
:
1318 case SIM_D10V_R9_REGNUM
:
1319 case SIM_D10V_R10_REGNUM
:
1320 case SIM_D10V_R11_REGNUM
:
1321 case SIM_D10V_R12_REGNUM
:
1322 case SIM_D10V_R13_REGNUM
:
1323 case SIM_D10V_R14_REGNUM
:
1324 case SIM_D10V_R15_REGNUM
:
1325 WRITE_16 (memory
, GPR (rn
- SIM_D10V_R0_REGNUM
));
1328 case SIM_D10V_CR0_REGNUM
:
1329 case SIM_D10V_CR1_REGNUM
:
1330 case SIM_D10V_CR2_REGNUM
:
1331 case SIM_D10V_CR3_REGNUM
:
1332 case SIM_D10V_CR4_REGNUM
:
1333 case SIM_D10V_CR5_REGNUM
:
1334 case SIM_D10V_CR6_REGNUM
:
1335 case SIM_D10V_CR7_REGNUM
:
1336 case SIM_D10V_CR8_REGNUM
:
1337 case SIM_D10V_CR9_REGNUM
:
1338 case SIM_D10V_CR10_REGNUM
:
1339 case SIM_D10V_CR11_REGNUM
:
1340 case SIM_D10V_CR12_REGNUM
:
1341 case SIM_D10V_CR13_REGNUM
:
1342 case SIM_D10V_CR14_REGNUM
:
1343 case SIM_D10V_CR15_REGNUM
:
1344 WRITE_16 (memory
, CREG (rn
- SIM_D10V_CR0_REGNUM
));
1347 case SIM_D10V_A0_REGNUM
:
1348 case SIM_D10V_A1_REGNUM
:
1349 WRITE_64 (memory
, ACC (rn
- SIM_D10V_A0_REGNUM
));
1352 case SIM_D10V_SPI_REGNUM
:
1353 /* PSW_SM indicates that the current SP is the USER
1355 WRITE_16 (memory
, spi_register ());
1358 case SIM_D10V_SPU_REGNUM
:
1359 /* PSW_SM indicates that the current SP is the USER
1361 WRITE_16 (memory
, spu_register ());
1364 case SIM_D10V_IMAP0_REGNUM
:
1365 case SIM_D10V_IMAP1_REGNUM
:
1366 WRITE_16 (memory
, imap_register (NULL
, rn
- SIM_D10V_IMAP0_REGNUM
));
1369 case SIM_D10V_DMAP0_REGNUM
:
1370 case SIM_D10V_DMAP1_REGNUM
:
1371 case SIM_D10V_DMAP2_REGNUM
:
1372 case SIM_D10V_DMAP3_REGNUM
:
1373 WRITE_16 (memory
, dmap_register (NULL
, rn
- SIM_D10V_DMAP0_REGNUM
));
1376 case SIM_D10V_TS2_DMAP_REGNUM
:
1387 sim_store_register (sd
, rn
, memory
, length
)
1390 unsigned char *memory
;
1394 switch ((enum sim_d10v_regs
) rn
)
1396 case SIM_D10V_R0_REGNUM
:
1397 case SIM_D10V_R1_REGNUM
:
1398 case SIM_D10V_R2_REGNUM
:
1399 case SIM_D10V_R3_REGNUM
:
1400 case SIM_D10V_R4_REGNUM
:
1401 case SIM_D10V_R5_REGNUM
:
1402 case SIM_D10V_R6_REGNUM
:
1403 case SIM_D10V_R7_REGNUM
:
1404 case SIM_D10V_R8_REGNUM
:
1405 case SIM_D10V_R9_REGNUM
:
1406 case SIM_D10V_R10_REGNUM
:
1407 case SIM_D10V_R11_REGNUM
:
1408 case SIM_D10V_R12_REGNUM
:
1409 case SIM_D10V_R13_REGNUM
:
1410 case SIM_D10V_R14_REGNUM
:
1411 case SIM_D10V_R15_REGNUM
:
1412 SET_GPR (rn
- SIM_D10V_R0_REGNUM
, READ_16 (memory
));
1415 case SIM_D10V_CR0_REGNUM
:
1416 case SIM_D10V_CR1_REGNUM
:
1417 case SIM_D10V_CR2_REGNUM
:
1418 case SIM_D10V_CR3_REGNUM
:
1419 case SIM_D10V_CR4_REGNUM
:
1420 case SIM_D10V_CR5_REGNUM
:
1421 case SIM_D10V_CR6_REGNUM
:
1422 case SIM_D10V_CR7_REGNUM
:
1423 case SIM_D10V_CR8_REGNUM
:
1424 case SIM_D10V_CR9_REGNUM
:
1425 case SIM_D10V_CR10_REGNUM
:
1426 case SIM_D10V_CR11_REGNUM
:
1427 case SIM_D10V_CR12_REGNUM
:
1428 case SIM_D10V_CR13_REGNUM
:
1429 case SIM_D10V_CR14_REGNUM
:
1430 case SIM_D10V_CR15_REGNUM
:
1431 SET_CREG (rn
- SIM_D10V_CR0_REGNUM
, READ_16 (memory
));
1434 case SIM_D10V_A0_REGNUM
:
1435 case SIM_D10V_A1_REGNUM
:
1436 SET_ACC (rn
- SIM_D10V_A0_REGNUM
, READ_64 (memory
) & MASK40
);
1439 case SIM_D10V_SPI_REGNUM
:
1440 /* PSW_SM indicates that the current SP is the USER
1442 set_spi_register (READ_16 (memory
));
1445 case SIM_D10V_SPU_REGNUM
:
1446 set_spu_register (READ_16 (memory
));
1449 case SIM_D10V_IMAP0_REGNUM
:
1450 case SIM_D10V_IMAP1_REGNUM
:
1451 set_imap_register (rn
- SIM_D10V_IMAP0_REGNUM
, READ_16(memory
));
1454 case SIM_D10V_DMAP0_REGNUM
:
1455 case SIM_D10V_DMAP1_REGNUM
:
1456 case SIM_D10V_DMAP2_REGNUM
:
1457 case SIM_D10V_DMAP3_REGNUM
:
1458 set_dmap_register (rn
- SIM_D10V_DMAP0_REGNUM
, READ_16(memory
));
1461 case SIM_D10V_TS2_DMAP_REGNUM
:
1474 sim_do_command (sd
, cmd
)
1478 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_do_command: %s\n",cmd
);
1482 sim_load (sd
, prog
, abfd
, from_tty
)
1488 extern bfd
*sim_load_file (); /* ??? Don't know where this should live. */
1490 if (prog_bfd
!= NULL
&& prog_bfd_was_opened_p
)
1492 bfd_close (prog_bfd
);
1493 prog_bfd_was_opened_p
= 0;
1495 prog_bfd
= sim_load_file (sd
, myname
, d10v_callback
, prog
, abfd
,
1496 sim_kind
== SIM_OPEN_DEBUG
,
1497 1/*LMA*/, sim_write
);
1498 if (prog_bfd
== NULL
)
1500 prog_bfd_was_opened_p
= abfd
== NULL
;