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[thirdparty/binutils-gdb.git] / sim / erc32 / erc32.c
1 /* This file is part of SIS (SPARC instruction simulator)
2
3 Copyright (C) 1995-2024 Free Software Foundation, Inc.
4 Contributed by Jiri Gaisler, European Space Agency
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
18
19 /* The control space devices */
20
21 /* This must come before any other includes. */
22 #include "defs.h"
23
24 #include <sys/types.h>
25 #include <stdio.h>
26 #include <string.h>
27 #ifdef HAVE_TERMIOS_H
28 #include <termios.h>
29 #endif
30 #include <sys/fcntl.h>
31 #include <sys/file.h>
32 #include <unistd.h>
33 #include "sis.h"
34 #include "sim-config.h"
35
36 extern int ctrl_c;
37 extern int32_t sis_verbose;
38 extern int32_t sparclite, sparclite_board;
39 extern int rom8,wrp,uben;
40 extern char uart_dev1[], uart_dev2[];
41
42 int dumbio = 0; /* normal, smart, terminal oriented IO by default */
43
44 /* MEC registers */
45 #define MEC_START 0x01f80000
46 #define MEC_END 0x01f80100
47
48 /* Memory exception waitstates */
49 #define MEM_EX_WS 1
50
51 /* ERC32 always adds one waitstate during RAM std */
52 #define STD_WS 1
53
54 #ifdef ERRINJ
55 extern int errmec;
56 #endif
57
58 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
59 #define MOK 0
60
61 /* MEC register addresses */
62
63 #define MEC_MCR 0x000
64 #define MEC_SFR 0x004
65 #define MEC_PWDR 0x008
66 #define MEC_MEMCFG 0x010
67 #define MEC_IOCR 0x014
68 #define MEC_WCR 0x018
69
70 #define MEC_MAR0 0x020
71 #define MEC_MAR1 0x024
72
73 #define MEC_SSA1 0x020
74 #define MEC_SEA1 0x024
75 #define MEC_SSA2 0x028
76 #define MEC_SEA2 0x02C
77 #define MEC_ISR 0x044
78 #define MEC_IPR 0x048
79 #define MEC_IMR 0x04C
80 #define MEC_ICR 0x050
81 #define MEC_IFR 0x054
82 #define MEC_WDOG 0x060
83 #define MEC_TRAPD 0x064
84 #define MEC_RTC_COUNTER 0x080
85 #define MEC_RTC_RELOAD 0x080
86 #define MEC_RTC_SCALER 0x084
87 #define MEC_GPT_COUNTER 0x088
88 #define MEC_GPT_RELOAD 0x088
89 #define MEC_GPT_SCALER 0x08C
90 #define MEC_TIMER_CTRL 0x098
91 #define MEC_SFSR 0x0A0
92 #define MEC_FFAR 0x0A4
93 #define MEC_ERSR 0x0B0
94 #define MEC_DBG 0x0C0
95 #define MEC_TCR 0x0D0
96
97 #define MEC_BRK 0x0C4
98 #define MEC_WPR 0x0C8
99
100 #define MEC_UARTA 0x0E0
101 #define MEC_UARTB 0x0E4
102 #define MEC_UART_CTRL 0x0E8
103 #define SIM_LOAD 0x0F0
104
105 /* Memory exception causes */
106 #define PROT_EXC 0x3
107 #define UIMP_ACC 0x4
108 #define MEC_ACC 0x6
109 #define WATCH_EXC 0xa
110 #define BREAK_EXC 0xb
111
112 /* Size of UART buffers (bytes) */
113 #define UARTBUF 1024
114
115 /* Number of simulator ticks between flushing the UARTS. */
116 /* For good performance, keep above 1000 */
117 #define UART_FLUSH_TIME 3000
118
119 /* MEC timer control register bits */
120 #define TCR_GACR 1
121 #define TCR_GACL 2
122 #define TCR_GASE 4
123 #define TCR_GASL 8
124 #define TCR_TCRCR 0x100
125 #define TCR_TCRCL 0x200
126 #define TCR_TCRSE 0x400
127 #define TCR_TCRSL 0x800
128
129 /* New uart defines */
130 #define UART_TX_TIME 1000
131 #define UART_RX_TIME 1000
132 #define UARTA_DR 0x1
133 #define UARTA_SRE 0x2
134 #define UARTA_HRE 0x4
135 #define UARTA_OR 0x40
136 #define UARTA_CLR 0x80
137 #define UARTB_DR 0x10000
138 #define UARTB_SRE 0x20000
139 #define UARTB_HRE 0x40000
140 #define UARTB_OR 0x400000
141 #define UARTB_CLR 0x800000
142
143 #define UART_DR 0x100
144 #define UART_TSE 0x200
145 #define UART_THE 0x400
146
147 /* MEC registers */
148
149 static char fname[256];
150 static int32_t find = 0;
151 static uint32_t mec_ssa[2]; /* Write protection start address */
152 static uint32_t mec_sea[2]; /* Write protection end address */
153 static uint32_t mec_wpr[2]; /* Write protection control fields */
154 static uint32_t mec_sfsr;
155 static uint32_t mec_ffar;
156 static uint32_t mec_ipr;
157 static uint32_t mec_imr;
158 static uint32_t mec_isr;
159 static uint32_t mec_icr;
160 static uint32_t mec_ifr;
161 static uint32_t mec_mcr; /* MEC control register */
162 static uint32_t mec_memcfg; /* Memory control register */
163 static uint32_t mec_wcr; /* MEC waitstate register */
164 static uint32_t mec_iocr; /* MEC IO control register */
165 static uint32_t posted_irq;
166 static uint32_t mec_ersr; /* MEC error and status register */
167 static uint32_t mec_tcr; /* MEC test comtrol register */
168
169 static uint32_t rtc_counter;
170 static uint32_t rtc_reload;
171 static uint32_t rtc_scaler;
172 static uint32_t rtc_scaler_start;
173 static uint32_t rtc_enabled;
174 static uint32_t rtc_cr;
175 static uint32_t rtc_se;
176
177 static uint32_t gpt_counter;
178 static uint32_t gpt_reload;
179 static uint32_t gpt_scaler;
180 static uint32_t gpt_scaler_start;
181 static uint32_t gpt_enabled;
182 static uint32_t gpt_cr;
183 static uint32_t gpt_se;
184
185 static uint32_t wdog_scaler;
186 static uint32_t wdog_counter;
187 static uint32_t wdog_rst_delay;
188 static uint32_t wdog_rston;
189
190 enum wdog_type {
191 init, disabled, enabled, stopped
192 };
193
194 static enum wdog_type wdog_status;
195
196
197 /* ROM size 1024 Kbyte */
198 #define ROM_SZ 0x100000
199 #define ROM_MASK 0x0fffff
200
201 /* RAM size 4 Mbyte */
202 #define RAM_START 0x02000000
203 #define RAM_END 0x02400000
204 #define RAM_MASK 0x003fffff
205
206 /* SPARClite boards all seem to have RAM at the same place. */
207 #define RAM_START_SLITE 0x40000000
208 #define RAM_END_SLITE 0x40400000
209 #define RAM_MASK_SLITE 0x003fffff
210
211 /* Memory support variables */
212
213 static uint32_t mem_ramr_ws; /* RAM read waitstates */
214 static uint32_t mem_ramw_ws; /* RAM write waitstates */
215 static uint32_t mem_romr_ws; /* ROM read waitstates */
216 static uint32_t mem_romw_ws; /* ROM write waitstates */
217 static uint32_t mem_ramstart; /* RAM start */
218 static uint32_t mem_ramend; /* RAM end */
219 static uint32_t mem_rammask; /* RAM address mask */
220 static uint32_t mem_ramsz; /* RAM size */
221 static uint32_t mem_romsz; /* ROM size */
222 static uint32_t mem_accprot; /* RAM write protection enabled */
223 static uint32_t mem_blockprot; /* RAM block write protection enabled */
224
225 static unsigned char romb[ROM_SZ];
226 static unsigned char ramb[RAM_END - RAM_START];
227
228
229 /* UART support variables */
230
231 static int32_t fd1, fd2; /* file descriptor for input file */
232 static int32_t Ucontrol; /* UART status register */
233 static unsigned char aq[UARTBUF], bq[UARTBUF];
234 static int32_t anum, aind = 0;
235 static int32_t bnum, bind = 0;
236 static char wbufa[UARTBUF], wbufb[UARTBUF];
237 static unsigned wnuma;
238 static unsigned wnumb;
239 static FILE *f1in, *f1out, *f2in, *f2out;
240 #ifdef HAVE_TERMIOS_H
241 static struct termios ioc1, ioc2, iocold1, iocold2;
242 #endif
243 static int f1open = 0, f2open = 0;
244
245 static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
246 static uint32_t uart_stat_reg;
247 static uint32_t uarta_data, uartb_data;
248
249 #ifdef ERA
250 int era = 0;
251 int erareg;
252 #endif
253
254 /* Forward declarations */
255
256 static void decode_ersr (void);
257 #ifdef ERRINJ
258 static void iucomperr (void);
259 #endif
260 static void mecparerror (void);
261 static void decode_memcfg (void);
262 static void decode_wcr (void);
263 static void decode_mcr (void);
264 static void close_port (void);
265 static void mec_reset (void);
266 static void mec_intack (int32_t level);
267 static void chk_irq (void);
268 static void mec_irq (int32_t level);
269 static void set_sfsr (uint32_t fault, uint32_t addr,
270 uint32_t asi, uint32_t read);
271 static int32_t mec_read (uint32_t addr, uint32_t asi, uint32_t *data);
272 static int mec_write (uint32_t addr, uint32_t data);
273 static void port_init (void);
274 static uint32_t read_uart (uint32_t addr);
275 static void write_uart (uint32_t addr, uint32_t data);
276 static void flush_uart (void);
277 static void uarta_tx (int32_t);
278 static void uartb_tx (int32_t);
279 static void uart_rx (int32_t);
280 static void uart_intr (int32_t);
281 static void uart_irq_start (void);
282 static void wdog_intr (int32_t);
283 static void wdog_start (void);
284 static void rtc_intr (int32_t);
285 static void rtc_start (void);
286 static uint32_t rtc_counter_read (void);
287 static void rtc_scaler_set (uint32_t val);
288 static void rtc_reload_set (uint32_t val);
289 static void gpt_intr (int32_t);
290 static void gpt_start (void);
291 static uint32_t gpt_counter_read (void);
292 static void gpt_scaler_set (uint32_t val);
293 static void gpt_reload_set (uint32_t val);
294 static void timer_ctrl (uint32_t val);
295 static void * get_mem_ptr (uint32_t addr, uint32_t size);
296 static void store_bytes (unsigned char *mem, uint32_t waddr,
297 uint32_t *data, int sz, int32_t *ws);
298
299 extern int ext_irl;
300
301
302 /* One-time init */
303
304 void
305 init_sim(void)
306 {
307 port_init();
308 }
309
310 /* Power-on reset init */
311
312 void
313 reset(void)
314 {
315 mec_reset();
316 uart_irq_start();
317 wdog_start();
318 }
319
320 static void
321 decode_ersr(void)
322 {
323 if (mec_ersr & 0x01) {
324 if (!(mec_mcr & 0x20)) {
325 if (mec_mcr & 0x40) {
326 sys_reset();
327 mec_ersr = 0x8000;
328 if (sis_verbose)
329 printf("Error manager reset - IU in error mode\n");
330 } else {
331 sys_halt();
332 mec_ersr |= 0x2000;
333 if (sis_verbose)
334 printf("Error manager halt - IU in error mode\n");
335 }
336 } else
337 mec_irq(1);
338 }
339 if (mec_ersr & 0x04) {
340 if (!(mec_mcr & 0x200)) {
341 if (mec_mcr & 0x400) {
342 sys_reset();
343 mec_ersr = 0x8000;
344 if (sis_verbose)
345 printf("Error manager reset - IU comparison error\n");
346 } else {
347 sys_halt();
348 mec_ersr |= 0x2000;
349 if (sis_verbose)
350 printf("Error manager halt - IU comparison error\n");
351 }
352 } else
353 mec_irq(1);
354 }
355 if (mec_ersr & 0x20) {
356 if (!(mec_mcr & 0x2000)) {
357 if (mec_mcr & 0x4000) {
358 sys_reset();
359 mec_ersr = 0x8000;
360 if (sis_verbose)
361 printf("Error manager reset - MEC hardware error\n");
362 } else {
363 sys_halt();
364 mec_ersr |= 0x2000;
365 if (sis_verbose)
366 printf("Error manager halt - MEC hardware error\n");
367 }
368 } else
369 mec_irq(1);
370 }
371 }
372
373 #ifdef ERRINJ
374 static void
375 iucomperr()
376 {
377 mec_ersr |= 0x04;
378 decode_ersr();
379 }
380 #endif
381
382 static void
383 mecparerror(void)
384 {
385 mec_ersr |= 0x20;
386 decode_ersr();
387 }
388
389
390 /* IU error mode manager */
391
392 void
393 error_mode(uint32_t pc)
394 {
395
396 mec_ersr |= 0x1;
397 decode_ersr();
398 }
399
400
401 /* Check memory settings */
402
403 static void
404 decode_memcfg(void)
405 {
406 if (rom8) mec_memcfg &= ~0x20000;
407 else mec_memcfg |= 0x20000;
408
409 mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
410 mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
411
412 if (sparclite_board) {
413 mem_ramstart = RAM_START_SLITE;
414 mem_ramend = RAM_END_SLITE;
415 mem_rammask = RAM_MASK_SLITE;
416 }
417 else {
418 mem_ramstart = RAM_START;
419 mem_ramend = RAM_END;
420 mem_rammask = RAM_MASK;
421 }
422 if (sis_verbose)
423 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
424 mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
425 }
426
427 static void
428 decode_wcr(void)
429 {
430 mem_ramr_ws = mec_wcr & 3;
431 mem_ramw_ws = (mec_wcr >> 2) & 3;
432 mem_romr_ws = (mec_wcr >> 4) & 0x0f;
433 if (rom8) {
434 if (mem_romr_ws > 0 ) mem_romr_ws--;
435 mem_romr_ws = 5 + (4*mem_romr_ws);
436 }
437 mem_romw_ws = (mec_wcr >> 8) & 0x0f;
438 if (sis_verbose)
439 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
440 mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
441 }
442
443 static void
444 decode_mcr(void)
445 {
446 mem_accprot = (mec_wpr[0] | mec_wpr[1]);
447 mem_blockprot = (mec_mcr >> 3) & 1;
448 if (sis_verbose && mem_accprot)
449 printf("Memory block write protection enabled\n");
450 if (mec_mcr & 0x08000) {
451 mec_ersr |= 0x20;
452 decode_ersr();
453 }
454 if (sis_verbose && (mec_mcr & 2))
455 printf("Software reset enabled\n");
456 if (sis_verbose && (mec_mcr & 1))
457 printf("Power-down mode enabled\n");
458 }
459
460 /* Flush ports when simulator stops */
461
462 void
463 sim_halt(void)
464 {
465 #ifdef FAST_UART
466 flush_uart();
467 #endif
468 }
469
470 int
471 sim_stop(SIM_DESC sd)
472 {
473 ctrl_c = 1;
474 return 1;
475 }
476
477 static void
478 close_port(void)
479 {
480 if (f1open && f1in != stdin)
481 fclose(f1in);
482 if (f2open && f2in != stdin)
483 fclose(f2in);
484 }
485
486 void
487 exit_sim(void)
488 {
489 close_port();
490 }
491
492 static void
493 mec_reset(void)
494 {
495 int i;
496
497 find = 0;
498 for (i = 0; i < 2; i++)
499 mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
500 mec_mcr = 0x01350014;
501 mec_iocr = 0;
502 mec_sfsr = 0x078;
503 mec_ffar = 0;
504 mec_ipr = 0;
505 mec_imr = 0x7ffe;
506 mec_isr = 0;
507 mec_icr = 0;
508 mec_ifr = 0;
509 mec_memcfg = 0x10000;
510 mec_wcr = -1;
511 mec_ersr = 0; /* MEC error and status register */
512 mec_tcr = 0; /* MEC test comtrol register */
513
514 decode_memcfg();
515 decode_wcr();
516 decode_mcr();
517
518 posted_irq = 0;
519 wnuma = wnumb = 0;
520 anum = aind = bnum = bind = 0;
521
522 uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
523 uarta_data = uartb_data = UART_THE | UART_TSE;
524
525 rtc_counter = 0xffffffff;
526 rtc_reload = 0xffffffff;
527 rtc_scaler = 0xff;
528 rtc_enabled = 0;
529 rtc_cr = 0;
530 rtc_se = 0;
531
532 gpt_counter = 0xffffffff;
533 gpt_reload = 0xffffffff;
534 gpt_scaler = 0xffff;
535 gpt_enabled = 0;
536 gpt_cr = 0;
537 gpt_se = 0;
538
539 wdog_scaler = 255;
540 wdog_rst_delay = 255;
541 wdog_counter = 0xffff;
542 wdog_rston = 0;
543 wdog_status = init;
544
545 #ifdef ERA
546 erareg = 0;
547 #endif
548
549 }
550
551
552
553 static void
554 mec_intack(int32_t level)
555 {
556 int irq_test;
557
558 if (sis_verbose)
559 printf("interrupt %d acknowledged\n", level);
560 irq_test = mec_tcr & 0x80000;
561 if ((irq_test) && (mec_ifr & (1 << level)))
562 mec_ifr &= ~(1 << level);
563 else
564 mec_ipr &= ~(1 << level);
565 chk_irq();
566 }
567
568 static void
569 chk_irq(void)
570 {
571 int32_t i;
572 uint32_t itmp;
573 int old_irl;
574
575 old_irl = ext_irl;
576 if (mec_tcr & 0x80000) itmp = mec_ifr;
577 else itmp = 0;
578 itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
579 ext_irl = 0;
580 if (itmp != 0) {
581 for (i = 15; i > 0; i--) {
582 if (((itmp >> i) & 1) != 0) {
583 if ((sis_verbose) && (i > old_irl))
584 printf("IU irl: %d\n", i);
585 ext_irl = i;
586 set_int(i, mec_intack, i);
587 break;
588 }
589 }
590 }
591 }
592
593 static void
594 mec_irq(int32_t level)
595 {
596 mec_ipr |= (1 << level);
597 chk_irq();
598 }
599
600 static void
601 set_sfsr(uint32_t fault, uint32_t addr, uint32_t asi, uint32_t read)
602 {
603 if ((asi == 0xa) || (asi == 0xb)) {
604 mec_ffar = addr;
605 mec_sfsr = (fault << 3) | (!read << 15);
606 mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
607 switch (asi) {
608 case 0xa:
609 mec_sfsr |= 0x0004;
610 break;
611 case 0xb:
612 mec_sfsr |= 0x1004;
613 break;
614 }
615 }
616 }
617
618 static int32_t
619 mec_read(uint32_t addr, uint32_t asi, uint32_t *data)
620 {
621
622 switch (addr & 0x0ff) {
623
624 case MEC_MCR: /* 0x00 */
625 *data = mec_mcr;
626 break;
627
628 case MEC_MEMCFG: /* 0x10 */
629 *data = mec_memcfg;
630 break;
631
632 case MEC_IOCR:
633 *data = mec_iocr; /* 0x14 */
634 break;
635
636 case MEC_SSA1: /* 0x20 */
637 *data = mec_ssa[0] | (mec_wpr[0] << 23);
638 break;
639 case MEC_SEA1: /* 0x24 */
640 *data = mec_sea[0];
641 break;
642 case MEC_SSA2: /* 0x28 */
643 *data = mec_ssa[1] | (mec_wpr[1] << 23);
644 break;
645 case MEC_SEA2: /* 0x2c */
646 *data = mec_sea[1];
647 break;
648
649 case MEC_ISR: /* 0x44 */
650 *data = mec_isr;
651 break;
652
653 case MEC_IPR: /* 0x48 */
654 *data = mec_ipr;
655 break;
656
657 case MEC_IMR: /* 0x4c */
658 *data = mec_imr;
659 break;
660
661 case MEC_IFR: /* 0x54 */
662 *data = mec_ifr;
663 break;
664
665 case MEC_RTC_COUNTER: /* 0x80 */
666 *data = rtc_counter_read();
667 break;
668 case MEC_RTC_SCALER: /* 0x84 */
669 if (rtc_enabled)
670 *data = rtc_scaler - (now() - rtc_scaler_start);
671 else
672 *data = rtc_scaler;
673 break;
674
675 case MEC_GPT_COUNTER: /* 0x88 */
676 *data = gpt_counter_read();
677 break;
678
679 case MEC_GPT_SCALER: /* 0x8c */
680 if (rtc_enabled)
681 *data = gpt_scaler - (now() - gpt_scaler_start);
682 else
683 *data = gpt_scaler;
684 break;
685
686
687 case MEC_SFSR: /* 0xA0 */
688 *data = mec_sfsr;
689 break;
690
691 case MEC_FFAR: /* 0xA4 */
692 *data = mec_ffar;
693 break;
694
695 case SIM_LOAD:
696 fname[find] = 0;
697 if (find == 0)
698 strcpy(fname, "simload");
699 find = bfd_load(fname);
700 if (find == -1)
701 *data = 0;
702 else
703 *data = 1;
704 find = 0;
705 break;
706
707 case MEC_ERSR: /* 0xB0 */
708 *data = mec_ersr;
709 break;
710
711 case MEC_TCR: /* 0xD0 */
712 *data = mec_tcr;
713 break;
714
715 case MEC_UARTA: /* 0xE0 */
716 case MEC_UARTB: /* 0xE4 */
717 if (asi != 0xb) {
718 set_sfsr(MEC_ACC, addr, asi, 1);
719 return 1;
720 }
721 *data = read_uart(addr);
722 break;
723
724 case MEC_UART_CTRL: /* 0xE8 */
725
726 *data = read_uart(addr);
727 break;
728
729 case 0xF4: /* simulator RAM size in bytes */
730 *data = 4096*1024;
731 break;
732
733 case 0xF8: /* simulator ROM size in bytes */
734 *data = 1024*1024;
735 break;
736
737 default:
738 set_sfsr(MEC_ACC, addr, asi, 1);
739 return 1;
740 break;
741 }
742 return MOK;
743 }
744
745 static int
746 mec_write(uint32_t addr, uint32_t data)
747 {
748 if (sis_verbose > 1)
749 printf("MEC write a: %08x, d: %08x\n",addr,data);
750 switch (addr & 0x0ff) {
751
752 case MEC_MCR:
753 mec_mcr = data;
754 decode_mcr();
755 if (mec_mcr & 0x08000) mecparerror();
756 break;
757
758 case MEC_SFR:
759 if (mec_mcr & 0x2) {
760 sys_reset();
761 mec_ersr = 0x4000;
762 if (sis_verbose)
763 printf(" Software reset issued\n");
764 }
765 break;
766
767 case MEC_IOCR:
768 mec_iocr = data;
769 if (mec_iocr & 0xC0C0C0C0) mecparerror();
770 break;
771
772 case MEC_SSA1: /* 0x20 */
773 if (data & 0xFE000000) mecparerror();
774 mec_ssa[0] = data & 0x7fffff;
775 mec_wpr[0] = (data >> 23) & 0x03;
776 mem_accprot = mec_wpr[0] || mec_wpr[1];
777 if (sis_verbose && mec_wpr[0])
778 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
779 mec_ssa[0] << 2, mec_sea[0] << 2);
780 break;
781 case MEC_SEA1: /* 0x24 */
782 if (data & 0xFF800000) mecparerror();
783 mec_sea[0] = data & 0x7fffff;
784 break;
785 case MEC_SSA2: /* 0x28 */
786 if (data & 0xFE000000) mecparerror();
787 mec_ssa[1] = data & 0x7fffff;
788 mec_wpr[1] = (data >> 23) & 0x03;
789 mem_accprot = mec_wpr[0] || mec_wpr[1];
790 if (sis_verbose && mec_wpr[1])
791 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
792 mec_ssa[1] << 2, mec_sea[1] << 2);
793 break;
794 case MEC_SEA2: /* 0x2c */
795 if (data & 0xFF800000) mecparerror();
796 mec_sea[1] = data & 0x7fffff;
797 break;
798
799 case MEC_UARTA:
800 case MEC_UARTB:
801 if (data & 0xFFFFFF00) mecparerror();
802 ATTRIBUTE_FALLTHROUGH;
803 case MEC_UART_CTRL:
804 if (data & 0xFF00FF00) mecparerror();
805 write_uart(addr, data);
806 break;
807
808 case MEC_GPT_RELOAD:
809 gpt_reload_set(data);
810 break;
811
812 case MEC_GPT_SCALER:
813 if (data & 0xFFFF0000) mecparerror();
814 gpt_scaler_set(data);
815 break;
816
817 case MEC_TIMER_CTRL:
818 if (data & 0xFFFFF0F0) mecparerror();
819 timer_ctrl(data);
820 break;
821
822 case MEC_RTC_RELOAD:
823 rtc_reload_set(data);
824 break;
825
826 case MEC_RTC_SCALER:
827 if (data & 0xFFFFFF00) mecparerror();
828 rtc_scaler_set(data);
829 break;
830
831 case MEC_SFSR: /* 0xA0 */
832 if (data & 0xFFFF0880) mecparerror();
833 mec_sfsr = 0x78;
834 break;
835
836 case MEC_ISR:
837 if (data & 0xFFFFE000) mecparerror();
838 mec_isr = data;
839 break;
840
841 case MEC_IMR: /* 0x4c */
842
843 if (data & 0xFFFF8001) mecparerror();
844 mec_imr = data & 0x7ffe;
845 chk_irq();
846 break;
847
848 case MEC_ICR: /* 0x50 */
849
850 if (data & 0xFFFF0001) mecparerror();
851 mec_ipr &= ~data & 0x0fffe;
852 chk_irq();
853 break;
854
855 case MEC_IFR: /* 0x54 */
856
857 if (mec_tcr & 0x080000) {
858 if (data & 0xFFFF0001) mecparerror();
859 mec_ifr = data & 0xfffe;
860 chk_irq();
861 }
862 break;
863 case SIM_LOAD:
864 fname[find++] = (char) data;
865 break;
866
867
868 case MEC_MEMCFG: /* 0x10 */
869 if (data & 0xC0E08000) mecparerror();
870 mec_memcfg = data;
871 decode_memcfg();
872 if (mec_memcfg & 0xc0e08000)
873 mecparerror();
874 break;
875
876 case MEC_WCR: /* 0x18 */
877 mec_wcr = data;
878 decode_wcr();
879 break;
880
881 case MEC_ERSR: /* 0xB0 */
882 if (mec_tcr & 0x100000)
883 if (data & 0xFFFFEFC0) mecparerror();
884 mec_ersr = data & 0x103f;
885 break;
886
887 case MEC_TCR: /* 0xD0 */
888 if (data & 0xFFE1FFC0) mecparerror();
889 mec_tcr = data & 0x1e003f;
890 break;
891
892 case MEC_WDOG: /* 0x60 */
893 wdog_scaler = (data >> 16) & 0x0ff;
894 wdog_counter = data & 0x0ffff;
895 wdog_rst_delay = data >> 24;
896 wdog_rston = 0;
897 if (wdog_status == stopped)
898 wdog_start();
899 wdog_status = enabled;
900 break;
901
902 case MEC_TRAPD: /* 0x64 */
903 if (wdog_status == init) {
904 wdog_status = disabled;
905 if (sis_verbose)
906 printf("Watchdog disabled\n");
907 }
908 break;
909
910 case MEC_PWDR:
911 if (mec_mcr & 1)
912 wait_for_irq();
913 break;
914
915 default:
916 set_sfsr(MEC_ACC, addr, 0xb, 0);
917 return 1;
918 break;
919 }
920 return MOK;
921 }
922
923
924 /* MEC UARTS */
925
926 static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
927
928 void
929 init_stdio(void)
930 {
931 if (dumbio)
932 return; /* do nothing */
933 #ifdef HAVE_TERMIOS_H
934 if (!ifd1)
935 tcsetattr(0, TCSANOW, &ioc1);
936 if (!ifd2)
937 tcsetattr(0, TCSANOW, &ioc2);
938 #endif
939 }
940
941 void
942 restore_stdio(void)
943 {
944 if (dumbio)
945 return; /* do nothing */
946 #ifdef HAVE_TERMIOS_H
947 if (!ifd1)
948 tcsetattr(0, TCSANOW, &iocold1);
949 if (!ifd2)
950 tcsetattr(0, TCSANOW, &iocold2);
951 #endif
952 }
953
954 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
955 ( dumbio \
956 ? (0) /* no bytes read, no delay */ \
957 : read( _fd_, _buf_, _len_ ) )
958
959
960 static void
961 port_init(void)
962 {
963
964 if (uben) {
965 f2in = stdin;
966 f1in = NULL;
967 f2out = stdout;
968 f1out = NULL;
969 } else {
970 f1in = stdin;
971 f2in = NULL;
972 f1out = stdout;
973 f2out = NULL;
974 }
975 if (uart_dev1[0] != 0) {
976 if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
977 printf("Warning, couldn't open output device %s\n", uart_dev1);
978 } else {
979 if (sis_verbose)
980 printf("serial port A on %s\n", uart_dev1);
981 f1in = f1out = fdopen(fd1, "r+");
982 setbuf(f1out, NULL);
983 f1open = 1;
984 }
985 }
986 if (f1in) ifd1 = fileno(f1in);
987 if (ifd1 == 0) {
988 if (sis_verbose)
989 printf("serial port A on stdin/stdout\n");
990 if (!dumbio) {
991 #ifdef HAVE_TERMIOS_H
992 tcgetattr(ifd1, &ioc1);
993 iocold1 = ioc1;
994 ioc1.c_lflag &= ~(ICANON | ECHO);
995 ioc1.c_cc[VMIN] = 0;
996 ioc1.c_cc[VTIME] = 0;
997 #endif
998 }
999 f1open = 1;
1000 }
1001
1002 if (f1out) {
1003 ofd1 = fileno(f1out);
1004 if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1005 }
1006
1007 if (uart_dev2[0] != 0) {
1008 if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1009 printf("Warning, couldn't open output device %s\n", uart_dev2);
1010 } else {
1011 if (sis_verbose)
1012 printf("serial port B on %s\n", uart_dev2);
1013 f2in = f2out = fdopen(fd2, "r+");
1014 setbuf(f2out, NULL);
1015 f2open = 1;
1016 }
1017 }
1018 if (f2in) ifd2 = fileno(f2in);
1019 if (ifd2 == 0) {
1020 if (sis_verbose)
1021 printf("serial port B on stdin/stdout\n");
1022 if (!dumbio) {
1023 #ifdef HAVE_TERMIOS_H
1024 tcgetattr(ifd2, &ioc2);
1025 iocold2 = ioc2;
1026 ioc2.c_lflag &= ~(ICANON | ECHO);
1027 ioc2.c_cc[VMIN] = 0;
1028 ioc2.c_cc[VTIME] = 0;
1029 #endif
1030 }
1031 f2open = 1;
1032 }
1033
1034 if (f2out) {
1035 ofd2 = fileno(f2out);
1036 if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1037 }
1038
1039 wnuma = wnumb = 0;
1040
1041 }
1042
1043 static uint32_t
1044 read_uart(uint32_t addr)
1045 {
1046 switch (addr & 0xff) {
1047
1048 case 0xE0: /* UART 1 */
1049 #ifndef _WIN32
1050 #ifdef FAST_UART
1051
1052 if (aind < anum) {
1053 if ((aind + 1) < anum)
1054 mec_irq(4);
1055 return (0x700 | (uint32_t) aq[aind++]);
1056 } else {
1057 if (f1open) {
1058 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1059 }
1060 if (anum > 0) {
1061 aind = 0;
1062 if ((aind + 1) < anum)
1063 mec_irq(4);
1064 return (0x700 | (uint32_t) aq[aind++]);
1065 } else {
1066 return (0x600 | (uint32_t) aq[aind]);
1067 }
1068
1069 }
1070 #else
1071 unsigned tmp = uarta_data;
1072 uarta_data &= ~UART_DR;
1073 uart_stat_reg &= ~UARTA_DR;
1074 return tmp;
1075 #endif
1076 #else
1077 return 0;
1078 #endif
1079 break;
1080
1081 case 0xE4: /* UART 2 */
1082 #ifndef _WIN32
1083 #ifdef FAST_UART
1084 if (bind < bnum) {
1085 if ((bind + 1) < bnum)
1086 mec_irq(5);
1087 return (0x700 | (uint32_t) bq[bind++]);
1088 } else {
1089 if (f2open) {
1090 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1091 }
1092 if (bnum > 0) {
1093 bind = 0;
1094 if ((bind + 1) < bnum)
1095 mec_irq(5);
1096 return (0x700 | (uint32_t) bq[bind++]);
1097 } else {
1098 return (0x600 | (uint32_t) bq[bind]);
1099 }
1100
1101 }
1102 #else
1103 unsigned tmp = uartb_data;
1104 uartb_data &= ~UART_DR;
1105 uart_stat_reg &= ~UARTB_DR;
1106 return tmp;
1107 #endif
1108 #else
1109 return 0;
1110 #endif
1111 break;
1112
1113 case 0xE8: /* UART status register */
1114 #ifndef _WIN32
1115 #ifdef FAST_UART
1116
1117 Ucontrol = 0;
1118 if (aind < anum) {
1119 Ucontrol |= 0x00000001;
1120 } else {
1121 if (f1open) {
1122 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1123 }
1124 if (anum > 0) {
1125 Ucontrol |= 0x00000001;
1126 aind = 0;
1127 mec_irq(4);
1128 }
1129 }
1130 if (bind < bnum) {
1131 Ucontrol |= 0x00010000;
1132 } else {
1133 if (f2open) {
1134 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1135 }
1136 if (bnum > 0) {
1137 Ucontrol |= 0x00010000;
1138 bind = 0;
1139 mec_irq(5);
1140 }
1141 }
1142
1143 Ucontrol |= 0x00060006;
1144 return Ucontrol;
1145 #else
1146 return uart_stat_reg;
1147 #endif
1148 #else
1149 return 0x00060006;
1150 #endif
1151 break;
1152 default:
1153 if (sis_verbose)
1154 printf("Read from unimplemented MEC register (%x)\n", addr);
1155
1156 }
1157 return 0;
1158 }
1159
1160 static void
1161 write_uart(uint32_t addr, uint32_t data)
1162 {
1163 unsigned char c;
1164
1165 c = (unsigned char) data;
1166 switch (addr & 0xff) {
1167
1168 case 0xE0: /* UART A */
1169 #ifdef FAST_UART
1170 if (f1open) {
1171 if (wnuma < UARTBUF)
1172 wbufa[wnuma++] = c;
1173 else {
1174 while (wnuma)
1175 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1176 wbufa[wnuma++] = c;
1177 }
1178 }
1179 mec_irq(4);
1180 #else
1181 if (uart_stat_reg & UARTA_SRE) {
1182 uarta_sreg = c;
1183 uart_stat_reg &= ~UARTA_SRE;
1184 event(uarta_tx, 0, UART_TX_TIME);
1185 } else {
1186 uarta_hreg = c;
1187 uart_stat_reg &= ~UARTA_HRE;
1188 }
1189 #endif
1190 break;
1191
1192 case 0xE4: /* UART B */
1193 #ifdef FAST_UART
1194 if (f2open) {
1195 if (wnumb < UARTBUF)
1196 wbufb[wnumb++] = c;
1197 else {
1198 while (wnumb)
1199 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1200 wbufb[wnumb++] = c;
1201 }
1202 }
1203 mec_irq(5);
1204 #else
1205 if (uart_stat_reg & UARTB_SRE) {
1206 uartb_sreg = c;
1207 uart_stat_reg &= ~UARTB_SRE;
1208 event(uartb_tx, 0, UART_TX_TIME);
1209 } else {
1210 uartb_hreg = c;
1211 uart_stat_reg &= ~UARTB_HRE;
1212 }
1213 #endif
1214 break;
1215 case 0xE8: /* UART status register */
1216 #ifndef FAST_UART
1217 if (data & UARTA_CLR) {
1218 uart_stat_reg &= 0xFFFF0000;
1219 uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1220 }
1221 if (data & UARTB_CLR) {
1222 uart_stat_reg &= 0x0000FFFF;
1223 uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1224 }
1225 #endif
1226 break;
1227 default:
1228 if (sis_verbose)
1229 printf("Write to unimplemented MEC register (%x)\n", addr);
1230
1231 }
1232 }
1233
1234 static void
1235 flush_uart(void)
1236 {
1237 while (wnuma && f1open)
1238 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1239 while (wnumb && f2open)
1240 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1241 }
1242
1243 ATTRIBUTE_UNUSED
1244 static void
1245 uarta_tx(int32_t arg ATTRIBUTE_UNUSED)
1246 {
1247
1248 while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1249 if (uart_stat_reg & UARTA_HRE) {
1250 uart_stat_reg |= UARTA_SRE;
1251 } else {
1252 uarta_sreg = uarta_hreg;
1253 uart_stat_reg |= UARTA_HRE;
1254 event(uarta_tx, 0, UART_TX_TIME);
1255 }
1256 mec_irq(4);
1257 }
1258
1259 ATTRIBUTE_UNUSED
1260 static void
1261 uartb_tx(int32_t arg ATTRIBUTE_UNUSED)
1262 {
1263 while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1264 if (uart_stat_reg & UARTB_HRE) {
1265 uart_stat_reg |= UARTB_SRE;
1266 } else {
1267 uartb_sreg = uartb_hreg;
1268 uart_stat_reg |= UARTB_HRE;
1269 event(uartb_tx, 0, UART_TX_TIME);
1270 }
1271 mec_irq(5);
1272 }
1273
1274 ATTRIBUTE_UNUSED
1275 static void
1276 uart_rx(int32_t arg ATTRIBUTE_UNUSED)
1277 {
1278 int32_t rsize;
1279 char rxd;
1280
1281
1282 rsize = 0;
1283 if (f1open)
1284 rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1285 if (rsize > 0) {
1286 uarta_data = UART_DR | rxd;
1287 if (uart_stat_reg & UARTA_HRE)
1288 uarta_data |= UART_THE;
1289 if (uart_stat_reg & UARTA_SRE)
1290 uarta_data |= UART_TSE;
1291 if (uart_stat_reg & UARTA_DR) {
1292 uart_stat_reg |= UARTA_OR;
1293 mec_irq(7); /* UART error interrupt */
1294 }
1295 uart_stat_reg |= UARTA_DR;
1296 mec_irq(4);
1297 }
1298 rsize = 0;
1299 if (f2open)
1300 rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1301 if (rsize) {
1302 uartb_data = UART_DR | rxd;
1303 if (uart_stat_reg & UARTB_HRE)
1304 uartb_data |= UART_THE;
1305 if (uart_stat_reg & UARTB_SRE)
1306 uartb_data |= UART_TSE;
1307 if (uart_stat_reg & UARTB_DR) {
1308 uart_stat_reg |= UARTB_OR;
1309 mec_irq(7); /* UART error interrupt */
1310 }
1311 uart_stat_reg |= UARTB_DR;
1312 mec_irq(5);
1313 }
1314 event(uart_rx, 0, UART_RX_TIME);
1315 }
1316
1317 static void
1318 uart_intr(int32_t arg ATTRIBUTE_UNUSED)
1319 {
1320 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1321 flush_uart(); /* Flush UART ports */
1322 event(uart_intr, 0, UART_FLUSH_TIME);
1323 }
1324
1325
1326 static void
1327 uart_irq_start(void)
1328 {
1329 #ifdef FAST_UART
1330 event(uart_intr, 0, UART_FLUSH_TIME);
1331 #else
1332 #ifndef _WIN32
1333 event(uart_rx, 0, UART_RX_TIME);
1334 #endif
1335 #endif
1336 }
1337
1338 /* Watch-dog */
1339
1340 static void
1341 wdog_intr(int32_t arg ATTRIBUTE_UNUSED)
1342 {
1343 if (wdog_status == disabled) {
1344 wdog_status = stopped;
1345 } else {
1346
1347 if (wdog_counter) {
1348 wdog_counter--;
1349 event(wdog_intr, 0, wdog_scaler + 1);
1350 } else {
1351 if (wdog_rston) {
1352 printf("Watchdog reset!\n");
1353 sys_reset();
1354 mec_ersr = 0xC000;
1355 } else {
1356 mec_irq(15);
1357 wdog_rston = 1;
1358 wdog_counter = wdog_rst_delay;
1359 event(wdog_intr, 0, wdog_scaler + 1);
1360 }
1361 }
1362 }
1363 }
1364
1365 static void
1366 wdog_start(void)
1367 {
1368 event(wdog_intr, 0, wdog_scaler + 1);
1369 if (sis_verbose)
1370 printf("Watchdog started, scaler = %d, counter = %d\n",
1371 wdog_scaler, wdog_counter);
1372 }
1373
1374
1375 /* MEC timers */
1376
1377
1378 static void
1379 rtc_intr(int32_t arg ATTRIBUTE_UNUSED)
1380 {
1381 if (rtc_counter == 0) {
1382
1383 mec_irq(13);
1384 if (rtc_cr)
1385 rtc_counter = rtc_reload;
1386 else
1387 rtc_se = 0;
1388 } else
1389 rtc_counter -= 1;
1390 if (rtc_se) {
1391 event(rtc_intr, 0, rtc_scaler + 1);
1392 rtc_scaler_start = now();
1393 rtc_enabled = 1;
1394 } else {
1395 if (sis_verbose)
1396 printf("RTC stopped\n\r");
1397 rtc_enabled = 0;
1398 }
1399 }
1400
1401 static void
1402 rtc_start(void)
1403 {
1404 if (sis_verbose)
1405 printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1406 event(rtc_intr, 0, rtc_scaler + 1);
1407 rtc_scaler_start = now();
1408 rtc_enabled = 1;
1409 }
1410
1411 static uint32_t
1412 rtc_counter_read(void)
1413 {
1414 return rtc_counter;
1415 }
1416
1417 static void
1418 rtc_scaler_set(uint32_t val)
1419 {
1420 rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
1421 }
1422
1423 static void
1424 rtc_reload_set(uint32_t val)
1425 {
1426 rtc_reload = val;
1427 }
1428
1429 static void
1430 gpt_intr(int32_t arg ATTRIBUTE_UNUSED)
1431 {
1432 if (gpt_counter == 0) {
1433 mec_irq(12);
1434 if (gpt_cr)
1435 gpt_counter = gpt_reload;
1436 else
1437 gpt_se = 0;
1438 } else
1439 gpt_counter -= 1;
1440 if (gpt_se) {
1441 event(gpt_intr, 0, gpt_scaler + 1);
1442 gpt_scaler_start = now();
1443 gpt_enabled = 1;
1444 } else {
1445 if (sis_verbose)
1446 printf("GPT stopped\n\r");
1447 gpt_enabled = 0;
1448 }
1449 }
1450
1451 static void
1452 gpt_start(void)
1453 {
1454 if (sis_verbose)
1455 printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1456 event(gpt_intr, 0, gpt_scaler + 1);
1457 gpt_scaler_start = now();
1458 gpt_enabled = 1;
1459 }
1460
1461 static uint32_t
1462 gpt_counter_read(void)
1463 {
1464 return gpt_counter;
1465 }
1466
1467 static void
1468 gpt_scaler_set(uint32_t val)
1469 {
1470 gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1471 }
1472
1473 static void
1474 gpt_reload_set(uint32_t val)
1475 {
1476 gpt_reload = val;
1477 }
1478
1479 static void
1480 timer_ctrl(uint32_t val)
1481 {
1482
1483 rtc_cr = ((val & TCR_TCRCR) != 0);
1484 if (val & TCR_TCRCL) {
1485 rtc_counter = rtc_reload;
1486 }
1487 if (val & TCR_TCRSL) {
1488 }
1489 rtc_se = ((val & TCR_TCRSE) != 0);
1490 if (rtc_se && (rtc_enabled == 0))
1491 rtc_start();
1492
1493 gpt_cr = (val & TCR_GACR);
1494 if (val & TCR_GACL) {
1495 gpt_counter = gpt_reload;
1496 }
1497 if (val & TCR_GACL) {
1498 }
1499 gpt_se = (val & TCR_GASE) >> 2;
1500 if (gpt_se && (gpt_enabled == 0))
1501 gpt_start();
1502 }
1503
1504 /* Store data in host byte order. MEM points to the beginning of the
1505 emulated memory; WADDR contains the index the emulated memory,
1506 DATA points to words in host byte order to be stored. SZ contains log(2)
1507 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1508 2 (one word), or 3 (two words); WS should return the number of
1509 wait-states. */
1510
1511 static void
1512 store_bytes (unsigned char *mem, uint32_t waddr, uint32_t *data, int32_t sz,
1513 int32_t *ws)
1514 {
1515 switch (sz) {
1516 case 0:
1517 waddr ^= EBT;
1518 mem[waddr] = *data & 0x0ff;
1519 *ws = mem_ramw_ws + 3;
1520 break;
1521 case 1:
1522 #ifdef HOST_LITTLE_ENDIAN
1523 waddr ^= 2;
1524 #endif
1525 memcpy (&mem[waddr], data, 2);
1526 *ws = mem_ramw_ws + 3;
1527 break;
1528 case 2:
1529 memcpy (&mem[waddr], data, 4);
1530 *ws = mem_ramw_ws;
1531 break;
1532 case 3:
1533 memcpy (&mem[waddr], data, 8);
1534 *ws = 2 * mem_ramw_ws + STD_WS;
1535 break;
1536 }
1537 }
1538
1539
1540 /* Memory emulation */
1541
1542 int
1543 memory_iread (uint32_t addr, uint32_t *data, uint32_t *ws)
1544 {
1545 uint32_t asi;
1546 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1547 memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
1548 *ws = mem_ramr_ws;
1549 return 0;
1550 } else if (addr < mem_romsz) {
1551 memcpy (data, &romb[addr & ~3], 4);
1552 *ws = mem_romr_ws;
1553 return 0;
1554 }
1555
1556 if (sis_verbose)
1557 printf ("Memory exception at %x (illegal address)\n", addr);
1558 if (sregs.psr & 0x080)
1559 asi = 9;
1560 else
1561 asi = 8;
1562 set_sfsr (UIMP_ACC, addr, asi, 1);
1563 *ws = MEM_EX_WS;
1564 return 1;
1565 }
1566
1567 int
1568 memory_read(int32_t asi, uint32_t addr, void *data, int32_t sz, int32_t *ws)
1569 {
1570 int32_t mexc;
1571
1572 #ifdef ERRINJ
1573 if (errmec) {
1574 if (sis_verbose)
1575 printf("Inserted MEC error %d\n",errmec);
1576 set_sfsr(errmec, addr, asi, 1);
1577 if (errmec == 5) mecparerror();
1578 if (errmec == 6) iucomperr();
1579 errmec = 0;
1580 return 1;
1581 }
1582 #endif
1583
1584 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1585 memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
1586 *ws = mem_ramr_ws;
1587 return 0;
1588 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1589 mexc = mec_read(addr, asi, data);
1590 if (mexc) {
1591 set_sfsr(MEC_ACC, addr, asi, 1);
1592 *ws = MEM_EX_WS;
1593 } else {
1594 *ws = 0;
1595 }
1596 return mexc;
1597
1598 #ifdef ERA
1599
1600 } else if (era) {
1601 if ((addr < 0x100000) ||
1602 ((addr>= 0x80000000) && (addr < 0x80100000))) {
1603 memcpy (data, &romb[addr & ROM_MASK & ~3], 4);
1604 *ws = 4;
1605 return 0;
1606 } else if ((addr >= 0x10000000) &&
1607 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1608 (mec_iocr & 0x10)) {
1609 memcpy (data, &erareg, 4);
1610 return 0;
1611 }
1612
1613 } else if (addr < mem_romsz) {
1614 memcpy (data, &romb[addr & ~3], 4);
1615 *ws = mem_romr_ws;
1616 return 0;
1617 #else
1618 } else if (addr < mem_romsz) {
1619 memcpy (data, &romb[addr & ~3], 4);
1620 *ws = mem_romr_ws;
1621 return 0;
1622 #endif
1623
1624 }
1625
1626 if (sis_verbose)
1627 printf ("Memory exception at %x (illegal address)\n", addr);
1628 set_sfsr(UIMP_ACC, addr, asi, 1);
1629 *ws = MEM_EX_WS;
1630 return 1;
1631 }
1632
1633 int
1634 memory_write(int32_t asi, uint32_t addr, uint32_t *data, int32_t sz, int32_t *ws)
1635 {
1636 uint32_t waddr;
1637 int32_t mexc;
1638 int i;
1639 int wphit[2];
1640
1641 #ifdef ERRINJ
1642 if (errmec) {
1643 if (sis_verbose)
1644 printf("Inserted MEC error %d\n",errmec);
1645 set_sfsr(errmec, addr, asi, 0);
1646 if (errmec == 5) mecparerror();
1647 if (errmec == 6) iucomperr();
1648 errmec = 0;
1649 return 1;
1650 }
1651 #endif
1652
1653 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1654 if (mem_accprot) {
1655
1656 waddr = (addr & 0x7fffff) >> 2;
1657 for (i = 0; i < 2; i++)
1658 wphit[i] =
1659 (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1660 ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1661 ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1662
1663 if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1664 ((!mem_blockprot) &&
1665 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1666 )) {
1667 if (sis_verbose)
1668 printf("Memory access protection error at 0x%08x\n", addr);
1669 set_sfsr(PROT_EXC, addr, asi, 0);
1670 *ws = MEM_EX_WS;
1671 return 1;
1672 }
1673 }
1674 waddr = addr & mem_rammask;
1675 store_bytes (ramb, waddr, data, sz, ws);
1676 return 0;
1677 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1678 if ((sz != 2) || (asi != 0xb)) {
1679 set_sfsr(MEC_ACC, addr, asi, 0);
1680 *ws = MEM_EX_WS;
1681 return 1;
1682 }
1683 mexc = mec_write(addr, *data);
1684 if (mexc) {
1685 set_sfsr(MEC_ACC, addr, asi, 0);
1686 *ws = MEM_EX_WS;
1687 } else {
1688 *ws = 0;
1689 }
1690 return mexc;
1691
1692 #ifdef ERA
1693
1694 } else if (era) {
1695 if ((erareg & 2) &&
1696 ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1697 addr &= ROM_MASK;
1698 *ws = sz == 3 ? 8 : 4;
1699 store_bytes (romb, addr, data, sz, ws);
1700 return 0;
1701 } else if ((addr >= 0x10000000) &&
1702 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1703 (mec_iocr & 0x10)) {
1704 erareg = *data & 0x0e;
1705 return 0;
1706 }
1707
1708 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1709 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1710 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1711
1712 *ws = mem_romw_ws + 1;
1713 if (sz == 3)
1714 *ws += mem_romw_ws + STD_WS;
1715 store_bytes (romb, addr, data, sz, ws);
1716 return 0;
1717
1718 #else
1719 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1720 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1721 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1722
1723 *ws = mem_romw_ws + 1;
1724 if (sz == 3)
1725 *ws += mem_romw_ws + STD_WS;
1726 store_bytes (romb, addr, data, sz, ws);
1727 return 0;
1728
1729 #endif
1730
1731 }
1732
1733 *ws = MEM_EX_WS;
1734 set_sfsr(UIMP_ACC, addr, asi, 0);
1735 return 1;
1736 }
1737
1738 static void *
1739 get_mem_ptr(uint32_t addr, uint32_t size)
1740 {
1741 if ((addr + size) < ROM_SZ) {
1742 return &romb[addr];
1743 } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
1744 return &ramb[addr & mem_rammask];
1745 }
1746
1747 #ifdef ERA
1748 else if ((era) && ((addr <0x100000) ||
1749 ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
1750 return &romb[addr & ROM_MASK];
1751 }
1752 #endif
1753
1754 return (void *) -1;
1755 }
1756
1757 int
1758 sis_memory_write(uint32_t addr, const void *data, uint32_t length)
1759 {
1760 void *mem;
1761
1762 if ((mem = get_mem_ptr(addr, length)) == ((void *) -1))
1763 return 0;
1764
1765 memcpy(mem, data, length);
1766 return length;
1767 }
1768
1769 int
1770 sis_memory_read(uint32_t addr, void *data, uint32_t length)
1771 {
1772 char *mem;
1773
1774 if ((mem = get_mem_ptr(addr, length)) == ((void *) -1))
1775 return 0;
1776
1777 memcpy(data, mem, length);
1778 return length;
1779 }
1780
1781 extern struct pstate sregs;
1782
1783 void
1784 boot_init (void)
1785 {
1786 mec_write(MEC_WCR, 0); /* zero waitstates */
1787 mec_write(MEC_TRAPD, 0); /* turn off watch-dog */
1788 mec_write(MEC_RTC_SCALER, sregs.freq - 1); /* generate 1 MHz RTC tick */
1789 mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1790 sregs.wim = 2;
1791 sregs.psr = 0x110010e0;
1792 sregs.r[30] = RAM_END;
1793 sregs.r[14] = sregs.r[30] - 96 * 4;
1794 mec_mcr |= 1; /* power-down enabled */
1795 }
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