sim/frv/reset.c

   1 /* frv simulator support code
   2    Copyright (C) 1999-2021 Free Software Foundation, Inc.
   3    Contributed by Red Hat.
   4
   5 This file is part of the GNU simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* This must come before any other includes.  */
  21 #include "defs.h"
  22
  23 #define WANT_CPU
  24 #define WANT_CPU_FRVBF
  25
  26 #include "sim-main.h"
  27 #include "bfd.h"
  28
  29 /* Initialize the frv simulator.  */
  30 void
  31 frv_initialize (SIM_CPU *current_cpu, SIM_DESC sd)
  32 {
  33   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
  34   PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu);
  35   FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu);
  36   FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu);
  37   int insn_cache_enabled = CACHE_INITIALIZED (insn_cache);
  38   int data_cache_enabled = CACHE_INITIALIZED (data_cache);
  39   USI hsr0;
  40
  41   /* Initialize the register control information first since some of the
  42      register values are used in further configuration.  */
  43   frv_register_control_init (current_cpu);
  44
  45   /* We need to ensure that the caches are initialized even if they are not
  46      initially enabled (via commandline) because they can be enabled by
  47      software.  */
  48   if (! insn_cache_enabled)
  49     frv_cache_init (current_cpu, CPU_INSN_CACHE (current_cpu));
  50   if (! data_cache_enabled)
  51     frv_cache_init (current_cpu, CPU_DATA_CACHE (current_cpu));
  52
  53   /* Set the default cpu frequency if it has not been set on the command
  54      line.  */
  55   if (PROFILE_CPU_FREQ (p) == 0)
  56     PROFILE_CPU_FREQ (p) = 266000000; /* 266MHz */
  57
  58   /* Allocate one cache line of memory containing the address of the reset
  59      register Use the largest of the insn cache line size and the data cache
  60      line size.  */
  61   {
  62     int addr = RSTR_ADDRESS;
  63     void *aligned_buffer;
  64     int bytes;
  65
  66     if (CPU_INSN_CACHE (current_cpu)->line_size
  67         > CPU_DATA_CACHE (current_cpu)->line_size)
  68       bytes = CPU_INSN_CACHE (current_cpu)->line_size;
  69     else
  70       bytes = CPU_DATA_CACHE (current_cpu)->line_size;
  71
  72     /* 'bytes' is a power of 2. Calculate the starting address of the
  73        cache line.  */
  74     addr &= ~(bytes - 1);
  75     aligned_buffer = zalloc (bytes); /* clear */
  76     sim_core_attach (sd, NULL, 0, access_read_write, 0, addr, bytes,
  77                      0, NULL, aligned_buffer);
  78   }
  79
  80   PROFILE_INFO_CPU_CALLBACK(p) = frv_profile_info;
  81   ps->insn_fetch_address = -1;
  82   ps->branch_address = -1;
  83
  84   cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu),
  85                           frvbf_fpu_error);
  86
  87   /* Now perform power-on reset.  */
  88   frv_power_on_reset (current_cpu);
  89
  90   /* Make sure that HSR0.ICE and HSR0.DCE are set properly.  */
  91   hsr0 = GET_HSR0 ();
  92   if (insn_cache_enabled)
  93     SET_HSR0_ICE (hsr0);
  94   else
  95     CLEAR_HSR0_ICE (hsr0);
  96   if (data_cache_enabled)
  97     SET_HSR0_DCE (hsr0);
  98   else
  99     CLEAR_HSR0_DCE (hsr0);
 100   SET_HSR0 (hsr0);
 101 }
 102
 103 /* Initialize the frv simulator.  */
 104 void
 105 frv_term (SIM_DESC sd)
 106 {
 107   /* If the timer is enabled, and model profiling was not originally enabled,
 108      then turn it off again.  This is the only place we can currently gain
 109      control to do this.  */
 110   if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p)
 111     sim_profile_set_option (sd, "-model", PROFILE_MODEL_IDX, "0");
 112 }
 113
 114 /* Perform a power on reset.  */
 115 void
 116 frv_power_on_reset (SIM_CPU *cpu)
 117 {
 118   /* GR, FR and CPR registers are undefined at initialization time.  */
 119   frv_initialize_spr (cpu);
 120   /* Initialize the RSTR register (in memory).  */
 121   if (frv_cache_enabled (CPU_DATA_CACHE (cpu)))
 122     frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE);
 123   else
 124     SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE);
 125 }
 126
 127 /* Perform a hardware reset.  */
 128 void
 129 frv_hardware_reset (SIM_CPU *cpu)
 130 {
 131   /* GR, FR and CPR registers are undefined at hardware reset.  */
 132   frv_initialize_spr (cpu);
 133   /* Reset the RSTR register (in memory).  */
 134   if (frv_cache_enabled (CPU_DATA_CACHE (cpu)))
 135     frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET);
 136   else
 137     SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET);
 138   /* Reset the insn and data caches.  */
 139   frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0/* no flush */);
 140   frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 0/* no flush */);
 141 }
 142
 143 /* Perform a software reset.  */
 144 void
 145 frv_software_reset (SIM_CPU *cpu)
 146 {
 147   /* GR, FR and CPR registers are undefined at software reset.  */
 148   frv_reset_spr (cpu);
 149   /* Reset the RSTR register (in memory).  */
 150   if (frv_cache_enabled (CPU_DATA_CACHE (cpu)))
 151     frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET);
 152   else
 153     SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET);
 154 }