2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
20 /* This must come before any other includes. */
26 #ifdef HAVE_SYS_PARAM_H
27 #include <sys/param.h>
32 #include "sim/sim-h8300.h"
34 #include "sys/types.h"
35 #include "sim-options.h"
36 #include "sim-signal.h"
37 #include "sim/callback.h"
45 static int memory_size
;
47 #define X(op, size) (op * 4 + size)
49 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
51 #define h8_opcodes ops
53 #include "opcode/h8300.h"
55 /* CPU data object: */
58 h8_get_reg (sim_cpu
*cpu
, int regnum
)
60 return H8300_SIM_CPU (cpu
)->regs
[regnum
];
64 h8_set_reg (sim_cpu
*cpu
, int regnum
, int val
)
66 H8300_SIM_CPU (cpu
)->regs
[regnum
] = val
;
69 #define h8_get_ccr(cpu) h8_get_reg (cpu, CCR_REGNUM)
70 #define h8_set_ccr(cpu, val) h8_set_reg (cpu, CCR_REGNUM, val)
71 #define h8_get_exr(cpu) h8_get_reg (cpu, EXR_REGNUM)
72 #define h8_set_exr(cpu, val) h8_set_reg (cpu, EXR_REGNUM, val)
73 #define h8_get_sbr(cpu) h8_get_reg (cpu, SBR_REGNUM)
74 #define h8_set_sbr(cpu, val) h8_set_reg (cpu, SBR_REGNUM, val)
75 #define h8_get_vbr(cpu) h8_get_reg (cpu, VBR_REGNUM)
76 #define h8_set_vbr(cpu, val) h8_set_reg (cpu, VBR_REGNUM, val)
77 #define h8_get_cycles(cpu) h8_get_reg (cpu, CYCLE_REGNUM)
78 #define h8_set_cycles(cpu, val) h8_set_reg (cpu, CYCLE_REGNUM, val)
79 #define h8_get_insts(cpu) h8_get_reg (cpu, INST_REGNUM)
80 #define h8_set_insts(cpu, val) h8_set_reg (cpu, INST_REGNUM, val)
81 #define h8_get_ticks(cpu) h8_get_reg (cpu, TICK_REGNUM)
82 #define h8_set_ticks(cpu, val) h8_set_reg (cpu, TICK_REGNUM, val)
83 #define h8_get_mach(cpu) h8_get_reg (cpu, MACH_REGNUM)
84 #define h8_set_mach(cpu, val) h8_set_reg (cpu, MACH_REGNUM, val)
85 #define h8_get_macl(cpu) h8_get_reg (cpu, MACL_REGNUM)
86 #define h8_set_macl(cpu, val) h8_set_reg (cpu, MACL_REGNUM, val)
89 h8_get_mask (sim_cpu
*cpu
)
91 return H8300_SIM_CPU (cpu
)->mask
;
95 h8_set_mask (sim_cpu
*cpu
, int val
)
97 H8300_SIM_CPU (cpu
)->mask
= val
;
101 h8_get_exception (sim_cpu
*cpu
)
103 return H8300_SIM_CPU (cpu
)->exception
;
107 h8_set_exception (sim_cpu
*cpu
, int val
)
109 H8300_SIM_CPU (cpu
)->exception
= val
;
112 static enum h8300_sim_state
113 h8_get_state (SIM_DESC sd
)
115 return H8300_SIM_STATE (sd
)->state
;
119 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
121 H8300_SIM_STATE (sd
)->state
= val
;
125 static unsigned int *
126 h8_get_reg_buf (sim_cpu
*cpu
)
128 return &H8300_SIM_CPU (cpu
)->regs
[0];
133 h8_get_stats (SIM_DESC sd
, int idx
)
135 return H8300_SIM_STATE (sd
)->stats
[idx
];
139 h8_increment_stats (SIM_DESC sd
, int idx
)
141 H8300_SIM_STATE (sd
)->stats
[idx
] ++;
145 static unsigned char *
146 h8_get_memory_buf (sim_cpu
*cpu
)
148 return H8300_SIM_CPU (cpu
)->memory
;
152 h8_set_memory_buf (sim_cpu
*cpu
, unsigned char *ptr
)
154 H8300_SIM_CPU (cpu
)->memory
= ptr
;
158 h8_get_memory (sim_cpu
*cpu
, int idx
)
160 ASSERT (idx
< memory_size
);
161 return H8300_SIM_CPU (cpu
)->memory
[idx
];
165 h8_set_memory (sim_cpu
*cpu
, int idx
, unsigned int val
)
167 ASSERT (idx
< memory_size
);
168 H8300_SIM_CPU (cpu
)->memory
[idx
] = (unsigned char) val
;
172 h8_get_delayed_branch (sim_cpu
*cpu
)
174 return H8300_SIM_CPU (cpu
)->delayed_branch
;
178 h8_set_delayed_branch (sim_cpu
*cpu
, unsigned int dest
)
180 H8300_SIM_CPU (cpu
)->delayed_branch
= dest
;
184 h8_get_command_line (sim_cpu
*cpu
)
186 return H8300_SIM_CPU (cpu
)->command_line
;
190 h8_set_command_line (sim_cpu
*cpu
, char ** val
)
192 H8300_SIM_CPU (cpu
)->command_line
= val
;
196 h8_get_cmdline_arg (sim_cpu
*cpu
, int index
)
198 return H8300_SIM_CPU (cpu
)->command_line
[index
];
202 h8_set_cmdline_arg (sim_cpu
*cpu
, int index
, char * val
)
204 H8300_SIM_CPU (cpu
)->command_line
[index
] = val
;
207 /* MAC Saturation Mode */
209 h8_get_macS (sim_cpu
*cpu
)
211 return H8300_SIM_CPU (cpu
)->macS
;
216 h8_set_macS (sim_cpu
*cpu
, int val
)
218 H8300_SIM_CPU (cpu
)->macS
= (val
!= 0);
224 h8_get_macZ (sim_cpu
*cpu
)
226 return H8300_SIM_CPU (cpu
)->macZ
;
230 h8_set_macZ (sim_cpu
*cpu
, int val
)
232 H8300_SIM_CPU (cpu
)->macZ
= (val
!= 0);
235 /* MAC Negative Flag */
237 h8_get_macN (sim_cpu
*cpu
)
239 return H8300_SIM_CPU (cpu
)->macN
;
243 h8_set_macN (sim_cpu
*cpu
, int val
)
245 H8300_SIM_CPU (cpu
)->macN
= (val
!= 0);
248 /* MAC Overflow Flag */
250 h8_get_macV (sim_cpu
*cpu
)
252 return H8300_SIM_CPU (cpu
)->macV
;
256 h8_set_macV (sim_cpu
*cpu
, int val
)
258 H8300_SIM_CPU (cpu
)->macV
= (val
!= 0);
261 /* End CPU data object. */
263 /* The rate at which to call the host's poll_quit callback. */
265 enum { POLL_QUIT_INTERVAL
= 0x80000 };
267 #define LOW_BYTE(x) ((x) & 0xff)
268 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
269 #define P(X, Y) ((X << 8) | Y)
278 #define I (intMaskBit != 0)
280 #define BUILDSR(cpu) \
281 h8_set_ccr (cpu, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
282 | (N << 3) | (Z << 2) | (V << 1) | C)
285 /* Get Status Register (flags). */ \
286 c = (h8_get_ccr (cpu) >> 0) & 1; \
287 v = (h8_get_ccr (cpu) >> 1) & 1; \
288 nz = !((h8_get_ccr (cpu) >> 2) & 1); \
289 n = (h8_get_ccr (cpu) >> 3) & 1; \
290 u = (h8_get_ccr (cpu) >> 4) & 1; \
291 h = (h8_get_ccr (cpu) >> 5) & 1; \
292 ui = ((h8_get_ccr (cpu) >> 6) & 1); \
293 intMaskBit = (h8_get_ccr (cpu) >> 7) & 1
296 #ifdef __CHAR_IS_SIGNED__
297 #define SEXTCHAR(x) ((char) (x))
301 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
304 #define UEXTCHAR(x) ((x) & 0xff)
305 #define UEXTSHORT(x) ((x) & 0xffff)
306 #define SEXTSHORT(x) ((short) (x))
310 int h8300_normal_mode
= 0;
316 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
338 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
343 /* Simulate an indirection / dereference.
344 return 0 for success, -1 for failure.
348 lvalue (SIM_DESC sd
, sim_cpu
*cpu
, int x
, int rn
, unsigned int *val
)
350 if (val
== NULL
) /* Paranoia. */
356 if (rn
== ZERO_REGNUM
)
357 *val
= X (OP_IMM
, SP
);
359 *val
= X (OP_REG
, SP
);
362 *val
= X (OP_MEM
, SP
);
365 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
372 cmdline_location(void)
374 if (h8300smode
&& !h8300_normal_mode
)
376 else if (h8300hmode
&& !h8300_normal_mode
)
383 decode (SIM_DESC sd
, sim_cpu
*cpu
, int addr
, unsigned char *data
, decoded_inst
*dst
)
385 int cst
[3] = {0, 0, 0};
386 int reg
[3] = {0, 0, 0};
387 int rdisp
[3] = {0, 0, 0};
389 const struct h8_opcode
*q
;
395 /* Find the exact opcode/arg combo. */
396 for (q
= h8_opcodes
; q
->name
; q
++)
398 const op_type
*nib
= q
->data
.nib
;
399 unsigned int len
= 0;
401 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
402 (q
->available
== AV_H8S
&& !h8300smode
) ||
403 (q
->available
== AV_H8H
&& !h8300hmode
))
406 cst
[0] = cst
[1] = cst
[2] = 0;
407 reg
[0] = reg
[1] = reg
[2] = 0;
408 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
412 op_type looking_for
= *nib
;
413 int thisnib
= data
[len
/ 2];
415 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
416 opnum
= ((looking_for
& OP3
) ? 2 :
417 (looking_for
& DST
) ? 1 : 0);
419 if (looking_for
< 16 && looking_for
>= 0)
421 if (looking_for
!= thisnib
)
426 if (looking_for
& B31
)
428 if (!((thisnib
& 0x8) != 0))
431 looking_for
= (op_type
) (looking_for
& ~B31
);
434 else if (looking_for
& B30
)
436 if (!((thisnib
& 0x8) == 0))
439 looking_for
= (op_type
) (looking_for
& ~B30
);
442 if (looking_for
& B21
)
444 if (!((thisnib
& 0x4) != 0))
447 looking_for
= (op_type
) (looking_for
& ~B21
);
450 else if (looking_for
& B20
)
452 if (!((thisnib
& 0x4) == 0))
455 looking_for
= (op_type
) (looking_for
& ~B20
);
458 if (looking_for
& B11
)
460 if (!((thisnib
& 0x2) != 0))
463 looking_for
= (op_type
) (looking_for
& ~B11
);
466 else if (looking_for
& B10
)
468 if (!((thisnib
& 0x2) == 0))
471 looking_for
= (op_type
) (looking_for
& ~B10
);
474 if (looking_for
& B01
)
476 if (!((thisnib
& 0x1) != 0))
479 looking_for
= (op_type
) (looking_for
& ~B01
);
482 else if (looking_for
& B00
)
484 if (!((thisnib
& 0x1) == 0))
487 looking_for
= (op_type
) (looking_for
& ~B00
);
490 if (looking_for
& IGNORE
)
492 /* Hitachi has declared that IGNORE must be zero. */
496 else if ((looking_for
& MODE
) == DATA
)
498 ; /* Skip embedded data. */
500 else if ((looking_for
& MODE
) == DBIT
)
502 /* Exclude adds/subs by looking at bit 0 and 2, and
503 make sure the operand size, either w or l,
504 matches by looking at bit 1. */
505 if ((looking_for
& 7) != (thisnib
& 7))
508 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
510 else if ((looking_for
& MODE
) == REG
||
511 (looking_for
& MODE
) == LOWREG
||
512 (looking_for
& MODE
) == IND
||
513 (looking_for
& MODE
) == PREINC
||
514 (looking_for
& MODE
) == POSTINC
||
515 (looking_for
& MODE
) == PREDEC
||
516 (looking_for
& MODE
) == POSTDEC
)
518 reg
[opnum
] = thisnib
;
520 else if (looking_for
& CTRL
)
523 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
524 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
525 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
526 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
527 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
528 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
530 if (((looking_for
& MODE
) == CCR_EXR
&&
531 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
532 ((looking_for
& MODE
) == VBR_SBR
&&
533 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
534 ((looking_for
& MODE
) == MACREG
&&
535 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
537 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
538 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
539 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
542 reg
[opnum
] = thisnib
;
544 else if ((looking_for
& MODE
) == ABS
)
546 /* Absolute addresses are unsigned. */
547 switch (looking_for
& SIZE
)
550 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
554 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
558 (data
[len
/ 2 + 0] << 24) +
559 (data
[len
/ 2 + 1] << 16) +
560 (data
[len
/ 2 + 2] << 8) +
564 printf ("decode: bad size ABS: %d\n",
565 (looking_for
& SIZE
));
569 else if ((looking_for
& MODE
) == DISP
||
570 (looking_for
& MODE
) == PCREL
||
571 (looking_for
& MODE
) == INDEXB
||
572 (looking_for
& MODE
) == INDEXW
||
573 (looking_for
& MODE
) == INDEXL
)
575 switch (looking_for
& SIZE
)
578 cst
[opnum
] = thisnib
& 3;
581 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
584 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
585 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
588 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
592 (data
[len
/ 2 + 0] << 24) +
593 (data
[len
/ 2 + 1] << 16) +
594 (data
[len
/ 2 + 2] << 8) +
598 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
599 (looking_for
& SIZE
));
603 else if ((looking_for
& SIZE
) == L_16
||
604 (looking_for
& SIZE
) == L_16U
)
606 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
607 /* Immediates are always unsigned. */
608 if ((looking_for
& SIZE
) != L_16U
&&
609 (looking_for
& MODE
) != IMM
)
610 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
612 else if (looking_for
& ABSJMP
)
614 switch (looking_for
& SIZE
) {
616 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
620 (data
[len
/ 2 + 0] << 24) +
621 (data
[len
/ 2 + 1] << 16) +
622 (data
[len
/ 2 + 2] << 8) +
626 printf ("decode: bad size ABSJMP: %d\n",
627 (looking_for
& SIZE
));
631 else if ((looking_for
& MODE
) == MEMIND
)
633 cst
[opnum
] = data
[1];
635 else if ((looking_for
& MODE
) == VECIND
)
637 if(h8300_normal_mode
)
638 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
640 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
641 cst
[opnum
] += h8_get_vbr (cpu
); /* Add vector base reg. */
643 else if ((looking_for
& SIZE
) == L_32
)
648 (data
[i
+ 0] << 24) |
649 (data
[i
+ 1] << 16) |
653 else if ((looking_for
& SIZE
) == L_24
)
658 (data
[i
+ 0] << 16) |
662 else if (looking_for
& DISPREG
)
664 rdisp
[opnum
] = thisnib
& 0x7;
666 else if ((looking_for
& MODE
) == KBIT
)
683 else if ((looking_for
& SIZE
) == L_8
)
685 if ((looking_for
& MODE
) == ABS
)
687 /* Will be combined with contents of SBR_REGNUM
688 by fetch (). For all modes except h8sx, this
689 will always contain the value 0xFFFFFF00. */
690 cst
[opnum
] = data
[len
/ 2] & 0xff;
694 cst
[opnum
] = data
[len
/ 2] & 0xff;
697 else if ((looking_for
& SIZE
) == L_2
)
699 cst
[opnum
] = thisnib
& 3;
701 else if ((looking_for
& SIZE
) == L_3
||
702 (looking_for
& SIZE
) == L_3NZ
)
704 cst
[opnum
] = thisnib
& 7;
705 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
708 else if ((looking_for
& SIZE
) == L_4
)
710 cst
[opnum
] = thisnib
& 15;
712 else if ((looking_for
& SIZE
) == L_5
)
714 cst
[opnum
] = data
[len
/ 2] & 0x1f;
716 else if (looking_for
== E
)
721 /* Fill in the args. */
723 const op_type
*args
= q
->args
.nib
;
728 nargs
< 3 && *args
!= E
;
734 opnum
= ((x
& OP3
) ? 2 :
743 if ((x
& MODE
) == IMM
||
744 (x
& MODE
) == KBIT
||
747 /* Use the instruction to determine
749 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
750 p
->literal
= cst
[opnum
];
752 else if ((x
& MODE
) == CONST_2
||
753 (x
& MODE
) == CONST_4
||
754 (x
& MODE
) == CONST_8
||
755 (x
& MODE
) == CONST_16
)
757 /* Use the instruction to determine
759 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
761 case CONST_2
: p
->literal
= 2; break;
762 case CONST_4
: p
->literal
= 4; break;
763 case CONST_8
: p
->literal
= 8; break;
764 case CONST_16
: p
->literal
= 16; break;
767 else if ((x
& MODE
) == REG
)
769 p
->type
= X (OP_REG
, bitfrom (x
));
772 else if ((x
& MODE
) == LOWREG
)
774 p
->type
= X (OP_LOWREG
, bitfrom (x
));
777 else if ((x
& MODE
) == PREINC
)
779 /* Use the instruction to determine
781 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
782 p
->reg
= reg
[opnum
] & 0x7;
784 else if ((x
& MODE
) == POSTINC
)
786 /* Use the instruction to determine
788 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
789 p
->reg
= reg
[opnum
] & 0x7;
791 else if ((x
& MODE
) == PREDEC
)
793 /* Use the instruction to determine
795 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
796 p
->reg
= reg
[opnum
] & 0x7;
798 else if ((x
& MODE
) == POSTDEC
)
800 /* Use the instruction to determine
802 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
803 p
->reg
= reg
[opnum
] & 0x7;
805 else if ((x
& MODE
) == IND
)
807 /* Note: an indirect is transformed into
808 a displacement of zero.
810 /* Use the instruction to determine
812 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
813 p
->reg
= reg
[opnum
] & 0x7;
815 if (OP_KIND (q
->how
) == O_JSR
||
816 OP_KIND (q
->how
) == O_JMP
)
817 if (lvalue (sd
, cpu
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
820 else if ((x
& MODE
) == ABS
)
822 /* Note: a 16 or 32 bit ABS is transformed into a
823 displacement from pseudo-register ZERO_REGNUM,
824 which is always zero. An 8 bit ABS becomes
825 a displacement from SBR_REGNUM.
827 /* Use the instruction to determine
829 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
830 p
->literal
= cst
[opnum
];
832 /* 8-bit ABS is displacement from SBR.
833 16 and 32-bit ABS are displacement from ZERO.
834 (SBR will always be zero except for h8/sx)
836 if ((x
& SIZE
) == L_8
)
839 p
->reg
= ZERO_REGNUM
;;
841 else if ((x
& MODE
) == MEMIND
||
842 (x
& MODE
) == VECIND
)
844 /* Size doesn't matter. */
845 p
->type
= X (OP_MEM
, SB
);
846 p
->literal
= cst
[opnum
];
847 if (OP_KIND (q
->how
) == O_JSR
||
848 OP_KIND (q
->how
) == O_JMP
)
849 if (lvalue (sd
, cpu
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
852 else if ((x
& MODE
) == PCREL
)
854 /* Size doesn't matter. */
855 p
->type
= X (OP_PCREL
, SB
);
856 p
->literal
= cst
[opnum
];
860 p
->type
= X (OP_IMM
, SP
);
861 p
->literal
= cst
[opnum
];
863 else if ((x
& MODE
) == INDEXB
)
865 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
866 p
->literal
= cst
[opnum
];
867 p
->reg
= rdisp
[opnum
];
869 else if ((x
& MODE
) == INDEXW
)
871 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
872 p
->literal
= cst
[opnum
];
873 p
->reg
= rdisp
[opnum
];
875 else if ((x
& MODE
) == INDEXL
)
877 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
878 p
->literal
= cst
[opnum
];
879 p
->reg
= rdisp
[opnum
];
881 else if ((x
& MODE
) == DISP
)
883 /* Yuck -- special for mova args. */
884 if (strncmp (q
->name
, "mova", 4) == 0 &&
887 /* Mova can have a DISP2 dest, with an
888 INDEXB or INDEXW src. The multiplier
889 for the displacement value is determined
890 by the src operand, not by the insn. */
892 switch (OP_KIND (dst
->src
.type
))
895 p
->type
= X (OP_DISP
, SB
);
896 p
->literal
= cst
[opnum
];
899 p
->type
= X (OP_DISP
, SW
);
900 p
->literal
= cst
[opnum
] * 2;
908 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
909 p
->literal
= cst
[opnum
];
910 /* DISP2 is special. */
911 if ((x
& SIZE
) == L_2
)
912 switch (OP_SIZE (q
->how
))
915 case SW
: p
->literal
*= 2; break;
916 case SL
: p
->literal
*= 4; break;
919 p
->reg
= rdisp
[opnum
];
926 p
->type
= X (OP_CCR
, SB
);
929 p
->type
= X (OP_EXR
, SB
);
932 p
->type
= X (OP_MACH
, SL
);
935 p
->type
= X (OP_MACL
, SL
);
938 p
->type
= X (OP_VBR
, SL
);
941 p
->type
= X (OP_SBR
, SL
);
945 else if ((x
& MODE
) == CCR
)
949 else if ((x
& MODE
) == EXR
)
954 printf ("Hmmmm 0x%x...\n", x
);
960 /* Unary operators: treat src and dst as equivalent. */
961 if (dst
->dst
.type
== -1)
963 if (dst
->src
.type
== -1)
966 dst
->opcode
= q
->how
;
967 dst
->cycles
= q
->time
;
969 /* And jsr's to these locations are turned into
972 if (OP_KIND (dst
->opcode
) == O_JSR
)
974 switch (dst
->src
.literal
)
977 dst
->opcode
= O (O_SYS_OPEN
, SB
);
980 dst
->opcode
= O (O_SYS_READ
, SB
);
983 dst
->opcode
= O (O_SYS_WRITE
, SB
);
986 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
989 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
992 dst
->opcode
= O (O_SYS_STAT
, SB
);
995 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
998 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1001 /* End of Processing for system calls. */
1004 /* Use same register is specified for source
1006 The value of source will be the value after
1007 address calculation. */
1008 if (OP_KIND (dst
->opcode
) != O_CMP
&&
1009 OP_KIND (dst
->src
.type
) == OP_REG
&&
1010 (dst
->src
.reg
& 7) == dst
->dst
.reg
) {
1011 switch (OP_KIND (dst
->dst
.type
))
1014 dst
->src
.type
= X (OP_REG_DEC
,
1015 OP_SIZE (dst
->dst
.type
));
1018 dst
->src
.type
= X (OP_REG_INC
,
1019 OP_SIZE (dst
->dst
.type
));
1022 if (OP_KIND (dst
->opcode
) == O_MOV
)
1023 dst
->src
.type
= X (OP_REG_INC
,
1024 OP_SIZE (dst
->dst
.type
));
1027 if (OP_KIND (dst
->opcode
) == O_MOV
)
1028 dst
->src
.type
= X (OP_REG_DEC
,
1029 OP_SIZE (dst
->dst
.type
));
1033 dst
->next_pc
= addr
+ len
/ 2;
1037 printf ("Don't understand 0x%x \n", looking_for
);
1048 /* Fell off the end. */
1049 dst
->opcode
= O (O_ILL
, SB
);
1052 static unsigned char *breg
[32];
1053 static unsigned short *wreg
[16];
1055 #define GET_B_REG(X) *(breg[X])
1056 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1057 #define GET_W_REG(X) *(wreg[X])
1058 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1059 #define GET_L_REG(X) h8_get_reg (cpu, X)
1060 #define SET_L_REG(X, Y) h8_set_reg (cpu, X, Y)
1062 #define GET_MEMORY_L(X) \
1063 ((X) < memory_size \
1064 ? ((h8_get_memory (cpu, (X)+0) << 24) | (h8_get_memory (cpu, (X)+1) << 16) \
1065 | (h8_get_memory (cpu, (X)+2) << 8) | (h8_get_memory (cpu, (X)+3) << 0)) \
1068 #define GET_MEMORY_W(X) \
1069 ((X) < memory_size \
1070 ? ((h8_get_memory (cpu, (X)+0) << 8) | (h8_get_memory (cpu, (X)+1) << 0)) \
1073 #define GET_MEMORY_B(X) \
1074 ((X) < memory_size ? h8_get_memory (cpu, (X)) : 0)
1076 #define SET_MEMORY_L(X, Y) \
1077 { register unsigned char *_p; register int __y = (Y); \
1078 _p = ((X) < memory_size ? h8_get_memory_buf (cpu) + (X) : 0); \
1079 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1080 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1083 #define SET_MEMORY_W(X, Y) \
1084 { register unsigned char *_p; register int __y = (Y); \
1085 _p = ((X) < memory_size ? h8_get_memory_buf (cpu) + (X) : 0); \
1086 _p[0] = __y >> 8; _p[1] = __y; \
1089 #define SET_MEMORY_B(X, Y) \
1090 ((X) < memory_size ? h8_set_memory (cpu, (X), (Y)) : 0)
1092 /* Simulate a memory fetch.
1093 Return 0 for success, -1 for failure.
1097 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1099 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1101 int abs
= arg
->literal
;
1106 return -1; /* Paranoia. */
1110 /* Indexed register plus displacement mode:
1112 This new family of addressing modes are similar to OP_DISP
1113 (register plus displacement), with two differences:
1114 1) INDEXB uses only the least significant byte of the register,
1115 INDEXW uses only the least significant word, and
1116 INDEXL uses the entire register (just like OP_DISP).
1118 2) The displacement value in abs is multiplied by two
1119 for SW-sized operations, and by four for SL-size.
1121 This gives nine possible variations.
1124 case X (OP_INDEXB
, SB
):
1125 case X (OP_INDEXB
, SW
):
1126 case X (OP_INDEXB
, SL
):
1127 case X (OP_INDEXW
, SB
):
1128 case X (OP_INDEXW
, SW
):
1129 case X (OP_INDEXW
, SL
):
1130 case X (OP_INDEXL
, SB
):
1131 case X (OP_INDEXL
, SW
):
1132 case X (OP_INDEXL
, SL
):
1134 switch (OP_KIND (arg
->type
)) {
1135 case OP_INDEXB
: t
&= 0xff; break;
1136 case OP_INDEXW
: t
&= 0xffff; break;
1140 switch (OP_SIZE (arg
->type
)) {
1142 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (cpu
));
1145 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (cpu
));
1148 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (cpu
));
1153 case X (OP_LOWREG
, SB
):
1154 *val
= GET_L_REG (rn
) & 0xff;
1156 case X (OP_LOWREG
, SW
):
1157 *val
= GET_L_REG (rn
) & 0xffff;
1160 case X (OP_REG
, SB
): /* Register direct, byte. */
1161 *val
= GET_B_REG (rn
);
1163 case X (OP_REG
, SW
): /* Register direct, word. */
1164 *val
= GET_W_REG (rn
);
1166 case X (OP_REG
, SL
): /* Register direct, long. */
1167 *val
= GET_L_REG (rn
);
1169 case X (OP_IMM
, SB
): /* Immediate, byte. */
1170 case X (OP_IMM
, SW
): /* Immediate, word. */
1171 case X (OP_IMM
, SL
): /* Immediate, long. */
1174 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1176 r
= GET_MEMORY_B (t
& h8_get_mask (cpu
));
1182 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1184 r
= GET_MEMORY_W (t
& h8_get_mask (cpu
));
1190 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1192 r
= GET_MEMORY_L (t
& h8_get_mask (cpu
));
1199 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1201 r
= GET_MEMORY_B (t
& h8_get_mask (cpu
));
1207 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1209 r
= GET_MEMORY_W (t
& h8_get_mask (cpu
));
1215 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1217 r
= GET_MEMORY_L (t
& h8_get_mask (cpu
));
1224 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1225 t
= GET_L_REG (rn
) - 1;
1227 t
&= h8_get_mask (cpu
);
1228 *val
= GET_MEMORY_B (t
);
1231 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1232 t
= GET_L_REG (rn
) - 2;
1234 t
&= h8_get_mask (cpu
);
1235 *val
= GET_MEMORY_W (t
);
1238 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1239 t
= GET_L_REG (rn
) - 4;
1241 t
&= h8_get_mask (cpu
);
1242 *val
= GET_MEMORY_L (t
);
1245 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1246 t
= GET_L_REG (rn
) + 1;
1248 t
&= h8_get_mask (cpu
);
1249 *val
= GET_MEMORY_B (t
);
1252 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1253 t
= GET_L_REG (rn
) + 2;
1255 t
&= h8_get_mask (cpu
);
1256 *val
= GET_MEMORY_W (t
);
1259 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1260 t
= GET_L_REG (rn
) + 4;
1262 t
&= h8_get_mask (cpu
);
1263 *val
= GET_MEMORY_L (t
);
1266 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1267 t
= GET_L_REG (rn
) + abs
;
1268 t
&= h8_get_mask (cpu
);
1269 *val
= GET_MEMORY_B (t
);
1272 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1273 t
= GET_L_REG (rn
) + abs
;
1274 t
&= h8_get_mask (cpu
);
1275 *val
= GET_MEMORY_W (t
);
1278 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1279 t
= GET_L_REG (rn
) + abs
;
1280 t
&= h8_get_mask (cpu
);
1281 *val
=GET_MEMORY_L (t
);
1284 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1285 t
= GET_MEMORY_L (abs
);
1286 t
&= h8_get_mask (cpu
);
1290 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1291 t
= GET_MEMORY_W (abs
);
1292 t
&= h8_get_mask (cpu
);
1296 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1297 case X (OP_PCREL
, SW
):
1298 case X (OP_PCREL
, SL
):
1299 case X (OP_PCREL
, SN
):
1303 case X (OP_REG_DEC
, SB
): /* Register direct, affected decrement byte. */
1304 *val
= GET_B_REG (rn
) - 1;
1306 case X (OP_REG_DEC
, SW
): /* Register direct, affected decrement word. */
1307 *val
= GET_W_REG (rn
) - 2;
1309 case X (OP_REG_DEC
, SL
): /* Register direct, affected decrement long. */
1310 *val
= GET_L_REG (rn
) - 4;
1312 case X (OP_REG_INC
, SB
): /* Register direct, affected increment byte. */
1313 *val
= GET_B_REG (rn
) + 1;
1315 case X (OP_REG_INC
, SW
): /* Register direct, affected increment word. */
1316 *val
= GET_W_REG (rn
) + 2;
1318 case X (OP_REG_INC
, SL
): /* Register direct, affected increment long. */
1319 *val
= GET_L_REG (rn
) + 4;
1322 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1324 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1327 return 0; /* Success. */
1333 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1335 return fetch_1 (sd
, arg
, val
, 0);
1338 /* Fetch which will be followed by a store to the same location.
1339 The difference being that we don't want to do a post-increment
1340 or post-decrement at this time: we'll do it when we store. */
1343 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1345 return fetch_1 (sd
, arg
, val
, 1);
1348 /* Simulate a memory store.
1349 Return 0 for success, -1 for failure.
1353 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1355 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1357 int abs
= arg
->literal
;
1362 /* Indexed register plus displacement mode:
1364 This new family of addressing modes are similar to OP_DISP
1365 (register plus displacement), with two differences:
1366 1) INDEXB uses only the least significant byte of the register,
1367 INDEXW uses only the least significant word, and
1368 INDEXL uses the entire register (just like OP_DISP).
1370 2) The displacement value in abs is multiplied by two
1371 for SW-sized operations, and by four for SL-size.
1373 This gives nine possible variations.
1376 case X (OP_INDEXB
, SB
):
1377 case X (OP_INDEXB
, SW
):
1378 case X (OP_INDEXB
, SL
):
1379 case X (OP_INDEXW
, SB
):
1380 case X (OP_INDEXW
, SW
):
1381 case X (OP_INDEXW
, SL
):
1382 case X (OP_INDEXL
, SB
):
1383 case X (OP_INDEXL
, SW
):
1384 case X (OP_INDEXL
, SL
):
1386 switch (OP_KIND (arg
->type
)) {
1387 case OP_INDEXB
: t
&= 0xff; break;
1388 case OP_INDEXW
: t
&= 0xffff; break;
1392 switch (OP_SIZE (arg
->type
)) {
1394 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (cpu
), n
);
1397 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (cpu
), n
);
1400 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (cpu
), n
);
1405 case X (OP_REG
, SB
): /* Register direct, byte. */
1408 case X (OP_REG
, SW
): /* Register direct, word. */
1411 case X (OP_REG
, SL
): /* Register direct, long. */
1415 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1420 t
&= h8_get_mask (cpu
);
1421 SET_MEMORY_B (t
, n
);
1424 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1429 t
&= h8_get_mask (cpu
);
1430 SET_MEMORY_W (t
, n
);
1433 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1438 t
&= h8_get_mask (cpu
);
1439 SET_MEMORY_L (t
, n
);
1442 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1447 t
&= h8_get_mask (cpu
);
1448 SET_MEMORY_B (t
, n
);
1451 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1456 t
&= h8_get_mask (cpu
);
1457 SET_MEMORY_W (t
, n
);
1460 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1465 t
&= h8_get_mask (cpu
);
1466 SET_MEMORY_L (t
, n
);
1469 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1471 SET_L_REG (rn
, t
- 1);
1472 t
&= h8_get_mask (cpu
);
1473 SET_MEMORY_B (t
, n
);
1476 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1478 SET_L_REG (rn
, t
- 2);
1479 t
&= h8_get_mask (cpu
);
1480 SET_MEMORY_W (t
, n
);
1483 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1485 SET_L_REG (rn
, t
- 4);
1486 t
&= h8_get_mask (cpu
);
1487 SET_MEMORY_L (t
, n
);
1490 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1492 SET_L_REG (rn
, t
+ 1);
1493 t
&= h8_get_mask (cpu
);
1494 SET_MEMORY_B (t
, n
);
1497 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1499 SET_L_REG (rn
, t
+ 2);
1500 t
&= h8_get_mask (cpu
);
1501 SET_MEMORY_W (t
, n
);
1504 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1506 SET_L_REG (rn
, t
+ 4);
1507 t
&= h8_get_mask (cpu
);
1508 SET_MEMORY_L (t
, n
);
1511 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1512 t
= GET_L_REG (rn
) + abs
;
1513 t
&= h8_get_mask (cpu
);
1514 SET_MEMORY_B (t
, n
);
1517 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1518 t
= GET_L_REG (rn
) + abs
;
1519 t
&= h8_get_mask (cpu
);
1520 SET_MEMORY_W (t
, n
);
1523 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1524 t
= GET_L_REG (rn
) + abs
;
1525 t
&= h8_get_mask (cpu
);
1526 SET_MEMORY_L (t
, n
);
1530 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1531 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1532 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1534 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1543 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1545 return store_1 (sd
, arg
, n
, 0);
1548 /* Store which follows a fetch from the same location.
1549 The difference being that we don't want to do a pre-increment
1550 or pre-decrement at this time: it was already done when we fetched. */
1553 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1555 return store_1 (sd
, arg
, n
, 1);
1558 /* Flag to be set whenever a new SIM_DESC object is created. */
1559 static int init_pointers_needed
= 1;
1562 init_pointers (SIM_DESC sd
)
1564 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
1565 struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
1567 if (init_pointers_needed
)
1571 if (h8300smode
&& !h8300_normal_mode
)
1572 memory_size
= H8300S_MSIZE
;
1573 else if (h8300hmode
&& !h8300_normal_mode
)
1574 memory_size
= H8300H_MSIZE
;
1576 memory_size
= H8300_MSIZE
;
1577 /* `msize' must be a power of two. */
1578 if ((memory_size
& (memory_size
- 1)) != 0)
1582 "init_pointers: bad memory size %d, defaulting to %d.\n",
1583 memory_size
, H8300S_MSIZE
);
1584 memory_size
= H8300S_MSIZE
;
1587 if (h8_get_memory_buf (cpu
))
1588 free (h8_get_memory_buf (cpu
));
1590 h8_set_memory_buf (cpu
, (unsigned char *)
1591 calloc (sizeof (char), memory_size
));
1592 state
->memory_size
= memory_size
;
1594 h8_set_mask (cpu
, memory_size
- 1);
1596 memset (h8_get_reg_buf (cpu
), 0, sizeof (H8300_SIM_CPU (cpu
)->regs
));
1598 for (i
= 0; i
< 8; i
++)
1600 /* FIXME: rewrite using local buffer. */
1601 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (cpu
) + i
);
1602 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (cpu
) + i
+ 1);
1603 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (cpu
) + i
);
1604 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (cpu
) + i
+ 1);
1605 h8_set_reg (cpu
, i
, 0x00112233);
1620 wreg
[i
] = wreg
[i
+ 8] = 0;
1634 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1635 sim_io_printf (sd
, "init_pointers: internal error.\n");
1637 h8_set_reg (cpu
, i
, 0);
1640 init_pointers_needed
= 0;
1644 #define OBITOP(name, f, s, op) \
1645 case O (name, SB): \
1650 if (fetch (sd, &code->dst, &ea)) \
1652 if (fetch (sd, &code->src, &tmp)) \
1654 m = 1 << (tmp & 7); \
1657 if (store (sd, &code->dst,ea)) \
1663 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
1667 int tick_start
= get_now ();
1674 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1678 const struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
1679 host_callback
*sim_callback
= STATE_CALLBACK (sd
);
1683 pc
= cpu_get_pc (cpu
);
1685 /* The PC should never be odd. */
1688 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGBUS
);
1692 /* Get Status Register (flags). */
1695 if (h8300smode
) /* Get exr. */
1697 trace
= (h8_get_exr (cpu
) >> 7) & 1;
1698 intMask
= h8_get_exr (cpu
) & 7;
1701 oldmask
= h8_get_mask (cpu
);
1702 if (!h8300hmode
|| h8300_normal_mode
)
1703 h8_set_mask (cpu
, 0xffff);
1706 decoded_inst _code
, *code
= &_code
;
1707 memset (code
, 0, sizeof (*code
));
1708 decode (sd
, cpu
, pc
, h8_get_memory_buf (cpu
) + pc
, code
);
1714 printf ("%x %d %s\n", pc
, code
->opcode
,
1715 code
->op
? code
->op
->name
: "**");
1717 h8_increment_stats (sd
, code
->opcode
);
1722 cycles
+= code
->cycles
;
1726 switch (code
->opcode
)
1728 case O (O_MOVAB
, SL
):
1729 case O (O_MOVAW
, SL
):
1730 case O (O_MOVAL
, SL
):
1731 /* 1) Evaluate 2nd argument (dst).
1732 2) Mask / zero extend according to whether 1st argument (src)
1733 is INDEXB, INDEXW, or INDEXL.
1734 3) Left-shift the result by 0, 1 or 2, according to size of mova
1735 (mova/b, mova/w, mova/l).
1736 4) Add literal value of 1st argument (src).
1737 5) Store result in 3rd argument (op3).
1740 /* Alas, since this is the only instruction with 3 arguments,
1741 decode doesn't handle them very well. Some fix-up is required.
1743 a) The size of dst is determined by whether src is
1744 INDEXB or INDEXW. */
1746 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1747 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1748 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1749 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1751 /* b) If op3 == null, then this is the short form of the insn.
1752 Dst is the dispreg of src, and op3 is the 32-bit form
1753 of the same register.
1756 if (code
->op3
.type
== -1)
1758 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1759 We get to compose dst and op3 as follows:
1761 op3 is a 32-bit register, ID == src.reg.
1762 dst is the same register, but 8 or 16 bits
1763 depending on whether src is INDEXB or INDEXW.
1766 code
->op3
.type
= X (OP_REG
, SL
);
1767 code
->op3
.reg
= code
->src
.reg
;
1768 code
->op3
.literal
= 0;
1770 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1772 code
->dst
.type
= X (OP_REG
, SB
);
1773 code
->dst
.reg
= code
->op3
.reg
+ 8;
1776 code
->dst
.type
= X (OP_REG
, SW
);
1779 if (fetch (sd
, &code
->dst
, &ea
))
1782 switch (OP_KIND (code
->src
.type
)) {
1783 case OP_INDEXB
: ea
= ea
& 0xff; break;
1784 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1785 case OP_INDEXL
: break;
1786 default: goto illegal
;
1789 switch (code
->opcode
) {
1790 case O (O_MOVAB
, SL
): break;
1791 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1792 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1793 default: goto illegal
;
1796 ea
= ea
+ code
->src
.literal
;
1798 if (store (sd
, &code
->op3
, ea
))
1803 case O (O_SUBX
, SB
): /* subx, extended sub */
1804 if (fetch2 (sd
, &code
->dst
, &rd
))
1806 if (fetch (sd
, &code
->src
, &ea
))
1812 case O (O_SUBX
, SW
): /* subx, extended sub */
1813 if (fetch2 (sd
, &code
->dst
, &rd
))
1815 if (fetch (sd
, &code
->src
, &ea
))
1821 case O (O_SUBX
, SL
): /* subx, extended sub */
1822 if (fetch2 (sd
, &code
->dst
, &rd
))
1824 if (fetch (sd
, &code
->src
, &ea
))
1830 case O (O_ADDX
, SB
): /* addx, extended add */
1831 if (fetch2 (sd
, &code
->dst
, &rd
))
1833 if (fetch (sd
, &code
->src
, &ea
))
1839 case O (O_ADDX
, SW
): /* addx, extended add */
1840 if (fetch2 (sd
, &code
->dst
, &rd
))
1842 if (fetch (sd
, &code
->src
, &ea
))
1848 case O (O_ADDX
, SL
): /* addx, extended add */
1849 if (fetch2 (sd
, &code
->dst
, &rd
))
1851 if (fetch (sd
, &code
->src
, &ea
))
1857 case O (O_SUB
, SB
): /* sub.b */
1858 /* Fetch rd and ea. */
1859 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1865 case O (O_SUB
, SW
): /* sub.w */
1866 /* Fetch rd and ea. */
1867 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1873 case O (O_SUB
, SL
): /* sub.l */
1874 /* Fetch rd and ea. */
1875 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1881 case O (O_NEG
, SB
): /* neg.b */
1883 if (fetch2 (sd
, &code
->src
, &ea
))
1890 case O (O_NEG
, SW
): /* neg.w */
1892 if (fetch2 (sd
, &code
->src
, &ea
))
1899 case O (O_NEG
, SL
): /* neg.l */
1901 if (fetch2 (sd
, &code
->src
, &ea
))
1908 case O (O_ADD
, SB
): /* add.b */
1909 if (fetch2 (sd
, &code
->dst
, &rd
))
1911 if (fetch (sd
, &code
->src
, &ea
))
1916 case O (O_ADD
, SW
): /* add.w */
1917 if (fetch2 (sd
, &code
->dst
, &rd
))
1919 if (fetch (sd
, &code
->src
, &ea
))
1924 case O (O_ADD
, SL
): /* add.l */
1925 if (fetch2 (sd
, &code
->dst
, &rd
))
1927 if (fetch (sd
, &code
->src
, &ea
))
1932 case O (O_AND
, SB
): /* and.b */
1933 /* Fetch rd and ea. */
1934 if (fetch2 (sd
, &code
->dst
, &rd
) || fetch (sd
, &code
->src
, &ea
))
1939 case O (O_AND
, SW
): /* and.w */
1940 /* Fetch rd and ea. */
1941 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1946 case O (O_AND
, SL
): /* and.l */
1947 /* Fetch rd and ea. */
1948 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1953 case O (O_OR
, SB
): /* or.b */
1954 /* Fetch rd and ea. */
1955 if (fetch2 (sd
, &code
->dst
, &rd
) || fetch (sd
, &code
->src
, &ea
))
1960 case O (O_OR
, SW
): /* or.w */
1961 /* Fetch rd and ea. */
1962 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1967 case O (O_OR
, SL
): /* or.l */
1968 /* Fetch rd and ea. */
1969 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1974 case O (O_XOR
, SB
): /* xor.b */
1975 /* Fetch rd and ea. */
1976 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1981 case O (O_XOR
, SW
): /* xor.w */
1982 /* Fetch rd and ea. */
1983 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1988 case O (O_XOR
, SL
): /* xor.l */
1989 /* Fetch rd and ea. */
1990 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1996 if (fetch (sd
, &code
->src
, &res
))
1998 if (store (sd
, &code
->dst
, res
))
2000 goto just_flags_log8
;
2002 if (fetch (sd
, &code
->src
, &res
))
2004 if (store (sd
, &code
->dst
, res
))
2006 goto just_flags_log16
;
2008 if (fetch (sd
, &code
->src
, &res
))
2010 if (store (sd
, &code
->dst
, res
))
2012 goto just_flags_log32
;
2014 case O (O_MOVMD
, SB
): /* movmd.b */
2021 rd
= GET_MEMORY_B (GET_L_REG (5));
2022 SET_MEMORY_B (GET_L_REG (6), rd
);
2023 SET_L_REG (5, GET_L_REG (5) + 1);
2024 SET_L_REG (6, GET_L_REG (6) + 1);
2029 case O (O_MOVMD
, SW
): /* movmd.w */
2036 rd
= GET_MEMORY_W (GET_L_REG (5));
2037 SET_MEMORY_W (GET_L_REG (6), rd
);
2038 SET_L_REG (5, GET_L_REG (5) + 2);
2039 SET_L_REG (6, GET_L_REG (6) + 2);
2044 case O (O_MOVMD
, SL
): /* movmd.l */
2051 rd
= GET_MEMORY_L (GET_L_REG (5));
2052 SET_MEMORY_L (GET_L_REG (6), rd
);
2053 SET_L_REG (5, GET_L_REG (5) + 4);
2054 SET_L_REG (6, GET_L_REG (6) + 4);
2059 case O (O_MOVSD
, SB
): /* movsd.b */
2060 /* This instruction implements strncpy, with a conditional branch.
2061 r4 contains n, r5 contains src, and r6 contains dst.
2062 The 16-bit displacement operand is added to the pc
2063 if and only if the end of string is reached before
2064 n bytes are transferred. */
2066 ea
= GET_L_REG (4) & 0xffff;
2072 rd
= GET_MEMORY_B (GET_L_REG (5));
2073 SET_MEMORY_B (GET_L_REG (6), rd
);
2074 SET_L_REG (5, GET_L_REG (5) + 1);
2075 SET_L_REG (6, GET_L_REG (6) + 1);
2082 case O (O_EEPMOV
, SB
): /* eepmov.b */
2083 case O (O_EEPMOV
, SW
): /* eepmov.w */
2084 if (h8300hmode
|| h8300smode
)
2086 register unsigned char *_src
, *_dst
;
2087 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2088 ? h8_get_reg (cpu
, R4_REGNUM
) & 0xffff
2089 : h8_get_reg (cpu
, R4_REGNUM
) & 0xff);
2091 _src
= h8_get_memory_buf (cpu
) + h8_get_reg (cpu
, R5_REGNUM
);
2092 if ((_src
+ count
) >= (h8_get_memory_buf (cpu
) + memory_size
))
2094 _dst
= h8_get_memory_buf (cpu
) + h8_get_reg (cpu
, R6_REGNUM
);
2095 if ((_dst
+ count
) >= (h8_get_memory_buf (cpu
) + memory_size
))
2097 memcpy (_dst
, _src
, count
);
2099 h8_set_reg (cpu
, R5_REGNUM
, h8_get_reg (cpu
, R5_REGNUM
) + count
);
2100 h8_set_reg (cpu
, R6_REGNUM
, h8_get_reg (cpu
, R6_REGNUM
) + count
);
2101 h8_set_reg (cpu
, R4_REGNUM
, h8_get_reg (cpu
, R4_REGNUM
) &
2102 ((code
->opcode
== O (O_EEPMOV
, SW
))
2103 ? (~0xffff) : (~0xff)));
2104 cycles
+= 2 * count
;
2109 case O (O_ADDS
, SL
): /* adds (.l) */
2111 * This insn only uses register operands, but still
2112 * it would be cleaner to use fetch and store... */
2113 SET_L_REG (code
->dst
.reg
,
2114 GET_L_REG (code
->dst
.reg
)
2115 + code
->src
.literal
);
2119 case O (O_SUBS
, SL
): /* subs (.l) */
2121 * This insn only uses register operands, but still
2122 * it would be cleaner to use fetch and store... */
2123 SET_L_REG (code
->dst
.reg
,
2124 GET_L_REG (code
->dst
.reg
)
2125 - code
->src
.literal
);
2128 case O (O_CMP
, SB
): /* cmp.b */
2129 if (fetch (sd
, &code
->dst
, &rd
))
2131 if (fetch (sd
, &code
->src
, &ea
))
2135 goto just_flags_alu8
;
2137 case O (O_CMP
, SW
): /* cmp.w */
2138 if (fetch (sd
, &code
->dst
, &rd
))
2140 if (fetch (sd
, &code
->src
, &ea
))
2144 goto just_flags_alu16
;
2146 case O (O_CMP
, SL
): /* cmp.l */
2147 if (fetch (sd
, &code
->dst
, &rd
))
2149 if (fetch (sd
, &code
->src
, &ea
))
2153 goto just_flags_alu32
;
2155 case O (O_DEC
, SB
): /* dec.b */
2157 * This insn only uses register operands, but still
2158 * it would be cleaner to use fetch and store... */
2159 rd
= GET_B_REG (code
->src
.reg
);
2162 SET_B_REG (code
->src
.reg
, res
);
2163 goto just_flags_inc8
;
2165 case O (O_DEC
, SW
): /* dec.w */
2167 * This insn only uses register operands, but still
2168 * it would be cleaner to use fetch and store... */
2169 rd
= GET_W_REG (code
->dst
.reg
);
2170 ea
= -code
->src
.literal
;
2172 SET_W_REG (code
->dst
.reg
, res
);
2173 goto just_flags_inc16
;
2175 case O (O_DEC
, SL
): /* dec.l */
2177 * This insn only uses register operands, but still
2178 * it would be cleaner to use fetch and store... */
2179 rd
= GET_L_REG (code
->dst
.reg
);
2180 ea
= -code
->src
.literal
;
2182 SET_L_REG (code
->dst
.reg
, res
);
2183 goto just_flags_inc32
;
2185 case O (O_INC
, SB
): /* inc.b */
2187 * This insn only uses register operands, but still
2188 * it would be cleaner to use fetch and store... */
2189 rd
= GET_B_REG (code
->src
.reg
);
2192 SET_B_REG (code
->src
.reg
, res
);
2193 goto just_flags_inc8
;
2195 case O (O_INC
, SW
): /* inc.w */
2197 * This insn only uses register operands, but still
2198 * it would be cleaner to use fetch and store... */
2199 rd
= GET_W_REG (code
->dst
.reg
);
2200 ea
= code
->src
.literal
;
2202 SET_W_REG (code
->dst
.reg
, res
);
2203 goto just_flags_inc16
;
2205 case O (O_INC
, SL
): /* inc.l */
2207 * This insn only uses register operands, but still
2208 * it would be cleaner to use fetch and store... */
2209 rd
= GET_L_REG (code
->dst
.reg
);
2210 ea
= code
->src
.literal
;
2212 SET_L_REG (code
->dst
.reg
, res
);
2213 goto just_flags_inc32
;
2215 case O (O_LDC
, SB
): /* ldc.b */
2216 if (fetch (sd
, &code
->src
, &res
))
2220 case O (O_LDC
, SW
): /* ldc.w */
2221 if (fetch (sd
, &code
->src
, &res
))
2224 /* Word operand, value from MSB, must be shifted. */
2228 case O (O_LDC
, SL
): /* ldc.l */
2229 if (fetch (sd
, &code
->src
, &res
))
2231 switch (code
->dst
.type
) {
2232 case X (OP_SBR
, SL
):
2233 h8_set_sbr (cpu
, res
);
2235 case X (OP_VBR
, SL
):
2236 h8_set_vbr (cpu
, res
);
2243 case O (O_STC
, SW
): /* stc.w */
2244 case O (O_STC
, SB
): /* stc.b */
2245 if (code
->src
.type
== X (OP_CCR
, SB
))
2248 res
= h8_get_ccr (cpu
);
2250 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2253 h8_set_exr (cpu
, (trace
<< 7) | intMask
);
2254 res
= h8_get_exr (cpu
);
2259 /* Word operand, value to MSB, must be shifted. */
2260 if (code
->opcode
== X (O_STC
, SW
))
2262 if (store (sd
, &code
->dst
, res
))
2265 case O (O_STC
, SL
): /* stc.l */
2266 switch (code
->src
.type
) {
2267 case X (OP_SBR
, SL
):
2268 res
= h8_get_sbr (cpu
);
2270 case X (OP_VBR
, SL
):
2271 res
= h8_get_vbr (cpu
);
2276 if (store (sd
, &code
->dst
, res
))
2280 case O (O_ANDC
, SB
): /* andc.b */
2281 if (code
->dst
.type
== X (OP_CCR
, SB
))
2284 rd
= h8_get_ccr (cpu
);
2286 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2289 h8_set_exr (cpu
, (trace
<< 7) | intMask
);
2290 rd
= h8_get_exr (cpu
);
2294 ea
= code
->src
.literal
;
2298 case O (O_ORC
, SB
): /* orc.b */
2299 if (code
->dst
.type
== X (OP_CCR
, SB
))
2302 rd
= h8_get_ccr (cpu
);
2304 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2307 h8_set_exr (cpu
, (trace
<< 7) | intMask
);
2308 rd
= h8_get_exr (cpu
);
2312 ea
= code
->src
.literal
;
2316 case O (O_XORC
, SB
): /* xorc.b */
2317 if (code
->dst
.type
== X (OP_CCR
, SB
))
2320 rd
= h8_get_ccr (cpu
);
2322 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2325 h8_set_exr (cpu
, (trace
<< 7) | intMask
);
2326 rd
= h8_get_exr (cpu
);
2330 ea
= code
->src
.literal
;
2334 case O (O_BRAS
, SB
): /* bra/s */
2335 /* This is basically an ordinary branch, with a delay slot. */
2336 if (fetch (sd
, &code
->src
, &res
))
2344 /* Execution continues at next instruction, but
2345 delayed_branch is set up for next cycle. */
2346 h8_set_delayed_branch (cpu
, code
->next_pc
+ res
);
2350 case O (O_BRAB
, SB
): /* bra rd.b */
2351 case O (O_BRAW
, SW
): /* bra rd.w */
2352 case O (O_BRAL
, SL
): /* bra erd.l */
2353 if (fetch (sd
, &code
->src
, &rd
))
2355 switch (OP_SIZE (code
->opcode
)) {
2356 case SB
: rd
&= 0xff; break;
2357 case SW
: rd
&= 0xffff; break;
2358 case SL
: rd
&= 0xffffffff; break;
2360 pc
= code
->next_pc
+ rd
;
2363 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2364 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2365 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2366 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2367 if (fetch (sd
, &code
->dst
, &rd
) ||
2368 fetch (sd
, &code
->src
, &bit
))
2371 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2372 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2374 if ((rd
& (1 << bit
))) /* no branch */
2377 else /* branch/call if set */
2379 if (!(rd
& (1 << bit
))) /* no branch */
2383 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2385 pc
= code
->next_pc
+ res
;
2387 if (code
->opcode
== O (O_BRABC
, SB
) ||
2388 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2396 case O (O_BRA
, SB
): /* bra, branch always */
2401 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2406 case O (O_BHI
, SB
): /* bhi */
2412 case O (O_BLS
, SB
): /* bls */
2417 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2422 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2427 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2431 case O (O_BGT
, SB
): /* bgt */
2432 if (((Z
|| (N
^ V
)) == 0))
2436 case O (O_BLE
, SB
): /* ble */
2437 if (((Z
|| (N
^ V
)) == 1))
2441 case O (O_BGE
, SB
): /* bge */
2445 case O (O_BLT
, SB
): /* blt */
2449 case O (O_BMI
, SB
): /* bmi */
2453 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2458 case O (O_BPL
, SB
): /* bpl */
2462 case O (O_BVC
, SB
): /* bvc */
2466 case O (O_BVS
, SB
): /* bvs */
2471 /* Trap for Command Line setup. */
2472 case O (O_SYS_CMDLINE
, SB
):
2474 int i
= 0; /* Loop counter. */
2475 int j
= 0; /* Loop counter. */
2476 int ind_arg_len
= 0; /* Length of each argument. */
2477 int no_of_args
= 0; /* The no. or cmdline args. */
2478 int current_location
= 0; /* Location of string. */
2479 int old_sp
= 0; /* The Initial Stack Pointer. */
2480 int no_of_slots
= 0; /* No. of slots required on the stack
2481 for storing cmdline args. */
2482 int sp_move
= 0; /* No. of locations by which the stack needs
2484 int new_sp
= 0; /* The final stack pointer location passed
2486 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2487 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2488 args on the stack. */
2489 int char_ptr_size
= 0; /* Size of a character pointer on
2491 int addr_cmdline
= 0; /* Memory location where cmdline has
2493 int size_cmdline
= 0; /* Size of cmdline. */
2495 /* Set the address of 256 free locations where command line is
2497 addr_cmdline
= cmdline_location();
2498 h8_set_reg (cpu
, 0, addr_cmdline
);
2500 /* Counting the no. of commandline arguments. */
2501 for (i
= 0; h8_get_cmdline_arg (cpu
, i
) != NULL
; i
++)
2504 /* No. of arguments in the command line. */
2507 /* Current location is just a temporary variable,which we are
2508 setting to the point to the start of our commandline string. */
2509 current_location
= addr_cmdline
;
2511 /* Allocating space for storing pointers of the command line
2513 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2515 /* Setting char_ptr_size to the sizeof (char *) on the different
2517 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2526 for (i
= 0; i
< no_of_args
; i
++)
2530 /* The size of the commandline argument. */
2531 ind_arg_len
= strlen (h8_get_cmdline_arg (cpu
, i
)) + 1;
2533 /* The total size of the command line string. */
2534 size_cmdline
+= ind_arg_len
;
2536 /* As we have only 256 bytes, we need to provide a graceful
2537 exit. Anyways, a program using command line arguments
2538 where we cannot store all the command line arguments
2539 given may behave unpredictably. */
2540 if (size_cmdline
>= 256)
2542 h8_set_reg (cpu
, 0, 0);
2547 /* current_location points to the memory where the next
2548 commandline argument is stored. */
2549 argv_ptrs
[i
] = current_location
;
2550 for (j
= 0; j
< ind_arg_len
; j
++)
2552 SET_MEMORY_B ((current_location
+
2553 (sizeof (char) * j
)),
2554 *(h8_get_cmdline_arg (cpu
, i
) +
2555 sizeof (char) * j
));
2558 /* Setting current_location to the starting of next
2560 current_location
+= ind_arg_len
;
2564 /* This is the original position of the stack pointer. */
2565 old_sp
= h8_get_reg (cpu
, SP_REGNUM
);
2567 /* We need space from the stack to store the pointers to argvs. */
2568 /* As we will infringe on the stack, we need to shift the stack
2569 pointer so that the data is not overwritten. We calculate how
2570 much space is required. */
2571 sp_move
= (no_of_args
) * (char_ptr_size
);
2573 /* The final position of stack pointer, we have thus taken some
2574 space from the stack. */
2575 new_sp
= old_sp
- sp_move
;
2577 /* Temporary variable holding value where the argv pointers need
2579 argv_ptrs_location
= new_sp
;
2581 /* The argv pointers are stored at sequential locations. As per
2583 for (i
= 0; i
< no_of_args
; i
++)
2585 /* Saving the argv pointer. */
2586 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2588 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2592 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2595 /* The next location where the pointer to the next argv
2596 string has to be stored. */
2597 argv_ptrs_location
+= char_ptr_size
;
2600 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2602 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2604 SET_MEMORY_L (old_sp
, 0x0);
2608 SET_MEMORY_W (old_sp
, 0x0);
2611 /* Freeing allocated memory. */
2613 for (i
= 0; i
<= no_of_args
; i
++)
2615 free (h8_get_cmdline_arg (cpu
, i
));
2617 free (h8_get_command_line (cpu
));
2619 /* The no. of argv arguments are returned in Reg 0. */
2620 h8_set_reg (cpu
, 0, no_of_args
);
2621 /* The Pointer to argv in Register 1. */
2622 h8_set_reg (cpu
, 1, new_sp
);
2623 /* Setting the stack pointer to the new value. */
2624 h8_set_reg (cpu
, SP_REGNUM
, new_sp
);
2628 /* System call processing starts. */
2629 case O (O_SYS_OPEN
, SB
):
2631 int len
= 0; /* Length of filename. */
2632 char *filename
; /* Filename would go here. */
2633 char temp_char
; /* Temporary character */
2634 int mode
= 0; /* Mode bits for the file. */
2635 int open_return
; /* Return value of open, file descriptor. */
2636 int i
; /* Loop counter */
2637 int filename_ptr
; /* Pointer to filename in cpu memory. */
2639 /* Setting filename_ptr to first argument of open, */
2640 /* and trying to get mode. */
2641 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2643 filename_ptr
= GET_L_REG (0);
2644 mode
= GET_MEMORY_L (h8_get_reg (cpu
, SP_REGNUM
) + 4);
2648 filename_ptr
= GET_W_REG (0);
2649 mode
= GET_MEMORY_W (h8_get_reg (cpu
, SP_REGNUM
) + 2);
2652 /* Trying to find the length of the filename. */
2653 temp_char
= GET_MEMORY_B (h8_get_reg (cpu
, 0));
2656 while (temp_char
!= '\0')
2658 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2662 /* Allocating space for the filename. */
2663 filename
= (char *) malloc (sizeof (char) * len
);
2665 /* String copying the filename from memory. */
2666 for (i
= 0; i
< len
; i
++)
2668 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2669 filename
[i
] = temp_char
;
2672 /* Callback to open and return the file descriptor. */
2673 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2675 /* Return value in register 0. */
2676 h8_set_reg (cpu
, 0, open_return
);
2678 /* Freeing memory used for filename. */
2683 case O (O_SYS_READ
, SB
):
2685 char *char_ptr
; /* Where characters read would be stored. */
2686 int fd
; /* File descriptor */
2687 int buf_size
; /* BUF_SIZE parameter in read. */
2688 int i
= 0; /* Temporary Loop counter */
2689 int read_return
= 0; /* Return value from callback to
2692 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2693 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2695 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2697 /* Callback to read and return the no. of characters read. */
2699 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2701 /* The characters read are stored in cpu memory. */
2702 for (i
= 0; i
< buf_size
; i
++)
2704 SET_MEMORY_B ((h8_get_reg (cpu
, 1) + (sizeof (char) * i
)),
2705 *(char_ptr
+ (sizeof (char) * i
)));
2708 /* Return value in Register 0. */
2709 h8_set_reg (cpu
, 0, read_return
);
2711 /* Freeing memory used as buffer. */
2716 case O (O_SYS_WRITE
, SB
):
2718 int fd
; /* File descriptor */
2719 char temp_char
; /* Temporary character */
2720 int len
; /* Length of write, Parameter II to write. */
2721 int char_ptr
; /* Character Pointer, Parameter I of write. */
2722 char *ptr
; /* Where characters to be written are stored.
2724 int write_return
; /* Return value from callback to write. */
2725 int i
= 0; /* Loop counter */
2727 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2728 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2729 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2731 /* Allocating space for the characters to be written. */
2732 ptr
= (char *) malloc (sizeof (char) * len
);
2734 /* Fetching the characters from cpu memory. */
2735 for (i
= 0; i
< len
; i
++)
2737 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2741 /* Callback write and return the no. of characters written. */
2742 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2744 /* Return value in Register 0. */
2745 h8_set_reg (cpu
, 0, write_return
);
2747 /* Freeing memory used as buffer. */
2752 case O (O_SYS_LSEEK
, SB
):
2754 int fd
; /* File descriptor */
2755 int offset
; /* Offset */
2756 int origin
; /* Origin */
2757 int lseek_return
; /* Return value from callback to lseek. */
2759 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2760 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2761 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2763 /* Callback lseek and return offset. */
2765 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2767 /* Return value in register 0. */
2768 h8_set_reg (cpu
, 0, lseek_return
);
2772 case O (O_SYS_CLOSE
, SB
):
2774 int fd
; /* File descriptor */
2775 int close_return
; /* Return value from callback to close. */
2777 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2779 /* Callback close and return. */
2780 close_return
= sim_callback
->close (sim_callback
, fd
);
2782 /* Return value in register 0. */
2783 h8_set_reg (cpu
, 0, close_return
);
2787 case O (O_SYS_FSTAT
, SB
):
2789 int fd
; /* File descriptor */
2790 struct stat stat_rec
; /* Stat record */
2791 int fstat_return
; /* Return value from callback to stat. */
2792 int stat_ptr
; /* Pointer to stat record. */
2793 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2795 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2797 /* Setting stat_ptr to second argument of stat. */
2798 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2800 /* Callback stat and return. */
2801 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
2804 /* Have stat_ptr point to starting of stat_rec. */
2805 temp_stat_ptr
= (char *) (&stat_rec
);
2807 /* Setting up the stat structure returned. */
2808 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2810 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2812 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2814 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2816 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2818 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2820 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2822 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2824 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2826 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2828 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2830 /* Return value in register 0. */
2831 h8_set_reg (cpu
, 0, fstat_return
);
2835 case O (O_SYS_STAT
, SB
):
2837 int len
= 0; /* Length of filename. */
2838 char *filename
; /* Filename would go here. */
2839 char temp_char
; /* Temporary character */
2840 int filename_ptr
; /* Pointer to filename in cpu memory. */
2841 struct stat stat_rec
; /* Stat record */
2842 int stat_return
; /* Return value from callback to stat */
2843 int stat_ptr
; /* Pointer to stat record. */
2844 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2845 int i
= 0; /* Loop Counter */
2847 /* Setting filename_ptr to first argument of open. */
2848 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2850 /* Trying to find the length of the filename. */
2851 temp_char
= GET_MEMORY_B (h8_get_reg (cpu
, 0));
2854 while (temp_char
!= '\0')
2856 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2860 /* Allocating space for the filename. */
2861 filename
= (char *) malloc (sizeof (char) * len
);
2863 /* String copying the filename from memory. */
2864 for (i
= 0; i
< len
; i
++)
2866 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2867 filename
[i
] = temp_char
;
2870 /* Setting stat_ptr to second argument of stat. */
2871 /* stat_ptr = h8_get_reg (cpu, 1); */
2872 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2874 /* Callback stat and return. */
2876 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
2878 /* Have stat_ptr point to starting of stat_rec. */
2879 temp_stat_ptr
= (char *) (&stat_rec
);
2881 /* Freeing memory used for filename. */
2884 /* Setting up the stat structure returned. */
2885 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2887 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2889 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2891 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2893 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2895 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2897 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2899 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2901 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2903 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2905 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2907 /* Return value in register 0. */
2908 h8_set_reg (cpu
, 0, stat_return
);
2911 /* End of system call processing. */
2913 case O (O_NOT
, SB
): /* not.b */
2914 if (fetch2 (sd
, &code
->src
, &rd
))
2920 case O (O_NOT
, SW
): /* not.w */
2921 if (fetch2 (sd
, &code
->src
, &rd
))
2927 case O (O_NOT
, SL
): /* not.l */
2928 if (fetch2 (sd
, &code
->src
, &rd
))
2934 case O (O_SHLL
, SB
): /* shll.b */
2935 case O (O_SHLR
, SB
): /* shlr.b */
2936 if (fetch2 (sd
, &code
->dst
, &rd
))
2939 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
2940 ea
= 1; /* unary op */
2941 else /* binary op */
2942 fetch (sd
, &code
->src
, &ea
);
2944 if (code
->opcode
== O (O_SHLL
, SB
))
2947 c
= rd
& (0x80 >> (ea
- 1));
2953 c
= rd
& (1 << (ea
- 1));
2954 rd
= (unsigned char) rd
>> ea
;
2958 case O (O_SHLL
, SW
): /* shll.w */
2959 case O (O_SHLR
, SW
): /* shlr.w */
2960 if (fetch2 (sd
, &code
->dst
, &rd
))
2963 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
2964 ea
= 1; /* unary op */
2966 fetch (sd
, &code
->src
, &ea
);
2968 if (code
->opcode
== O (O_SHLL
, SW
))
2971 c
= rd
& (0x8000 >> (ea
- 1));
2977 c
= rd
& (1 << (ea
- 1));
2978 rd
= (unsigned short) rd
>> ea
;
2982 case O (O_SHLL
, SL
): /* shll.l */
2983 case O (O_SHLR
, SL
): /* shlr.l */
2984 if (fetch2 (sd
, &code
->dst
, &rd
))
2987 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
2988 ea
= 1; /* unary op */
2990 fetch (sd
, &code
->src
, &ea
);
2992 if (code
->opcode
== O (O_SHLL
, SL
))
2995 c
= rd
& (0x80000000 >> (ea
- 1));
3001 c
= rd
& (1 << (ea
- 1));
3002 rd
= (unsigned int) rd
>> ea
;
3006 case O (O_SHAL
, SB
):
3007 case O (O_SHAR
, SB
):
3008 if (fetch2 (sd
, &code
->dst
, &rd
))
3011 if (code
->src
.type
== X (OP_IMM
, SB
))
3012 fetch (sd
, &code
->src
, &ea
);
3016 if (code
->opcode
== O (O_SHAL
, SB
))
3018 c
= rd
& (0x80 >> (ea
- 1));
3019 res
= rd
>> (7 - ea
);
3020 v
= ((res
& 1) && !(res
& 2))
3021 || (!(res
& 1) && (res
& 2));
3026 c
= rd
& (1 << (ea
- 1));
3028 rd
= ((signed char) rd
) >> ea
;
3032 case O (O_SHAL
, SW
):
3033 case O (O_SHAR
, SW
):
3034 if (fetch2 (sd
, &code
->dst
, &rd
))
3037 if (code
->src
.type
== X (OP_IMM
, SW
))
3038 fetch (sd
, &code
->src
, &ea
);
3042 if (code
->opcode
== O (O_SHAL
, SW
))
3044 c
= rd
& (0x8000 >> (ea
- 1));
3045 res
= rd
>> (15 - ea
);
3046 v
= ((res
& 1) && !(res
& 2))
3047 || (!(res
& 1) && (res
& 2));
3052 c
= rd
& (1 << (ea
- 1));
3054 rd
= ((signed short) rd
) >> ea
;
3058 case O (O_SHAL
, SL
):
3059 case O (O_SHAR
, SL
):
3060 if (fetch2 (sd
, &code
->dst
, &rd
))
3063 if (code
->src
.type
== X (OP_IMM
, SL
))
3064 fetch (sd
, &code
->src
, &ea
);
3068 if (code
->opcode
== O (O_SHAL
, SL
))
3070 c
= rd
& (0x80000000 >> (ea
- 1));
3071 res
= rd
>> (31 - ea
);
3072 v
= ((res
& 1) && !(res
& 2))
3073 || (!(res
& 1) && (res
& 2));
3078 c
= rd
& (1 << (ea
- 1));
3080 rd
= ((signed int) rd
) >> ea
;
3084 case O (O_ROTL
, SB
):
3085 case O (O_ROTR
, SB
):
3086 if (fetch2 (sd
, &code
->dst
, &rd
))
3089 if (code
->src
.type
== X (OP_IMM
, SB
))
3090 fetch (sd
, &code
->src
, &ea
);
3095 if (code
->opcode
== O (O_ROTL
, SB
))
3105 rd
= ((unsigned char) rd
) >> 1;
3113 case O (O_ROTL
, SW
):
3114 case O (O_ROTR
, SW
):
3115 if (fetch2 (sd
, &code
->dst
, &rd
))
3118 if (code
->src
.type
== X (OP_IMM
, SW
))
3119 fetch (sd
, &code
->src
, &ea
);
3124 if (code
->opcode
== O (O_ROTL
, SW
))
3134 rd
= ((unsigned short) rd
) >> 1;
3142 case O (O_ROTL
, SL
):
3143 case O (O_ROTR
, SL
):
3144 if (fetch2 (sd
, &code
->dst
, &rd
))
3147 if (code
->src
.type
== X (OP_IMM
, SL
))
3148 fetch (sd
, &code
->src
, &ea
);
3153 if (code
->opcode
== O (O_ROTL
, SL
))
3155 c
= rd
& 0x80000000;
3163 rd
= ((unsigned int) rd
) >> 1;
3171 case O (O_ROTXL
, SB
):
3172 case O (O_ROTXR
, SB
):
3173 if (fetch2 (sd
, &code
->dst
, &rd
))
3176 if (code
->src
.type
== X (OP_IMM
, SB
))
3177 fetch (sd
, &code
->src
, &ea
);
3182 if (code
->opcode
== O (O_ROTXL
, SB
))
3193 rd
= ((unsigned char) rd
) >> 1;
3202 case O (O_ROTXL
, SW
):
3203 case O (O_ROTXR
, SW
):
3204 if (fetch2 (sd
, &code
->dst
, &rd
))
3207 if (code
->src
.type
== X (OP_IMM
, SW
))
3208 fetch (sd
, &code
->src
, &ea
);
3213 if (code
->opcode
== O (O_ROTXL
, SW
))
3224 rd
= ((unsigned short) rd
) >> 1;
3233 case O (O_ROTXL
, SL
):
3234 case O (O_ROTXR
, SL
):
3235 if (fetch2 (sd
, &code
->dst
, &rd
))
3238 if (code
->src
.type
== X (OP_IMM
, SL
))
3239 fetch (sd
, &code
->src
, &ea
);
3244 if (code
->opcode
== O (O_ROTXL
, SL
))
3246 res
= rd
& 0x80000000;
3255 rd
= ((unsigned int) rd
) >> 1;
3266 case O (O_JMP
, SB
): /* jmp */
3268 fetch (sd
, &code
->src
, &pc
);
3273 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3275 if (fetch (sd
, &code
->src
, &pc
))
3278 tmp
= h8_get_reg (cpu
, SP_REGNUM
);
3280 if (h8300hmode
&& !h8300_normal_mode
)
3283 SET_MEMORY_L (tmp
, code
->next_pc
);
3288 SET_MEMORY_W (tmp
, code
->next_pc
);
3290 h8_set_reg (cpu
, SP_REGNUM
, tmp
);
3296 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3297 if (fetch (sd
, &code
->src
, &res
))
3299 pc
= code
->next_pc
+ res
;
3302 case O (O_RTE
, SN
): /* rte, return from exception */
3304 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3305 tmp
= h8_get_reg (cpu
, SP_REGNUM
);
3307 if (h8300smode
) /* pop exr */
3309 h8_set_exr (cpu
, GET_MEMORY_L (tmp
));
3312 if (h8300hmode
&& !h8300_normal_mode
)
3314 h8_set_ccr (cpu
, GET_MEMORY_L (tmp
));
3316 pc
= GET_MEMORY_L (tmp
);
3321 h8_set_ccr (cpu
, GET_MEMORY_W (tmp
));
3323 pc
= GET_MEMORY_W (tmp
);
3328 h8_set_reg (cpu
, SP_REGNUM
, tmp
);
3331 case O (O_RTS
, SN
): /* rts, return from subroutine */
3333 tmp
= h8_get_reg (cpu
, SP_REGNUM
);
3335 if (h8300hmode
&& !h8300_normal_mode
)
3337 pc
= GET_MEMORY_L (tmp
);
3342 pc
= GET_MEMORY_W (tmp
);
3346 h8_set_reg (cpu
, SP_REGNUM
, tmp
);
3349 case O (O_ILL
, SB
): /* illegal */
3350 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
3353 case O (O_SLEEP
, SN
): /* sleep */
3354 /* Check for magic numbers in r1 and r2. */
3355 if ((h8_get_reg (cpu
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3356 (h8_get_reg (cpu
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3357 SIM_WIFEXITED (h8_get_reg (cpu
, 0)))
3359 /* This trap comes from _exit, not from gdb. */
3360 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_exited
,
3361 SIM_WEXITSTATUS (h8_get_reg (cpu
, 0)));
3364 /* Unfortunately this won't really work, because
3365 when we take a breakpoint trap, R0 has a "random",
3366 user-defined value. Don't see any immediate solution. */
3367 else if (SIM_WIFSTOPPED (h8_get_reg (cpu
, 0)))
3369 /* Pass the stop signal up to gdb. */
3370 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
,
3371 SIM_WSTOPSIG (h8_get_reg (cpu
, 0)));
3376 /* Treat it as a sigtrap. */
3377 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3381 case O (O_TRAPA
, SB
): /* trapa */
3382 if (fetch (sd
, &code
->src
, &res
))
3383 goto end
; /* res is vector number. */
3385 tmp
= h8_get_reg (cpu
, SP_REGNUM
);
3386 if(h8300_normal_mode
)
3389 SET_MEMORY_W (tmp
, code
->next_pc
);
3391 SET_MEMORY_W (tmp
, h8_get_ccr (cpu
));
3396 SET_MEMORY_L (tmp
, code
->next_pc
);
3398 SET_MEMORY_L (tmp
, h8_get_ccr (cpu
));
3406 SET_MEMORY_L (tmp
, h8_get_exr (cpu
));
3409 h8_set_reg (cpu
, SP_REGNUM
, tmp
);
3411 if(h8300_normal_mode
)
3412 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3414 pc
= GET_MEMORY_L (0x20 + res
* 4);
3418 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3421 case O (O_BSETEQ
, SB
):
3426 case O (O_BSETNE
, SB
):
3431 case O (O_BCLREQ
, SB
):
3436 case O (O_BCLRNE
, SB
):
3441 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3442 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3444 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3446 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3447 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3448 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3449 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3450 if (C
) ea
|= m
); /* bst */
3451 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3452 if (!C
) ea
|= m
); /* bist */
3453 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3454 if (Z
) ea
|= m
); /* bstz */
3455 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3456 if (!Z
) ea
|= m
); /* bistz */
3457 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3458 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3459 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3460 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3461 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3462 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3464 case O (O_BFLD
, SB
): /* bfld */
3467 if (fetch (sd
, &code
->src
, &bit
))
3472 if (fetch (sd
, &code
->dst
, &ea
))
3482 if (store (sd
, &code
->op3
, ea
))
3487 case O(O_BFST
, SB
): /* bfst */
3488 /* bitfield store */
3489 /* NOTE: the imm8 value is in dst, and the ea value
3490 (which is actually the destination) is in op3.
3491 It has to be that way, to avoid breaking the assembler. */
3493 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3495 if (bit
== 0) /* noop -- nothing to do. */
3498 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3501 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3504 /* Left-shift the register data into position. */
3505 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3508 /* Combine it with the neighboring bits. */
3509 ea
= (ea
& ~bit
) | (rd
& bit
);
3512 if (store2 (sd
, &code
->op3
, ea
))
3516 case O (O_CLRMAC
, SN
): /* clrmac */
3517 h8_set_mach (cpu
, 0);
3518 h8_set_macl (cpu
, 0);
3519 h8_set_macZ (cpu
, 1);
3520 h8_set_macV (cpu
, 0);
3521 h8_set_macN (cpu
, 0);
3524 case O (O_STMAC
, SL
): /* stmac, 260 */
3525 switch (code
->src
.type
) {
3526 case X (OP_MACH
, SL
):
3527 res
= h8_get_mach (cpu
);
3528 if (res
& 0x200) /* sign extend */
3531 case X (OP_MACL
, SL
):
3532 res
= h8_get_macl (cpu
);
3534 default: goto illegal
;
3536 nz
= !h8_get_macZ (cpu
);
3537 n
= h8_get_macN (cpu
);
3538 v
= h8_get_macV (cpu
);
3540 if (store (sd
, &code
->dst
, res
))
3545 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3546 if (fetch (sd
, &code
->src
, &rd
))
3549 switch (code
->dst
.type
) {
3550 case X (OP_MACH
, SL
):
3551 rd
&= 0x3ff; /* Truncate to 10 bits */
3552 h8_set_mach (cpu
, rd
);
3554 case X (OP_MACL
, SL
):
3555 h8_set_macl (cpu
, rd
);
3557 default: goto illegal
;
3559 h8_set_macV (cpu
, 0);
3563 if (fetch (sd
, &code
->src
, &rd
) ||
3564 fetch (sd
, &code
->dst
, &res
))
3567 /* Ye gods, this is non-portable!
3568 However, the existing mul/div code is similar. */
3569 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3571 if (h8_get_macS (cpu
)) /* Saturating mode */
3573 long long mac
= h8_get_macl (cpu
);
3575 if (mac
& 0x80000000) /* sign extend */
3576 mac
|= 0xffffffff00000000LL
;
3579 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3580 h8_set_macV (cpu
, 1);
3581 h8_set_macZ (cpu
, (mac
== 0));
3582 h8_set_macN (cpu
, (mac
< 0));
3583 h8_set_macl (cpu
, (int) mac
);
3585 else /* "Less Saturating" mode */
3587 long long mac
= h8_get_mach (cpu
);
3589 mac
+= h8_get_macl (cpu
);
3591 if (mac
& 0x20000000000LL
) /* sign extend */
3592 mac
|= 0xfffffc0000000000LL
;
3595 if (mac
> 0x1ffffffffffLL
||
3596 mac
< (long long) 0xfffffe0000000000LL
)
3597 h8_set_macV (cpu
, 1);
3598 h8_set_macZ (cpu
, (mac
== 0));
3599 h8_set_macN (cpu
, (mac
< 0));
3600 h8_set_macl (cpu
, (int) mac
);
3602 h8_set_mach (cpu
, (int) (mac
& 0x3ff));
3606 case O (O_MULS
, SW
): /* muls.w */
3607 if (fetch (sd
, &code
->src
, &ea
) ||
3608 fetch (sd
, &code
->dst
, &rd
))
3611 ea
= SEXTSHORT (ea
);
3612 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3616 if (store (sd
, &code
->dst
, res
))
3621 case O (O_MULS
, SL
): /* muls.l */
3622 if (fetch (sd
, &code
->src
, &ea
) ||
3623 fetch (sd
, &code
->dst
, &rd
))
3628 n
= res
& 0x80000000;
3629 nz
= res
& 0xffffffff;
3630 if (store (sd
, &code
->dst
, res
))
3634 case O (O_MULSU
, SL
): /* muls/u.l */
3635 if (fetch (sd
, &code
->src
, &ea
) ||
3636 fetch (sd
, &code
->dst
, &rd
))
3639 /* Compute upper 32 bits of the 64-bit result. */
3640 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3642 n
= res
& 0x80000000;
3643 nz
= res
& 0xffffffff;
3644 if (store (sd
, &code
->dst
, res
))
3648 case O (O_MULU
, SW
): /* mulu.w */
3649 if (fetch (sd
, &code
->src
, &ea
) ||
3650 fetch (sd
, &code
->dst
, &rd
))
3653 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3655 /* Don't set Z or N. */
3656 if (store (sd
, &code
->dst
, res
))
3661 case O (O_MULU
, SL
): /* mulu.l */
3662 if (fetch (sd
, &code
->src
, &ea
) ||
3663 fetch (sd
, &code
->dst
, &rd
))
3668 /* Don't set Z or N. */
3669 if (store (sd
, &code
->dst
, res
))
3674 case O (O_MULUU
, SL
): /* mulu/u.l */
3675 if (fetch (sd
, &code
->src
, &ea
) ||
3676 fetch (sd
, &code
->dst
, &rd
))
3679 /* Compute upper 32 bits of the 64-bit result. */
3680 res
= (((unsigned long long) (unsigned) ea
) *
3681 ((unsigned long long) (unsigned) rd
)) >> 32;
3683 /* Don't set Z or N. */
3684 if (store (sd
, &code
->dst
, res
))
3689 case O (O_MULXS
, SB
): /* mulxs.b */
3690 if (fetch (sd
, &code
->src
, &ea
) ||
3691 fetch (sd
, &code
->dst
, &rd
))
3695 res
= ea
* SEXTCHAR (rd
);
3699 if (store (sd
, &code
->dst
, res
))
3704 case O (O_MULXS
, SW
): /* mulxs.w */
3705 if (fetch (sd
, &code
->src
, &ea
) ||
3706 fetch (sd
, &code
->dst
, &rd
))
3709 ea
= SEXTSHORT (ea
);
3710 res
= ea
* SEXTSHORT (rd
& 0xffff);
3712 n
= res
& 0x80000000;
3713 nz
= res
& 0xffffffff;
3714 if (store (sd
, &code
->dst
, res
))
3719 case O (O_MULXU
, SB
): /* mulxu.b */
3720 if (fetch (sd
, &code
->src
, &ea
) ||
3721 fetch (sd
, &code
->dst
, &rd
))
3724 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3726 if (store (sd
, &code
->dst
, res
))
3731 case O (O_MULXU
, SW
): /* mulxu.w */
3732 if (fetch (sd
, &code
->src
, &ea
) ||
3733 fetch (sd
, &code
->dst
, &rd
))
3736 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3738 if (store (sd
, &code
->dst
, res
))
3743 case O (O_TAS
, SB
): /* tas (test and set) */
3744 if (!h8300sxmode
) /* h8sx can use any register. */
3745 switch (code
->src
.reg
)
3756 if (fetch (sd
, &code
->src
, &res
))
3758 if (store (sd
, &code
->src
, res
| 0x80))
3761 goto just_flags_log8
;
3763 case O (O_DIVU
, SW
): /* divu.w */
3764 if (fetch (sd
, &code
->src
, &ea
) ||
3765 fetch (sd
, &code
->dst
, &rd
))
3771 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
3775 if (store (sd
, &code
->dst
, res
))
3779 case O (O_DIVU
, SL
): /* divu.l */
3780 if (fetch (sd
, &code
->src
, &ea
) ||
3781 fetch (sd
, &code
->dst
, &rd
))
3784 n
= ea
& 0x80000000;
3785 nz
= ea
& 0xffffffff;
3787 res
= (unsigned) rd
/ ea
;
3791 if (store (sd
, &code
->dst
, res
))
3795 case O (O_DIVS
, SW
): /* divs.w */
3796 if (fetch (sd
, &code
->src
, &ea
) ||
3797 fetch (sd
, &code
->dst
, &rd
))
3802 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
3812 if (store (sd
, &code
->dst
, res
))
3816 case O (O_DIVS
, SL
): /* divs.l */
3817 if (fetch (sd
, &code
->src
, &ea
) ||
3818 fetch (sd
, &code
->dst
, &rd
))
3832 n
= res
& 0x80000000;
3833 if (store (sd
, &code
->dst
, res
))
3837 case O (O_DIVXU
, SB
): /* divxu.b */
3838 if (fetch (sd
, &code
->src
, &ea
) ||
3839 fetch (sd
, &code
->dst
, &rd
))
3842 rd
= UEXTSHORT (rd
);
3849 tmp
= (unsigned) rd
% ea
;
3850 res
= (unsigned) rd
/ ea
;
3858 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3862 case O (O_DIVXU
, SW
): /* divxu.w */
3863 if (fetch (sd
, &code
->src
, &ea
) ||
3864 fetch (sd
, &code
->dst
, &rd
))
3867 ea
= UEXTSHORT (ea
);
3873 tmp
= (unsigned) rd
% ea
;
3874 res
= (unsigned) rd
/ ea
;
3882 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3886 case O (O_DIVXS
, SB
): /* divxs.b */
3887 if (fetch (sd
, &code
->src
, &ea
) ||
3888 fetch (sd
, &code
->dst
, &rd
))
3891 rd
= SEXTSHORT (rd
);
3896 tmp
= (int) rd
% (int) ea
;
3897 res
= (int) rd
/ (int) ea
;
3908 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3912 case O (O_DIVXS
, SW
): /* divxs.w */
3913 if (fetch (sd
, &code
->src
, &ea
) ||
3914 fetch (sd
, &code
->dst
, &rd
))
3917 ea
= SEXTSHORT (ea
);
3921 tmp
= (int) rd
% (int) ea
;
3922 res
= (int) rd
/ (int) ea
;
3932 n
= res
& 0x80000000;
3933 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3937 case O (O_EXTS
, SW
): /* exts.w, signed extend */
3938 if (fetch2 (sd
, &code
->dst
, &rd
))
3940 ea
= rd
& 0x80 ? -256 : 0;
3941 res
= (rd
& 0xff) + ea
;
3944 case O (O_EXTS
, SL
): /* exts.l, signed extend */
3945 if (fetch2 (sd
, &code
->dst
, &rd
))
3947 if (code
->src
.type
== X (OP_IMM
, SL
))
3949 if (fetch (sd
, &code
->src
, &ea
))
3952 if (ea
== 2) /* exts.l #2, nn */
3954 /* Sign-extend from 8-bit to 32-bit. */
3955 ea
= rd
& 0x80 ? -256 : 0;
3956 res
= (rd
& 0xff) + ea
;
3960 /* Sign-extend from 16-bit to 32-bit. */
3961 ea
= rd
& 0x8000 ? -65536 : 0;
3962 res
= (rd
& 0xffff) + ea
;
3965 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
3966 if (fetch2 (sd
, &code
->dst
, &rd
))
3969 res
= (rd
& 0xff) + ea
;
3972 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
3973 if (fetch2 (sd
, &code
->dst
, &rd
))
3975 if (code
->src
.type
== X (OP_IMM
, SL
))
3977 if (fetch (sd
, &code
->src
, &ea
))
3980 if (ea
== 2) /* extu.l #2, nn */
3982 /* Zero-extend from 8-bit to 32-bit. */
3984 res
= (rd
& 0xff) + ea
;
3988 /* Zero-extend from 16-bit to 32-bit. */
3990 res
= (rd
& 0xffff) + ea
;
3993 case O (O_NOP
, SN
): /* nop */
3996 case O (O_STM
, SL
): /* stm, store to memory */
3998 int nregs
, firstreg
, i
;
4000 nregs
= GET_MEMORY_B (pc
+ 1);
4003 firstreg
= code
->src
.reg
;
4005 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4007 h8_set_reg (cpu
, SP_REGNUM
, h8_get_reg (cpu
, SP_REGNUM
) - 4);
4008 SET_MEMORY_L (h8_get_reg (cpu
, SP_REGNUM
), h8_get_reg (cpu
, i
));
4013 case O (O_LDM
, SL
): /* ldm, load from memory */
4014 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4015 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4017 int nregs
, firstreg
, i
;
4019 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4020 firstreg
= code
->dst
.reg
& 0xf;
4021 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4023 h8_set_reg (cpu
, i
, GET_MEMORY_L (h8_get_reg (cpu
, SP_REGNUM
)));
4024 h8_set_reg (cpu
, SP_REGNUM
, h8_get_reg (cpu
, SP_REGNUM
) + 4);
4027 switch (code
->opcode
) {
4028 case O (O_RTEL
, SN
):
4030 case O (O_RTSL
, SN
):
4039 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4040 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4041 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4042 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4043 /* Nothing. */; /* Value added == 0. */
4044 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4045 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4046 res
= res
+ 0x6; /* Value added == 6. */
4047 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4048 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4049 res
= res
+ 0x6; /* Value added == 6. */
4050 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4051 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4052 res
= res
+ 0x60; /* Value added == 60. */
4053 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4054 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4055 res
= res
+ 0x66; /* Value added == 66. */
4056 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4057 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4058 res
= res
+ 0x66; /* Value added == 66. */
4059 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4060 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4061 res
= res
+ 0x60; /* Value added == 60. */
4062 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4063 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4064 res
= res
+ 0x66; /* Value added == 66. */
4065 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4066 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4067 res
= res
+ 0x66; /* Value added == 66. */
4072 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4073 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4074 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4075 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4076 /* Nothing. */; /* Value added == 0. */
4077 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4078 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4079 res
= res
+ 0xfa; /* Value added == 0xfa. */
4080 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4081 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4082 res
= res
+ 0xa0; /* Value added == 0xa0. */
4083 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4084 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4085 res
= res
+ 0x9a; /* Value added == 0x9a. */
4091 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4096 sim_io_printf (sd
, "sim_resume: internal error.\n");
4097 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4101 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4102 code
->dst
.type
== X (OP_CCR
, SW
))
4104 h8_set_ccr (cpu
, res
);
4107 else if (h8300smode
&&
4108 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4109 code
->dst
.type
== X (OP_EXR
, SW
)))
4111 h8_set_exr (cpu
, res
);
4112 if (h8300smode
) /* Get exr. */
4114 trace
= (h8_get_exr (cpu
) >> 7) & 1;
4115 intMask
= h8_get_exr (cpu
) & 7;
4124 /* When a branch works */
4125 if (fetch (sd
, &code
->src
, &res
))
4127 if (res
& 1) /* bad address */
4129 pc
= code
->next_pc
+ res
;
4132 /* Set the cond codes from res */
4135 /* Set the flags after an 8 bit inc/dec operation */
4139 v
= (rd
& 0x7f) == 0x7f;
4142 /* Set the flags after an 16 bit inc/dec operation */
4146 v
= (rd
& 0x7fff) == 0x7fff;
4149 /* Set the flags after an 32 bit inc/dec operation */
4151 n
= res
& 0x80000000;
4152 nz
= res
& 0xffffffff;
4153 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4157 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4160 if (store2 (sd
, &code
->dst
, rd
))
4165 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4168 if (store2 (sd
, &code
->dst
, rd
))
4173 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4174 n
= (rd
& 0x80000000);
4175 nz
= rd
& 0xffffffff;
4176 if (store2 (sd
, &code
->dst
, rd
))
4181 if (store2 (sd
, &code
->dst
, res
))
4185 /* flags after a 32bit logical operation */
4186 n
= res
& 0x80000000;
4187 nz
= res
& 0xffffffff;
4192 if (store2 (sd
, &code
->dst
, res
))
4196 /* flags after a 16bit logical operation */
4203 if (store2 (sd
, &code
->dst
, res
))
4213 if (store2 (sd
, &code
->dst
, res
))
4220 switch (code
->opcode
/ 4)
4224 v
= ((rd
& 0x80) == (ea
& 0x80)
4225 && (rd
& 0x80) != (res
& 0x80));
4230 v
= ((rd
& 0x80) != (-ea
& 0x80)
4231 && (rd
& 0x80) != (res
& 0x80));
4238 break; /* No effect on v flag. */
4243 if (store2 (sd
, &code
->dst
, res
))
4249 c
= (res
& 0x10000);
4250 switch (code
->opcode
/ 4)
4254 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4255 && (rd
& 0x8000) != (res
& 0x8000));
4260 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4261 && (rd
& 0x8000) != (res
& 0x8000));
4270 if (store2 (sd
, &code
->dst
, res
))
4274 n
= res
& 0x80000000;
4275 nz
= res
& 0xffffffff;
4276 switch (code
->opcode
/ 4)
4280 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4281 && (rd
& 0x80000000) != (res
& 0x80000000));
4282 c
= ((unsigned) res
< (unsigned) rd
) ||
4283 ((unsigned) res
< (unsigned) ea
);
4288 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4289 && (rd
& 0x80000000) != (res
& 0x80000000));
4290 c
= (unsigned) rd
< (unsigned) -ea
;
4293 v
= (rd
== 0x80000000);
4300 if ((res
= h8_get_delayed_branch (cpu
)) != 0)
4303 h8_set_delayed_branch (cpu
, 0);
4311 h8_set_ticks (cpu
, h8_get_ticks (cpu
) + get_now () - tick_start
);
4312 h8_set_cycles (cpu
, h8_get_cycles (cpu
) + cycles
);
4313 h8_set_insts (cpu
, h8_get_insts (cpu
) + insts
);
4314 cpu_set_pc (cpu
, pc
);
4318 h8_set_exr (cpu
, (trace
<<7) | intMask
);
4320 h8_set_mask (cpu
, oldmask
);
4324 sim_engine_run (SIM_DESC sd
,
4325 int next_cpu_nr
, /* ignore */
4326 int nr_cpus
, /* ignore */
4331 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4333 cpu
= STATE_CPU (sd
, 0);
4337 step_once (sd
, cpu
);
4338 if (sim_events_tick (sd
))
4339 sim_events_process (sd
);
4344 sim_write (SIM_DESC sd
, uint64_t addr
, const void *buffer
, uint64_t size
)
4346 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
4348 const unsigned char *data
= buffer
;
4353 for (i
= 0; i
< size
; i
++)
4355 if (addr
< memory_size
)
4357 h8_set_memory (cpu
, addr
+ i
, data
[i
]);
4366 sim_read (SIM_DESC sd
, uint64_t addr
, void *buffer
, uint64_t size
)
4368 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
4373 if (addr
+ size
< memory_size
)
4374 memcpy (buffer
, h8_get_memory_buf (cpu
) + addr
, size
);
4381 h8300_reg_store (SIM_CPU
*cpu
, int rn
, const void *buf
, int length
)
4383 const unsigned char *value
= buf
;
4388 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4389 shortval
= (value
[0] << 8) | (value
[1]);
4390 intval
= h8300hmode
? longval
: shortval
;
4392 init_pointers (CPU_STATE (cpu
));
4396 if(h8300_normal_mode
)
4397 cpu_set_pc (cpu
, shortval
); /* PC for Normal mode is 2 bytes */
4399 cpu_set_pc (cpu
, intval
);
4417 h8_set_reg (cpu
, rn
, intval
);
4422 h8_set_reg (cpu
, rn
, longval
);
4429 h8300_reg_fetch (SIM_CPU
*cpu
, int rn
, void *buf
, int length
)
4431 unsigned char *value
= buf
;
4435 init_pointers (CPU_STATE (cpu
));
4437 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4444 v
= cpu_get_pc (cpu
);
4460 v
= h8_get_reg (cpu
, rn
);
4465 v
= h8_get_reg (cpu
, rn
);
4472 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4473 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4490 sim_info (SIM_DESC sd
, int verbose
)
4492 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
4493 const struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
4494 double timetaken
= (double) h8_get_ticks (cpu
) / (double) now_persec ();
4495 double virttime
= h8_get_cycles (cpu
) / 10.0e6
;
4497 sim_io_printf (sd
, "\n\n#instructions executed %10d\n", h8_get_insts (cpu
));
4498 sim_io_printf (sd
, "#cycles (v approximate) %10d\n", h8_get_cycles (cpu
));
4499 sim_io_printf (sd
, "#real time taken %10.4f\n", timetaken
);
4500 sim_io_printf (sd
, "#virtual time taken %10.4f\n", virttime
);
4501 if (timetaken
!= 0.0)
4502 sim_io_printf (sd
, "#simulation ratio %10.4f\n", virttime
/ timetaken
);
4505 /* This to be conditional on `what' (aka `verbose'),
4506 however it was never passed as non-zero. */
4510 for (i
= 0; i
< O_LAST
; i
++)
4512 if (h8_get_stats (sd
, i
))
4513 sim_io_printf (sd
, "%d: %d\n", i
, h8_get_stats (sd
, i
));
4519 /* Indicate whether the cpu is an H8/300 or H8/300H.
4520 FLAG is non-zero for the H8/300H. */
4523 set_h8300h (unsigned long machine
)
4525 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4526 This function being replaced by a sim_open:ARGV configuration
4529 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4531 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4534 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4537 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4540 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4541 h8300_normal_mode
= 1;
4544 /* H8300-specific options.
4545 TODO: These really should be merged into the common model modules. */
4553 h8300_option_handler (SIM_DESC sd
, sim_cpu
*cpu ATTRIBUTE_UNUSED
, int opt
,
4554 char *arg
, int is_command ATTRIBUTE_UNUSED
)
4556 switch ((H8300_OPTIONS
) opt
)
4559 set_h8300h (bfd_mach_h8300h
);
4562 set_h8300h (bfd_mach_h8300s
);
4564 case OPTION_H8300SX
:
4565 set_h8300h (bfd_mach_h8300sx
);
4569 /* We'll actually never get here; the caller handles the error
4571 sim_io_eprintf (sd
, "Unknown option `%s'\n", arg
);
4578 static const OPTION h8300_options
[] =
4580 { {"h8300h", no_argument
, NULL
, OPTION_H8300H
},
4581 'h', NULL
, "Indicate the CPU is H8/300H",
4582 h8300_option_handler
},
4583 { {"h8300s", no_argument
, NULL
, OPTION_H8300S
},
4584 'S', NULL
, "Indicate the CPU is H8S",
4585 h8300_option_handler
},
4586 { {"h8300sx", no_argument
, NULL
, OPTION_H8300SX
},
4587 'x', NULL
, "Indicate the CPU is H8SX",
4588 h8300_option_handler
},
4589 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
4593 h8300_pc_get (sim_cpu
*cpu
)
4595 return H8300_SIM_CPU (cpu
)->pc
;
4599 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4601 H8300_SIM_CPU (cpu
)->pc
= pc
;
4604 /* Cover function of sim_state_free to free the cpu buffers as well. */
4607 free_state (SIM_DESC sd
)
4609 if (STATE_MODULES (sd
) != NULL
)
4610 sim_module_uninstall (sd
);
4612 /* Fixme: free buffers in _sim_cpu. */
4613 sim_state_free (sd
);
4617 sim_open (SIM_OPEN_KIND kind
,
4618 struct host_callback_struct
*callback
,
4626 sd
= sim_state_alloc_extra (kind
, callback
, sizeof (struct h8300_sim_state
));
4628 /* Set default options before parsing user options. */
4629 current_target_byte_order
= BFD_ENDIAN_BIG
;
4631 /* The cpu data is kept in a separately allocated chunk of memory. */
4632 if (sim_cpu_alloc_all_extra (sd
, 1, sizeof (struct h8300_sim_cpu
))
4639 cpu
= STATE_CPU (sd
, 0);
4640 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4641 h8_set_reg (cpu
, SBR_REGNUM
, 0xFFFFFF00);
4642 /* sim_cpu object is new, so some initialization is needed. */
4643 init_pointers_needed
= 1;
4645 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4651 if (sim_add_option_table (sd
, NULL
, h8300_options
) != SIM_RC_OK
)
4657 /* The parser will print an error message for us, so we silently return. */
4658 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4660 /* Uninstall the modules to avoid memory leaks,
4661 file descriptor leaks, etc. */
4666 /* Check for/establish the a reference program image. */
4667 if (sim_analyze_program (sd
, STATE_PROG_FILE (sd
), abfd
) != SIM_RC_OK
)
4673 /* Establish any remaining configuration options. */
4674 if (sim_config (sd
) != SIM_RC_OK
)
4680 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4682 /* Uninstall the modules to avoid memory leaks,
4683 file descriptor leaks, etc. */
4688 /* CPU specific initialization. */
4689 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4691 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4693 CPU_REG_FETCH (cpu
) = h8300_reg_fetch
;
4694 CPU_REG_STORE (cpu
) = h8300_reg_store
;
4695 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4696 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4699 /* sim_hw_configure (sd); */
4701 /* FIXME: Much of the code in sim_load can be moved here. */
4706 /* Called by gdb to load a program into memory. */
4709 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4711 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
4712 struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
4715 /* FIXME: The code below that sets a specific variant of the H8/300
4716 being simulated should be moved to sim_open(). */
4718 /* See if the file is for the H8/300 or H8/300H. */
4719 /* ??? This may not be the most efficient way. The z8k simulator
4720 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4724 prog_bfd
= bfd_openr (prog
, NULL
);
4725 if (prog_bfd
!= NULL
)
4727 /* Set the cpu type. We ignore failure from bfd_check_format
4728 and bfd_openr as sim_load_file checks too. */
4729 if (bfd_check_format (prog_bfd
, bfd_object
))
4731 set_h8300h (bfd_get_mach (prog_bfd
));
4735 /* If we're using gdb attached to the simulator, then we have to
4736 reallocate memory for the simulator.
4738 When gdb first starts, it calls fetch_registers (among other
4739 functions), which in turn calls init_pointers, which allocates
4742 The problem is when we do that, we don't know whether we're
4743 debugging an H8/300 or H8/300H program.
4745 This is the first point at which we can make that determination,
4746 so we just reallocate memory now; this will also allow us to handle
4747 switching between H8/300 and H8/300H programs without exiting
4750 if (h8300smode
&& !h8300_normal_mode
)
4751 memory_size
= H8300S_MSIZE
;
4752 else if (h8300hmode
&& !h8300_normal_mode
)
4753 memory_size
= H8300H_MSIZE
;
4755 memory_size
= H8300_MSIZE
;
4757 if (h8_get_memory_buf (cpu
))
4758 free (h8_get_memory_buf (cpu
));
4760 h8_set_memory_buf (cpu
, (unsigned char *)
4761 calloc (sizeof (char), memory_size
));
4762 state
->memory_size
= memory_size
;
4764 /* `msize' must be a power of two. */
4765 if ((memory_size
& (memory_size
- 1)) != 0)
4767 sim_io_printf (sd
, "sim_load: bad memory size.\n");
4770 h8_set_mask (cpu
, memory_size
- 1);
4772 if (sim_load_file (sd
, STATE_MY_NAME (sd
), STATE_CALLBACK (sd
), prog
,
4773 prog_bfd
, STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
,
4777 /* Close the bfd if we opened it. */
4778 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4779 bfd_close (prog_bfd
);
4783 /* Close the bfd if we opened it. */
4784 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4785 bfd_close (prog_bfd
);
4790 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
4791 char * const *argv
, char * const *env
)
4793 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
4799 cpu_set_pc (cpu
, bfd_get_start_address (abfd
));
4801 cpu_set_pc (cpu
, 0);
4803 /* Command Line support. */
4806 /* Counting the no. of commandline arguments. */
4807 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
4810 /* Allocating memory for the argv pointers. */
4811 h8_set_command_line (cpu
, (char **) malloc ((sizeof (char *))
4812 * (no_of_args
+ 1)));
4814 for (i
= 0; i
< no_of_args
; i
++)
4816 /* Copying the argument string. */
4817 h8_set_cmdline_arg (cpu
, i
, (char *) strdup (argv
[i
]));
4819 h8_set_cmdline_arg (cpu
, i
, NULL
);