]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/h8300/compile.c
2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
21 #include <sys/times.h>
22 #include <sys/param.h>
25 #include "remote-sim.h"
30 #define X(op, size) op*4+size
32 #define SP (h8300hmode ? SL:SW)
45 #define h8_opcodes ops
47 #include "opcode/h8300.h"
51 #define LOW_BYTE(x) ((x) & 0xff)
52 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
53 #define P(X,Y) ((X<<8) | Y)
55 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
58 c = (cpu.ccr >> 0) & 1;\
59 v = (cpu.ccr >> 1) & 1;\
60 nz = !((cpu.ccr >> 2) & 1);\
61 n = (cpu.ccr >> 3) & 1;
63 #ifdef __CHAR_IS_SIGNED__
64 #define SEXTCHAR(x) ((char)(x))
68 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
71 #define UEXTCHAR(x) ((x) & 0xff)
72 #define UEXTSHORT(x) ((x) & 0xffff)
73 #define SEXTSHORT(x) ((short)(x))
75 static cpu_state_type cpu
;
88 return b
.tms_utime
+ b
.tms_stime
;
111 return h8300hmode
? SL
: SW
;
124 return X (OP_IMM
, SP
);
126 return X (OP_REG
, SP
);
130 return X (OP_MEM
, SP
);
137 decode (addr
, data
, dst
)
149 struct h8_opcode
*q
= h8_opcodes
;
153 /* Find the exact opcode/arg combo */
157 unsigned int len
= 0;
163 op_type looking_for
= *nib
;
164 int thisnib
= data
[len
>> 1];
166 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
168 if (looking_for
< 16 && looking_for
>= 0)
170 if (looking_for
!= thisnib
)
175 if ((int) looking_for
& (int) B31
)
177 if (!(((int) thisnib
& 0x8) != 0))
179 looking_for
= (op_type
) ((int) looking_for
& ~(int)
183 if ((int) looking_for
& (int) B30
)
185 if (!(((int) thisnib
& 0x8) == 0))
187 looking_for
= (op_type
) ((int) looking_for
& ~(int) B30
);
189 if (looking_for
& DBIT
)
191 if ((looking_for
& 5) != (thisnib
& 5))
193 abs
= (thisnib
& 0x8) ? 2 : 1;
195 else if (looking_for
& (REG
| IND
| INC
| DEC
))
197 if (looking_for
& REG
)
200 * Can work out size from the
203 size
= bitfrom (looking_for
);
205 if (looking_for
& SRC
)
214 else if (looking_for
& L_16
)
216 abs
= (data
[len
>> 1]) * 256 + data
[(len
+ 2) >> 1];
218 if (looking_for
& (PCREL
| DISP
))
223 else if (looking_for
& ABSJMP
)
230 else if (looking_for
& MEMIND
)
234 else if (looking_for
& L_32
)
237 abs
= (data
[i
] << 24)
238 | (data
[i
+ 1] << 16)
244 else if (looking_for
& L_24
)
247 abs
= (data
[i
] << 16) | (data
[i
+ 1] << 8) | (data
[i
+ 2]);
250 else if (looking_for
& IGNORE
)
254 else if (looking_for
& DISPREG
)
256 rdisp
= thisnib
& 0x7;
258 else if (looking_for
& KBIT
)
273 else if (looking_for
& L_8
)
277 if (looking_for
& PCREL
)
279 abs
= SEXTCHAR (data
[len
>> 1]);
283 abs
= data
[len
>> 1] & 0xff;
286 else if (looking_for
& L_3
)
292 else if (looking_for
== E
)
296 /* Fill in the args */
298 op_type
*args
= q
->args
.nib
;
304 int rn
= (x
& DST
) ? rd
: rs
;
316 if (x
& (IMM
| KBIT
| DBIT
))
318 p
->type
= X (OP_IMM
, size
);
323 /* Reset the size, some
324 ops (like mul) have two sizes */
327 p
->type
= X (OP_REG
, size
);
332 p
->type
= X (OP_INC
, size
);
337 p
->type
= X (OP_DEC
, size
);
342 p
->type
= X (OP_DISP
, size
);
346 else if (x
& (ABS
| ABSJMP
| ABSMOV
))
348 p
->type
= X (OP_DISP
, size
);
354 p
->type
= X (OP_MEM
, size
);
359 p
->type
= X (OP_PCREL
, size
);
360 p
->literal
= abs
+ addr
+ 2;
366 p
->type
= X (OP_IMM
, SP
);
371 p
->type
= X (OP_DISP
, size
);
373 p
->reg
= rdisp
& 0x7;
380 printf ("Hmmmm %x", x
);
387 * But a jmp or a jsr gets
388 * automagically lvalued, since we
389 * branch to their address not their
392 if (q
->how
== O (O_JSR
, SB
)
393 || q
->how
== O (O_JMP
, SB
))
395 dst
->src
.type
= lvalue (dst
->src
.type
, dst
->src
.reg
);
398 if (dst
->dst
.type
== -1)
401 dst
->opcode
= q
->how
;
402 dst
->cycles
= q
->time
;
404 /* And a jsr to 0xc4 is turned into a magic trap */
406 if (dst
->opcode
== O (O_JSR
, SB
))
408 if (dst
->src
.literal
== 0xc4)
410 dst
->opcode
= O (O_SYSCALL
, SB
);
414 dst
->next_pc
= addr
+ len
/ 2;
419 printf ("Dont understand %x \n", looking_for
);
431 dst
->opcode
= O (O_ILL
, SB
);
440 /* find the next cache entry to use */
442 idx
= cpu
.cache_top
+ 1;
444 if (idx
>= cpu
.csize
)
450 /* Throw away its old meaning */
451 cpu
.cache_idx
[cpu
.cache
[idx
].oldpc
] = 0;
453 /* set to new address */
454 cpu
.cache
[idx
].oldpc
= pc
;
456 /* fill in instruction info */
457 decode (pc
, cpu
.memory
+ pc
, cpu
.cache
+ idx
);
459 /* point to new cache entry */
460 cpu
.cache_idx
[pc
] = idx
;
464 static unsigned char *breg
[18];
465 static unsigned short *wreg
[18];
466 static unsigned int *lreg
[18];
468 #define GET_B_REG(x) *(breg[x])
469 #define SET_B_REG(x,y) (*(breg[x])) = (y)
470 #define GET_W_REG(x) *(wreg[x])
471 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
473 #define GET_L_REG(x) *(lreg[x])
474 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
476 #define GET_MEMORY_L(x) \
477 ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3])
479 #define GET_MEMORY_W(x) \
480 ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0))
483 #define SET_MEMORY_B(x,y) \
484 (cpu.memory[(x)] = y)
486 #define SET_MEMORY_W(x,y) \
487 {register unsigned char *_p = cpu.memory+x;\
488 register int __y = y;\
492 #define SET_MEMORY_L(x,y) \
493 {register unsigned char *_p = cpu.memory+x;register int __y = y;\
494 _p[0] = (__y)>>24; _p[1] = (__y)>>16; _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
496 #define GET_MEMORY_B(x) (cpu.memory[x])
503 int abs
= arg
->literal
;
510 return GET_B_REG (rn
);
512 return GET_W_REG (rn
);
514 return GET_L_REG (rn
);
525 r
= GET_MEMORY_B (t
);
534 r
= GET_MEMORY_W (t
);
542 r
= GET_MEMORY_L (t
);
549 case X (OP_DISP
, SB
):
550 t
= GET_L_REG (rn
) + abs
;
552 return GET_MEMORY_B (t
);
554 case X (OP_DISP
, SW
):
555 t
= GET_L_REG (rn
) + abs
;
557 return GET_MEMORY_W (t
);
559 case X (OP_DISP
, SL
):
560 t
= GET_L_REG (rn
) + abs
;
562 return GET_MEMORY_L (t
);
565 t
= GET_MEMORY_L (abs
);
583 int abs
= arg
->literal
;
599 t
= GET_L_REG (rn
) - 1;
606 t
= (GET_L_REG (rn
) - 2) & cpu
.mask
;
612 t
= (GET_L_REG (rn
) - 4) & cpu
.mask
;
617 case X (OP_DISP
, SB
):
618 t
= GET_L_REG (rn
) + abs
;
623 case X (OP_DISP
, SW
):
624 t
= GET_L_REG (rn
) + abs
;
629 case X (OP_DISP
, SL
):
630 t
= GET_L_REG (rn
) + abs
;
666 cpu
.memory
= (unsigned char *) calloc (sizeof (char), MSIZE
);
667 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), MSIZE
);
668 cpu
.mask
= (1 << MPOWER
) - 1;
670 for (i
= 0; i
< 9; i
++)
675 for (i
= 0; i
< 8; i
++)
677 unsigned char *p
= (unsigned char *) (cpu
.regs
+ i
);
678 unsigned char *e
= (unsigned char *) (cpu
.regs
+ i
+ 1);
679 unsigned short *q
= (unsigned short *) (cpu
.regs
+ i
);
680 unsigned short *u
= (unsigned short *) (cpu
.regs
+ i
+ 1);
681 cpu
.regs
[i
] = 0x00112233;
707 lreg
[i
] = &cpu
.regs
[i
];
710 lreg
[8] = &cpu
.regs
[8];
712 /* initialize the seg registers */
719 control_c (sig
, code
, scp
, addr
)
725 cpu
.exception
= SIGINT
;
734 mop (code
, bsize
, sign
)
747 bsize
? SEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
748 SEXTSHORT (GET_W_REG (code
->dst
.reg
));
750 bsize
? SEXTCHAR (GET_B_REG (code
->src
.reg
)) :
751 SEXTSHORT (GET_W_REG (code
->src
.reg
));
755 multiplicand
= bsize
? UEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
756 UEXTSHORT (GET_W_REG (code
->dst
.reg
));
758 bsize
? UEXTCHAR (GET_B_REG (code
->src
.reg
)) :
759 UEXTSHORT (GET_W_REG (code
->src
.reg
));
762 result
= multiplier
* multiplicand
;
766 n
= result
& (bsize
? 0x8000 : 0x80000000);
767 nz
= result
& (bsize
? 0xffff : 0xffffffff);
771 SET_W_REG (code
->dst
.reg
, result
);
775 SET_L_REG (code
->dst
.reg
, result
);
777 /* return ((n==1) << 1) | (nz==1); */
781 #define OSHIFTS(name, how) \
786 rd = GET_B_REG (code->src.reg); \
794 rd = GET_W_REG (code->src.reg); \
801 int hm = 0x80000000; \
802 rd = GET_L_REG (code->src.reg); \
807 #define OBITOP(name,f, s, op) \
812 if (f) ea = fetch (&code->dst); \
813 m=1<< fetch(&code->src); \
815 if(s) store (&code->dst,ea); goto next; \
819 sim_resume (step
, siggnal
)
824 int tick_start
= get_now ();
837 prev
= signal (SIGINT
, control_c
);
841 cpu
.exception
= SIGTRAP
;
858 cidx
= cpu
.cache_idx
[pc
];
859 code
= cpu
.cache
+ cidx
;
862 #define ALUOP(STORE, NAME, HOW) \
863 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
864 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
865 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
868 #define LOGOP(NAME, HOW) \
869 case O(NAME,SB): HOW; goto log8;\
870 case O(NAME, SW): HOW; goto log16;\
871 case O(NAME,SL): HOW; goto log32;
878 printf ("%x %d %s\n", pc
, code
->opcode
,
879 code
->op
? code
->op
->name
: "**");
881 cpu
.stats
[code
->opcode
]++;
885 cycles
+= code
->cycles
;
887 switch (code
->opcode
)
891 * This opcode is a fake for when we get to an
892 * instruction which hasnt been compiled
900 rd
= fetch (&code
->dst
);
901 ea
= fetch (&code
->src
);
907 rd
= fetch (&code
->dst
);
908 ea
= fetch (&code
->src
);
913 #define EA ea = fetch(&code->src);
914 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
916 ALUOP (1, O_SUB
, RD_EA
;
925 rd
= GET_B_REG (code
->dst
.reg
);
926 ea
= fetch (&code
->src
);
930 rd
= GET_W_REG (code
->dst
.reg
);
931 ea
= fetch (&code
->src
);
935 rd
= GET_L_REG (code
->dst
.reg
);
936 ea
= fetch (&code
->src
);
951 case O (O_MOV_TO_MEM
, SB
):
952 res
= GET_B_REG (code
->src
.reg
);
954 case O (O_MOV_TO_MEM
, SW
):
955 res
= GET_W_REG (code
->src
.reg
);
957 case O (O_MOV_TO_MEM
, SL
):
958 res
= GET_L_REG (code
->src
.reg
);
962 case O (O_MOV_TO_REG
, SB
):
963 res
= fetch (&code
->src
);
964 SET_B_REG (code
->dst
.reg
, res
);
965 goto just_flags_log8
;
966 case O (O_MOV_TO_REG
, SW
):
967 res
= fetch (&code
->src
);
968 SET_W_REG (code
->dst
.reg
, res
);
969 goto just_flags_log16
;
970 case O (O_MOV_TO_REG
, SL
):
971 res
= fetch (&code
->src
);
972 SET_L_REG (code
->dst
.reg
, res
);
973 goto just_flags_log32
;
977 SET_L_REG (code
->dst
.reg
,
978 GET_L_REG (code
->dst
.reg
)
979 + code
->src
.literal
);
984 SET_L_REG (code
->dst
.reg
,
985 GET_L_REG (code
->dst
.reg
)
986 - code
->src
.literal
);
990 rd
= fetch (&code
->dst
);
991 ea
= fetch (&code
->src
);
994 goto just_flags_alu8
;
997 rd
= fetch (&code
->dst
);
998 ea
= fetch (&code
->src
);
1001 goto just_flags_alu16
;
1004 rd
= fetch (&code
->dst
);
1005 ea
= fetch (&code
->src
);
1008 goto just_flags_alu32
;
1012 rd
= GET_B_REG (code
->src
.reg
);
1015 SET_B_REG (code
->src
.reg
, res
);
1016 goto just_flags_inc8
;
1019 rd
= GET_W_REG (code
->dst
.reg
);
1020 ea
= -code
->src
.literal
;
1022 SET_W_REG (code
->dst
.reg
, res
);
1023 goto just_flags_inc16
;
1026 rd
= GET_L_REG (code
->dst
.reg
);
1027 ea
= -code
->src
.literal
;
1029 SET_L_REG (code
->dst
.reg
, res
);
1030 goto just_flags_inc32
;
1034 rd
= GET_B_REG (code
->src
.reg
);
1037 SET_B_REG (code
->src
.reg
, res
);
1038 goto just_flags_inc8
;
1041 rd
= GET_W_REG (code
->dst
.reg
);
1042 ea
= code
->src
.literal
;
1044 SET_W_REG (code
->dst
.reg
, res
);
1045 goto just_flags_inc16
;
1048 rd
= GET_L_REG (code
->dst
.reg
);
1049 ea
= code
->src
.literal
;
1051 SET_L_REG (code
->dst
.reg
, res
);
1052 goto just_flags_inc32
;
1055 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1057 case O (O_ANDC
, SB
):
1059 ea
= code
->src
.literal
;
1065 ea
= code
->src
.literal
;
1069 case O (O_XORC
, SB
):
1071 ea
= code
->src
.literal
;
1112 if (((Z
|| (N
^ V
)) == 0))
1118 if (((Z
|| (N
^ V
)) == 1))
1152 case O (O_SYSCALL
, SB
):
1153 printf ("%c", cpu
.regs
[2]);
1156 OSHIFTS (O_NOT
, rd
= ~rd
);
1157 OSHIFTS (O_SHLL
, c
= rd
& hm
;
1159 OSHIFTS (O_SHLR
, c
= rd
& 1;
1160 rd
= (unsigned int) rd
>> 1);
1161 OSHIFTS (O_SHAL
, c
= rd
& hm
;
1163 OSHIFTS (O_SHAR
, t
= rd
& hm
;
1168 OSHIFTS (O_ROTL
, c
= rd
& hm
;
1171 OSHIFTS (O_ROTR
, c
= rd
& 1;
1172 rd
= (unsigned int) rd
>> 1;
1174 OSHIFTS (O_ROTXL
, t
= rd
& hm
;
1179 OSHIFTS (O_ROTXR
, t
= rd
& 1;
1180 rd
= (unsigned int) rd
>> 1;
1181 if (C
) rd
|= hm
; c
= t
;);
1185 pc
= fetch (&code
->src
);
1193 pc
= fetch (&code
->src
);
1200 SET_MEMORY_L (tmp
, code
->next_pc
);
1205 SET_MEMORY_W (tmp
, code
->next_pc
);
1212 pc
= code
->src
.literal
;
1223 pc
= GET_MEMORY_L (tmp
);
1228 pc
= GET_MEMORY_W (tmp
);
1237 cpu
.exception
= SIGILL
;
1239 case O (O_SLEEP
, SB
):
1241 cpu
.exception
= SIGTRAP
;
1244 OBITOP (O_BNOT
, 1, 1, ea
^= m
);
1245 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
);
1246 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
);
1247 OBITOP (O_BSET
, 1, 1, ea
|= m
);
1248 OBITOP (O_BLD
, 1, 0, c
= ea
& m
);
1249 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
));
1250 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
1252 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
1254 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
);
1255 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
);
1256 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
);
1257 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
);
1258 OBITOP (O_BXOR
, 1, 0, c
= (ea
& m
) != C
);
1259 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
);
1262 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1264 case O (O_MULS
, SB
):
1267 case O (O_MULS
, SW
):
1270 case O (O_MULU
, SB
):
1273 case O (O_MULU
, SW
):
1278 case O (O_DIVU
, SB
):
1280 rd
= GET_W_REG (code
->dst
.reg
);
1281 ea
= GET_B_REG (code
->src
.reg
);
1287 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1293 case O (O_DIVU
, SW
):
1295 rd
= GET_L_REG (code
->dst
.reg
);
1296 ea
= GET_W_REG (code
->src
.reg
);
1304 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1308 case O (O_DIVS
, SB
):
1311 rd
= SEXTSHORT (GET_W_REG (code
->dst
.reg
));
1312 ea
= SEXTCHAR (GET_B_REG (code
->src
.reg
));
1315 tmp
= (int) rd
% (int) ea
;
1316 rd
= (int) rd
/ (int) ea
;
1322 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1325 case O (O_DIVS
, SW
):
1327 rd
= GET_L_REG (code
->dst
.reg
);
1328 ea
= SEXTSHORT (GET_W_REG (code
->src
.reg
));
1331 tmp
= (int) rd
% (int) ea
;
1332 rd
= (int) rd
/ (int) ea
;
1333 n
= rd
& 0x80000000;
1338 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1341 case O (O_EXTS
, SW
):
1342 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff; /* Yes, src, not dst. */
1343 ea
= rd
& 0x80 ? -256 : 0;
1346 case O (O_EXTS
, SL
):
1347 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1348 ea
= rd
& 0x8000 ? -65536 : 0;
1351 case O (O_EXTU
, SW
):
1352 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff;
1356 case O (O_EXTU
, SL
):
1357 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1366 cpu
.exception
= 123;
1378 /* When a branch works */
1379 pc
= code
->src
.literal
;
1382 /* Set the cond codes from res */
1385 /* Set the flags after an 8 bit inc/dec operation */
1389 v
= (rd
& 0x7f) == 0x7f;
1393 /* Set the flags after an 16 bit inc/dec operation */
1397 v
= (rd
& 0x7fff) == 0x7fff;
1401 /* Set the flags after an 32 bit inc/dec operation */
1403 n
= res
& 0x80000000;
1404 nz
= res
& 0xffffffff;
1405 v
= (rd
& 0x7fffffff) == 0x7fffffff;
1410 /* Set flags after an 8 bit shift op, carry set in insn */
1414 SET_B_REG (code
->src
.reg
, rd
);
1419 /* Set flags after an 16 bit shift op, carry set in insn */
1424 SET_W_REG (code
->src
.reg
, rd
);
1428 /* Set flags after an 32 bit shift op, carry set in insn */
1429 n
= (rd
& 0x80000000);
1431 nz
= rd
& 0xffffffff;
1432 SET_L_REG (code
->src
.reg
, rd
);
1436 store (&code
->dst
, res
);
1438 /* flags after a 32bit logical operation */
1439 n
= res
& 0x80000000;
1440 nz
= res
& 0xffffffff;
1445 store (&code
->dst
, res
);
1447 /* flags after a 16bit logical operation */
1455 store (&code
->dst
, res
);
1463 SET_B_REG (code
->dst
.reg
, res
);
1467 v
= ((ea
& 0x80) == (rd
& 0x80)) && ((ea
& 0x80) != (res
& 0x80));
1472 SET_W_REG (code
->dst
.reg
, res
);
1476 v
= ((ea
& 0x8000) == (rd
& 0x8000)) && ((ea
& 0x8000) != (res
& 0x8000));
1477 c
= (res
& 0x10000);
1481 SET_L_REG (code
->dst
.reg
, res
);
1483 n
= res
& 0x80000000;
1484 nz
= res
& 0xffffffff;
1485 v
= ((ea
& 0x80000000) == (rd
& 0x80000000))
1486 && ((ea
& 0x80000000) != (res
& 0x80000000));
1487 switch (code
->opcode
/ 4)
1490 c
= ((unsigned) res
< (unsigned) rd
) || ((unsigned) res
< (unsigned) ea
);
1494 c
= (unsigned) rd
< (unsigned) -ea
;
1507 /* if (cpu.regs[8] ) abort(); */
1510 /* Poll after every 100th insn, */
1511 if (poll_count
++ > 100)
1523 while (!cpu
.exception
);
1524 cpu
.ticks
+= get_now () - tick_start
;
1525 cpu
.cycles
+= cycles
;
1531 signal (SIGINT
, prev
);
1536 sim_write (addr
, buffer
, size
)
1538 unsigned char *buffer
;
1544 if (addr
< 0 || addr
+ size
> MSIZE
)
1546 for (i
= 0; i
< size
; i
++)
1548 cpu
.memory
[addr
+ i
] = buffer
[i
];
1549 cpu
.cache_idx
[addr
+ i
] = 0;
1555 sim_read (addr
, buffer
, size
)
1557 unsigned char *buffer
;
1561 if (addr
< 0 || addr
+ size
> MSIZE
)
1563 memcpy (buffer
, cpu
.memory
+ addr
, size
);
1577 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1578 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1581 #define CCR_REGNUM 8 /* Contains processor status */
1582 #define PC_REGNUM 9 /* Contains program counter */
1584 #define CYCLE_REGNUM 10
1585 #define INST_REGNUM 11
1586 #define TICK_REGNUM 12
1590 sim_store_register (rn
, value
)
1592 unsigned char *value
;
1597 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
1598 shortval
= (value
[0] << 8) | (value
[1]);
1599 intval
= h8300hmode
? longval
: shortval
;
1617 cpu
.regs
[rn
] = intval
;
1623 cpu
.cycles
= longval
;
1627 cpu
.insts
= longval
;
1631 cpu
.ticks
= longval
;
1638 sim_fetch_register (rn
, buf
)
1680 if (h8300hmode
|| longreg
)
1702 sim_stop_reason (reason
, sigrc
)
1703 enum sim_stop
*reason
;
1706 *reason
= sim_stopped
;
1707 *sigrc
= cpu
.exception
;
1726 cpu
.cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
1727 memset (cpu
.cache
, 0, sizeof (decoded_inst
) * n
);
1733 sim_info (printf_fn
, verbose
)
1734 void (*printf_fn
) ();
1738 double timetaken
= (double) cpu
.ticks
/ (double) now_persec ();
1739 double virttime
= cpu
.cycles
/ 10.0e6
;
1741 printf ("\n\n#instructions executed %10d\n", cpu
.insts
);
1742 printf ("#cycles (v approximate) %10d\n", cpu
.cycles
);
1743 printf ("#real time taken %10.4f\n", timetaken
);
1744 printf ("#virtual time taked %10.4f\n", virttime
);
1745 if (timetaken
!= 0.0)
1746 printf ("#simulation ratio %10.4f\n", virttime
/ timetaken
);
1747 printf ("#compiles %10d\n", cpu
.compiles
);
1748 printf ("#cache size %10d\n", cpu
.csize
);
1755 for (i
= 0; i
< O_LAST
; i
++)
1758 printf ("%d: %d\n", i
, cpu
.stats
[i
]);
1784 sim_set_args (argv
, env
)