2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
20 /* This must come before any other includes. */
26 #ifdef HAVE_SYS_PARAM_H
27 #include <sys/param.h>
32 #include "gdb/sim-h8300.h"
34 #include "sys/types.h"
35 #include "sim-options.h"
36 #include "sim/callback.h"
44 static int memory_size
;
46 #define X(op, size) (op * 4 + size)
48 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
50 #define h8_opcodes ops
52 #include "opcode/h8300.h"
54 /* CPU data object: */
57 h8_get_pc (SIM_DESC sd
)
59 return (STATE_CPU (sd
, 0)) -> pc
;
63 h8_set_pc (SIM_DESC sd
, unsigned int val
)
65 (STATE_CPU (sd
, 0)) -> pc
= val
;
69 h8_get_ccr (SIM_DESC sd
)
71 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
75 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
77 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
81 h8_get_exr (SIM_DESC sd
)
83 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
87 h8_set_exr (SIM_DESC sd
, unsigned int val
)
89 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
93 h8_get_sbr (SIM_DESC sd
)
95 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
99 h8_set_sbr (SIM_DESC sd
, int val
)
101 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
105 h8_get_vbr (SIM_DESC sd
)
107 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
111 h8_set_vbr (SIM_DESC sd
, int val
)
113 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
117 h8_get_mask (SIM_DESC sd
)
119 return (STATE_CPU (sd
, 0)) -> mask
;
123 h8_set_mask (SIM_DESC sd
, int val
)
125 (STATE_CPU (sd
, 0)) -> mask
= val
;
129 h8_get_exception (SIM_DESC sd
)
131 return (STATE_CPU (sd
, 0)) -> exception
;
135 h8_set_exception (SIM_DESC sd
, int val
)
137 (STATE_CPU (sd
, 0)) -> exception
= val
;
140 static enum h8300_sim_state
141 h8_get_state (SIM_DESC sd
)
143 return H8300_SIM_STATE (sd
)->state
;
147 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
149 H8300_SIM_STATE (sd
)->state
= val
;
153 h8_get_cycles (SIM_DESC sd
)
155 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
159 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
161 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
165 h8_get_insts (SIM_DESC sd
)
167 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
171 h8_set_insts (SIM_DESC sd
, unsigned int val
)
173 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
177 h8_get_ticks (SIM_DESC sd
)
179 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
183 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
185 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
189 h8_get_mach (SIM_DESC sd
)
191 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
195 h8_set_mach (SIM_DESC sd
, unsigned int val
)
197 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
201 h8_get_macl (SIM_DESC sd
)
203 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
207 h8_set_macl (SIM_DESC sd
, unsigned int val
)
209 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
212 static unsigned int *
213 h8_get_reg_buf (SIM_DESC sd
)
215 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
219 h8_get_reg (SIM_DESC sd
, int regnum
)
221 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
225 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
227 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
232 h8_get_stats (SIM_DESC sd
, int idx
)
234 return H8300_SIM_STATE (sd
)->stats
[idx
];
238 h8_increment_stats (SIM_DESC sd
, int idx
)
240 H8300_SIM_STATE (sd
)->stats
[idx
] ++;
244 static unsigned char *
245 h8_get_memory_buf (SIM_DESC sd
)
247 return (STATE_CPU (sd
, 0)) -> memory
;
251 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
253 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
257 h8_get_memory (SIM_DESC sd
, int idx
)
259 ASSERT (idx
< memory_size
);
260 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
264 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
266 ASSERT (idx
< memory_size
);
267 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
271 h8_get_delayed_branch (SIM_DESC sd
)
273 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
277 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
279 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
283 h8_get_command_line (SIM_DESC sd
)
285 return (STATE_CPU (sd
, 0)) -> command_line
;
289 h8_set_command_line (SIM_DESC sd
, char ** val
)
291 (STATE_CPU (sd
, 0)) -> command_line
= val
;
295 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
297 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
301 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
303 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
306 /* MAC Saturation Mode */
308 h8_get_macS (SIM_DESC sd
)
310 return (STATE_CPU (sd
, 0)) -> macS
;
315 h8_set_macS (SIM_DESC sd
, int val
)
317 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
323 h8_get_macZ (SIM_DESC sd
)
325 return (STATE_CPU (sd
, 0)) -> macZ
;
329 h8_set_macZ (SIM_DESC sd
, int val
)
331 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
334 /* MAC Negative Flag */
336 h8_get_macN (SIM_DESC sd
)
338 return (STATE_CPU (sd
, 0)) -> macN
;
342 h8_set_macN (SIM_DESC sd
, int val
)
344 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
347 /* MAC Overflow Flag */
349 h8_get_macV (SIM_DESC sd
)
351 return (STATE_CPU (sd
, 0)) -> macV
;
355 h8_set_macV (SIM_DESC sd
, int val
)
357 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
360 /* End CPU data object. */
362 /* The rate at which to call the host's poll_quit callback. */
364 enum { POLL_QUIT_INTERVAL
= 0x80000 };
366 #define LOW_BYTE(x) ((x) & 0xff)
367 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
368 #define P(X, Y) ((X << 8) | Y)
377 #define I (intMaskBit != 0)
379 #define BUILDSR(SD) \
380 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
381 | (N << 3) | (Z << 2) | (V << 1) | C)
384 /* Get Status Register (flags). */ \
385 c = (h8_get_ccr (sd) >> 0) & 1; \
386 v = (h8_get_ccr (sd) >> 1) & 1; \
387 nz = !((h8_get_ccr (sd) >> 2) & 1); \
388 n = (h8_get_ccr (sd) >> 3) & 1; \
389 u = (h8_get_ccr (sd) >> 4) & 1; \
390 h = (h8_get_ccr (sd) >> 5) & 1; \
391 ui = ((h8_get_ccr (sd) >> 6) & 1); \
392 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
395 #ifdef __CHAR_IS_SIGNED__
396 #define SEXTCHAR(x) ((char) (x))
400 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
403 #define UEXTCHAR(x) ((x) & 0xff)
404 #define UEXTSHORT(x) ((x) & 0xffff)
405 #define SEXTSHORT(x) ((short) (x))
409 int h8300_normal_mode
= 0;
415 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
437 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
442 /* Simulate an indirection / dereference.
443 return 0 for success, -1 for failure.
447 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
449 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
451 if (val
== NULL
) /* Paranoia. */
457 if (rn
== ZERO_REGNUM
)
458 *val
= X (OP_IMM
, SP
);
460 *val
= X (OP_REG
, SP
);
463 *val
= X (OP_MEM
, SP
);
466 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
473 cmdline_location(void)
475 if (h8300smode
&& !h8300_normal_mode
)
477 else if (h8300hmode
&& !h8300_normal_mode
)
484 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
486 int cst
[3] = {0, 0, 0};
487 int reg
[3] = {0, 0, 0};
488 int rdisp
[3] = {0, 0, 0};
490 const struct h8_opcode
*q
;
495 /* Find the exact opcode/arg combo. */
496 for (q
= h8_opcodes
; q
->name
; q
++)
498 const op_type
*nib
= q
->data
.nib
;
499 unsigned int len
= 0;
501 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
502 (q
->available
== AV_H8S
&& !h8300smode
) ||
503 (q
->available
== AV_H8H
&& !h8300hmode
))
506 cst
[0] = cst
[1] = cst
[2] = 0;
507 reg
[0] = reg
[1] = reg
[2] = 0;
508 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
512 op_type looking_for
= *nib
;
513 int thisnib
= data
[len
/ 2];
515 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
516 opnum
= ((looking_for
& OP3
) ? 2 :
517 (looking_for
& DST
) ? 1 : 0);
519 if (looking_for
< 16 && looking_for
>= 0)
521 if (looking_for
!= thisnib
)
526 if (looking_for
& B31
)
528 if (!((thisnib
& 0x8) != 0))
531 looking_for
= (op_type
) (looking_for
& ~B31
);
534 else if (looking_for
& B30
)
536 if (!((thisnib
& 0x8) == 0))
539 looking_for
= (op_type
) (looking_for
& ~B30
);
542 if (looking_for
& B21
)
544 if (!((thisnib
& 0x4) != 0))
547 looking_for
= (op_type
) (looking_for
& ~B21
);
550 else if (looking_for
& B20
)
552 if (!((thisnib
& 0x4) == 0))
555 looking_for
= (op_type
) (looking_for
& ~B20
);
558 if (looking_for
& B11
)
560 if (!((thisnib
& 0x2) != 0))
563 looking_for
= (op_type
) (looking_for
& ~B11
);
566 else if (looking_for
& B10
)
568 if (!((thisnib
& 0x2) == 0))
571 looking_for
= (op_type
) (looking_for
& ~B10
);
574 if (looking_for
& B01
)
576 if (!((thisnib
& 0x1) != 0))
579 looking_for
= (op_type
) (looking_for
& ~B01
);
582 else if (looking_for
& B00
)
584 if (!((thisnib
& 0x1) == 0))
587 looking_for
= (op_type
) (looking_for
& ~B00
);
590 if (looking_for
& IGNORE
)
592 /* Hitachi has declared that IGNORE must be zero. */
596 else if ((looking_for
& MODE
) == DATA
)
598 ; /* Skip embedded data. */
600 else if ((looking_for
& MODE
) == DBIT
)
602 /* Exclude adds/subs by looking at bit 0 and 2, and
603 make sure the operand size, either w or l,
604 matches by looking at bit 1. */
605 if ((looking_for
& 7) != (thisnib
& 7))
608 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
610 else if ((looking_for
& MODE
) == REG
||
611 (looking_for
& MODE
) == LOWREG
||
612 (looking_for
& MODE
) == IND
||
613 (looking_for
& MODE
) == PREINC
||
614 (looking_for
& MODE
) == POSTINC
||
615 (looking_for
& MODE
) == PREDEC
||
616 (looking_for
& MODE
) == POSTDEC
)
618 reg
[opnum
] = thisnib
;
620 else if (looking_for
& CTRL
)
623 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
624 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
625 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
626 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
627 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
628 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
630 if (((looking_for
& MODE
) == CCR_EXR
&&
631 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
632 ((looking_for
& MODE
) == VBR_SBR
&&
633 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
634 ((looking_for
& MODE
) == MACREG
&&
635 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
637 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
638 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
639 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
642 reg
[opnum
] = thisnib
;
644 else if ((looking_for
& MODE
) == ABS
)
646 /* Absolute addresses are unsigned. */
647 switch (looking_for
& SIZE
)
650 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
654 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
658 (data
[len
/ 2 + 0] << 24) +
659 (data
[len
/ 2 + 1] << 16) +
660 (data
[len
/ 2 + 2] << 8) +
664 printf ("decode: bad size ABS: %d\n",
665 (looking_for
& SIZE
));
669 else if ((looking_for
& MODE
) == DISP
||
670 (looking_for
& MODE
) == PCREL
||
671 (looking_for
& MODE
) == INDEXB
||
672 (looking_for
& MODE
) == INDEXW
||
673 (looking_for
& MODE
) == INDEXL
)
675 switch (looking_for
& SIZE
)
678 cst
[opnum
] = thisnib
& 3;
681 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
684 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
685 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
688 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
692 (data
[len
/ 2 + 0] << 24) +
693 (data
[len
/ 2 + 1] << 16) +
694 (data
[len
/ 2 + 2] << 8) +
698 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
699 (looking_for
& SIZE
));
703 else if ((looking_for
& SIZE
) == L_16
||
704 (looking_for
& SIZE
) == L_16U
)
706 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
707 /* Immediates are always unsigned. */
708 if ((looking_for
& SIZE
) != L_16U
&&
709 (looking_for
& MODE
) != IMM
)
710 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
712 else if (looking_for
& ABSJMP
)
714 switch (looking_for
& SIZE
) {
716 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
720 (data
[len
/ 2 + 0] << 24) +
721 (data
[len
/ 2 + 1] << 16) +
722 (data
[len
/ 2 + 2] << 8) +
726 printf ("decode: bad size ABSJMP: %d\n",
727 (looking_for
& SIZE
));
731 else if ((looking_for
& MODE
) == MEMIND
)
733 cst
[opnum
] = data
[1];
735 else if ((looking_for
& MODE
) == VECIND
)
737 if(h8300_normal_mode
)
738 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
740 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
741 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
743 else if ((looking_for
& SIZE
) == L_32
)
748 (data
[i
+ 0] << 24) |
749 (data
[i
+ 1] << 16) |
753 else if ((looking_for
& SIZE
) == L_24
)
758 (data
[i
+ 0] << 16) |
762 else if (looking_for
& DISPREG
)
764 rdisp
[opnum
] = thisnib
& 0x7;
766 else if ((looking_for
& MODE
) == KBIT
)
783 else if ((looking_for
& SIZE
) == L_8
)
785 if ((looking_for
& MODE
) == ABS
)
787 /* Will be combined with contents of SBR_REGNUM
788 by fetch (). For all modes except h8sx, this
789 will always contain the value 0xFFFFFF00. */
790 cst
[opnum
] = data
[len
/ 2] & 0xff;
794 cst
[opnum
] = data
[len
/ 2] & 0xff;
797 else if ((looking_for
& SIZE
) == L_2
)
799 cst
[opnum
] = thisnib
& 3;
801 else if ((looking_for
& SIZE
) == L_3
||
802 (looking_for
& SIZE
) == L_3NZ
)
804 cst
[opnum
] = thisnib
& 7;
805 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
808 else if ((looking_for
& SIZE
) == L_4
)
810 cst
[opnum
] = thisnib
& 15;
812 else if ((looking_for
& SIZE
) == L_5
)
814 cst
[opnum
] = data
[len
/ 2] & 0x1f;
816 else if (looking_for
== E
)
821 /* Fill in the args. */
823 const op_type
*args
= q
->args
.nib
;
828 nargs
< 3 && *args
!= E
;
834 opnum
= ((x
& OP3
) ? 2 :
843 if ((x
& MODE
) == IMM
||
844 (x
& MODE
) == KBIT
||
847 /* Use the instruction to determine
849 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
850 p
->literal
= cst
[opnum
];
852 else if ((x
& MODE
) == CONST_2
||
853 (x
& MODE
) == CONST_4
||
854 (x
& MODE
) == CONST_8
||
855 (x
& MODE
) == CONST_16
)
857 /* Use the instruction to determine
859 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
861 case CONST_2
: p
->literal
= 2; break;
862 case CONST_4
: p
->literal
= 4; break;
863 case CONST_8
: p
->literal
= 8; break;
864 case CONST_16
: p
->literal
= 16; break;
867 else if ((x
& MODE
) == REG
)
869 p
->type
= X (OP_REG
, bitfrom (x
));
872 else if ((x
& MODE
) == LOWREG
)
874 p
->type
= X (OP_LOWREG
, bitfrom (x
));
877 else if ((x
& MODE
) == PREINC
)
879 /* Use the instruction to determine
881 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
882 p
->reg
= reg
[opnum
] & 0x7;
884 else if ((x
& MODE
) == POSTINC
)
886 /* Use the instruction to determine
888 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
889 p
->reg
= reg
[opnum
] & 0x7;
891 else if ((x
& MODE
) == PREDEC
)
893 /* Use the instruction to determine
895 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
896 p
->reg
= reg
[opnum
] & 0x7;
898 else if ((x
& MODE
) == POSTDEC
)
900 /* Use the instruction to determine
902 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
903 p
->reg
= reg
[opnum
] & 0x7;
905 else if ((x
& MODE
) == IND
)
907 /* Note: an indirect is transformed into
908 a displacement of zero.
910 /* Use the instruction to determine
912 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
913 p
->reg
= reg
[opnum
] & 0x7;
915 if (OP_KIND (q
->how
) == O_JSR
||
916 OP_KIND (q
->how
) == O_JMP
)
917 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
920 else if ((x
& MODE
) == ABS
)
922 /* Note: a 16 or 32 bit ABS is transformed into a
923 displacement from pseudo-register ZERO_REGNUM,
924 which is always zero. An 8 bit ABS becomes
925 a displacement from SBR_REGNUM.
927 /* Use the instruction to determine
929 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
930 p
->literal
= cst
[opnum
];
932 /* 8-bit ABS is displacement from SBR.
933 16 and 32-bit ABS are displacement from ZERO.
934 (SBR will always be zero except for h8/sx)
936 if ((x
& SIZE
) == L_8
)
939 p
->reg
= ZERO_REGNUM
;;
941 else if ((x
& MODE
) == MEMIND
||
942 (x
& MODE
) == VECIND
)
944 /* Size doesn't matter. */
945 p
->type
= X (OP_MEM
, SB
);
946 p
->literal
= cst
[opnum
];
947 if (OP_KIND (q
->how
) == O_JSR
||
948 OP_KIND (q
->how
) == O_JMP
)
949 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
952 else if ((x
& MODE
) == PCREL
)
954 /* Size doesn't matter. */
955 p
->type
= X (OP_PCREL
, SB
);
956 p
->literal
= cst
[opnum
];
960 p
->type
= X (OP_IMM
, SP
);
961 p
->literal
= cst
[opnum
];
963 else if ((x
& MODE
) == INDEXB
)
965 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
966 p
->literal
= cst
[opnum
];
967 p
->reg
= rdisp
[opnum
];
969 else if ((x
& MODE
) == INDEXW
)
971 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
972 p
->literal
= cst
[opnum
];
973 p
->reg
= rdisp
[opnum
];
975 else if ((x
& MODE
) == INDEXL
)
977 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
978 p
->literal
= cst
[opnum
];
979 p
->reg
= rdisp
[opnum
];
981 else if ((x
& MODE
) == DISP
)
983 /* Yuck -- special for mova args. */
984 if (strncmp (q
->name
, "mova", 4) == 0 &&
987 /* Mova can have a DISP2 dest, with an
988 INDEXB or INDEXW src. The multiplier
989 for the displacement value is determined
990 by the src operand, not by the insn. */
992 switch (OP_KIND (dst
->src
.type
))
995 p
->type
= X (OP_DISP
, SB
);
996 p
->literal
= cst
[opnum
];
999 p
->type
= X (OP_DISP
, SW
);
1000 p
->literal
= cst
[opnum
] * 2;
1008 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1009 p
->literal
= cst
[opnum
];
1010 /* DISP2 is special. */
1011 if ((x
& SIZE
) == L_2
)
1012 switch (OP_SIZE (q
->how
))
1015 case SW
: p
->literal
*= 2; break;
1016 case SL
: p
->literal
*= 4; break;
1019 p
->reg
= rdisp
[opnum
];
1026 p
->type
= X (OP_CCR
, SB
);
1029 p
->type
= X (OP_EXR
, SB
);
1032 p
->type
= X (OP_MACH
, SL
);
1035 p
->type
= X (OP_MACL
, SL
);
1038 p
->type
= X (OP_VBR
, SL
);
1041 p
->type
= X (OP_SBR
, SL
);
1045 else if ((x
& MODE
) == CCR
)
1049 else if ((x
& MODE
) == EXR
)
1054 printf ("Hmmmm 0x%x...\n", x
);
1060 /* Unary operators: treat src and dst as equivalent. */
1061 if (dst
->dst
.type
== -1)
1062 dst
->dst
= dst
->src
;
1063 if (dst
->src
.type
== -1)
1064 dst
->src
= dst
->dst
;
1066 dst
->opcode
= q
->how
;
1067 dst
->cycles
= q
->time
;
1069 /* And jsr's to these locations are turned into
1072 if (OP_KIND (dst
->opcode
) == O_JSR
)
1074 switch (dst
->src
.literal
)
1077 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1080 dst
->opcode
= O (O_SYS_READ
, SB
);
1083 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1086 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1089 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1092 dst
->opcode
= O (O_SYS_STAT
, SB
);
1095 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1098 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1101 /* End of Processing for system calls. */
1104 /* Use same register is specified for source
1106 The value of source will be the value after
1107 address calculation. */
1108 if (OP_KIND (dst
->opcode
) != O_CMP
&&
1109 OP_KIND (dst
->src
.type
) == OP_REG
&&
1110 (dst
->src
.reg
& 7) == dst
->dst
.reg
) {
1111 switch (OP_KIND (dst
->dst
.type
))
1114 dst
->src
.type
= X (OP_REG_DEC
,
1115 OP_SIZE (dst
->dst
.type
));
1118 dst
->src
.type
= X (OP_REG_INC
,
1119 OP_SIZE (dst
->dst
.type
));
1122 if (OP_KIND (dst
->opcode
) == O_MOV
)
1123 dst
->src
.type
= X (OP_REG_INC
,
1124 OP_SIZE (dst
->dst
.type
));
1127 if (OP_KIND (dst
->opcode
) == O_MOV
)
1128 dst
->src
.type
= X (OP_REG_DEC
,
1129 OP_SIZE (dst
->dst
.type
));
1133 dst
->next_pc
= addr
+ len
/ 2;
1137 printf ("Don't understand 0x%x \n", looking_for
);
1148 /* Fell off the end. */
1149 dst
->opcode
= O (O_ILL
, SB
);
1152 static unsigned char *breg
[32];
1153 static unsigned short *wreg
[16];
1155 #define GET_B_REG(X) *(breg[X])
1156 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1157 #define GET_W_REG(X) *(wreg[X])
1158 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1159 #define GET_L_REG(X) h8_get_reg (sd, X)
1160 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1162 #define GET_MEMORY_L(X) \
1163 ((X) < memory_size \
1164 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1165 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1168 #define GET_MEMORY_W(X) \
1169 ((X) < memory_size \
1170 ? ((h8_get_memory (sd, (X)+0) << 8) | (h8_get_memory (sd, (X)+1) << 0)) \
1173 #define GET_MEMORY_B(X) \
1174 ((X) < memory_size ? h8_get_memory (sd, (X)) : 0)
1176 #define SET_MEMORY_L(X, Y) \
1177 { register unsigned char *_p; register int __y = (Y); \
1178 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1179 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1180 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1183 #define SET_MEMORY_W(X, Y) \
1184 { register unsigned char *_p; register int __y = (Y); \
1185 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1186 _p[0] = __y >> 8; _p[1] = __y; \
1189 #define SET_MEMORY_B(X, Y) \
1190 ((X) < memory_size ? h8_set_memory (sd, (X), (Y)) : 0)
1192 /* Simulate a memory fetch.
1193 Return 0 for success, -1 for failure.
1197 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1199 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1201 int abs
= arg
->literal
;
1206 return -1; /* Paranoia. */
1210 /* Indexed register plus displacement mode:
1212 This new family of addressing modes are similar to OP_DISP
1213 (register plus displacement), with two differences:
1214 1) INDEXB uses only the least significant byte of the register,
1215 INDEXW uses only the least significant word, and
1216 INDEXL uses the entire register (just like OP_DISP).
1218 2) The displacement value in abs is multiplied by two
1219 for SW-sized operations, and by four for SL-size.
1221 This gives nine possible variations.
1224 case X (OP_INDEXB
, SB
):
1225 case X (OP_INDEXB
, SW
):
1226 case X (OP_INDEXB
, SL
):
1227 case X (OP_INDEXW
, SB
):
1228 case X (OP_INDEXW
, SW
):
1229 case X (OP_INDEXW
, SL
):
1230 case X (OP_INDEXL
, SB
):
1231 case X (OP_INDEXL
, SW
):
1232 case X (OP_INDEXL
, SL
):
1234 switch (OP_KIND (arg
->type
)) {
1235 case OP_INDEXB
: t
&= 0xff; break;
1236 case OP_INDEXW
: t
&= 0xffff; break;
1240 switch (OP_SIZE (arg
->type
)) {
1242 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1245 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1248 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1253 case X (OP_LOWREG
, SB
):
1254 *val
= GET_L_REG (rn
) & 0xff;
1256 case X (OP_LOWREG
, SW
):
1257 *val
= GET_L_REG (rn
) & 0xffff;
1260 case X (OP_REG
, SB
): /* Register direct, byte. */
1261 *val
= GET_B_REG (rn
);
1263 case X (OP_REG
, SW
): /* Register direct, word. */
1264 *val
= GET_W_REG (rn
);
1266 case X (OP_REG
, SL
): /* Register direct, long. */
1267 *val
= GET_L_REG (rn
);
1269 case X (OP_IMM
, SB
): /* Immediate, byte. */
1270 case X (OP_IMM
, SW
): /* Immediate, word. */
1271 case X (OP_IMM
, SL
): /* Immediate, long. */
1274 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1276 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1282 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1284 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1290 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1292 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1299 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1301 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1307 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1309 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1315 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1317 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1324 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1325 t
= GET_L_REG (rn
) - 1;
1327 t
&= h8_get_mask (sd
);
1328 *val
= GET_MEMORY_B (t
);
1331 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1332 t
= GET_L_REG (rn
) - 2;
1334 t
&= h8_get_mask (sd
);
1335 *val
= GET_MEMORY_W (t
);
1338 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1339 t
= GET_L_REG (rn
) - 4;
1341 t
&= h8_get_mask (sd
);
1342 *val
= GET_MEMORY_L (t
);
1345 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1346 t
= GET_L_REG (rn
) + 1;
1348 t
&= h8_get_mask (sd
);
1349 *val
= GET_MEMORY_B (t
);
1352 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1353 t
= GET_L_REG (rn
) + 2;
1355 t
&= h8_get_mask (sd
);
1356 *val
= GET_MEMORY_W (t
);
1359 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1360 t
= GET_L_REG (rn
) + 4;
1362 t
&= h8_get_mask (sd
);
1363 *val
= GET_MEMORY_L (t
);
1366 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1367 t
= GET_L_REG (rn
) + abs
;
1368 t
&= h8_get_mask (sd
);
1369 *val
= GET_MEMORY_B (t
);
1372 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1373 t
= GET_L_REG (rn
) + abs
;
1374 t
&= h8_get_mask (sd
);
1375 *val
= GET_MEMORY_W (t
);
1378 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1379 t
= GET_L_REG (rn
) + abs
;
1380 t
&= h8_get_mask (sd
);
1381 *val
=GET_MEMORY_L (t
);
1384 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1385 t
= GET_MEMORY_L (abs
);
1386 t
&= h8_get_mask (sd
);
1390 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1391 t
= GET_MEMORY_W (abs
);
1392 t
&= h8_get_mask (sd
);
1396 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1397 case X (OP_PCREL
, SW
):
1398 case X (OP_PCREL
, SL
):
1399 case X (OP_PCREL
, SN
):
1403 case X (OP_REG_DEC
, SB
): /* Register direct, affected decrement byte. */
1404 *val
= GET_B_REG (rn
) - 1;
1406 case X (OP_REG_DEC
, SW
): /* Register direct, affected decrement word. */
1407 *val
= GET_W_REG (rn
) - 2;
1409 case X (OP_REG_DEC
, SL
): /* Register direct, affected decrement long. */
1410 *val
= GET_L_REG (rn
) - 4;
1412 case X (OP_REG_INC
, SB
): /* Register direct, affected increment byte. */
1413 *val
= GET_B_REG (rn
) + 1;
1415 case X (OP_REG_INC
, SW
): /* Register direct, affected increment word. */
1416 *val
= GET_W_REG (rn
) + 2;
1418 case X (OP_REG_INC
, SL
): /* Register direct, affected increment long. */
1419 *val
= GET_L_REG (rn
) + 4;
1422 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1424 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1427 return 0; /* Success. */
1433 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1435 return fetch_1 (sd
, arg
, val
, 0);
1438 /* Fetch which will be followed by a store to the same location.
1439 The difference being that we don't want to do a post-increment
1440 or post-decrement at this time: we'll do it when we store. */
1443 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1445 return fetch_1 (sd
, arg
, val
, 1);
1448 /* Simulate a memory store.
1449 Return 0 for success, -1 for failure.
1453 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1455 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1457 int abs
= arg
->literal
;
1462 /* Indexed register plus displacement mode:
1464 This new family of addressing modes are similar to OP_DISP
1465 (register plus displacement), with two differences:
1466 1) INDEXB uses only the least significant byte of the register,
1467 INDEXW uses only the least significant word, and
1468 INDEXL uses the entire register (just like OP_DISP).
1470 2) The displacement value in abs is multiplied by two
1471 for SW-sized operations, and by four for SL-size.
1473 This gives nine possible variations.
1476 case X (OP_INDEXB
, SB
):
1477 case X (OP_INDEXB
, SW
):
1478 case X (OP_INDEXB
, SL
):
1479 case X (OP_INDEXW
, SB
):
1480 case X (OP_INDEXW
, SW
):
1481 case X (OP_INDEXW
, SL
):
1482 case X (OP_INDEXL
, SB
):
1483 case X (OP_INDEXL
, SW
):
1484 case X (OP_INDEXL
, SL
):
1486 switch (OP_KIND (arg
->type
)) {
1487 case OP_INDEXB
: t
&= 0xff; break;
1488 case OP_INDEXW
: t
&= 0xffff; break;
1492 switch (OP_SIZE (arg
->type
)) {
1494 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1497 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1500 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1505 case X (OP_REG
, SB
): /* Register direct, byte. */
1508 case X (OP_REG
, SW
): /* Register direct, word. */
1511 case X (OP_REG
, SL
): /* Register direct, long. */
1515 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1520 t
&= h8_get_mask (sd
);
1521 SET_MEMORY_B (t
, n
);
1524 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1529 t
&= h8_get_mask (sd
);
1530 SET_MEMORY_W (t
, n
);
1533 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1538 t
&= h8_get_mask (sd
);
1539 SET_MEMORY_L (t
, n
);
1542 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1547 t
&= h8_get_mask (sd
);
1548 SET_MEMORY_B (t
, n
);
1551 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1556 t
&= h8_get_mask (sd
);
1557 SET_MEMORY_W (t
, n
);
1560 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1565 t
&= h8_get_mask (sd
);
1566 SET_MEMORY_L (t
, n
);
1569 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1571 SET_L_REG (rn
, t
- 1);
1572 t
&= h8_get_mask (sd
);
1573 SET_MEMORY_B (t
, n
);
1576 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1578 SET_L_REG (rn
, t
- 2);
1579 t
&= h8_get_mask (sd
);
1580 SET_MEMORY_W (t
, n
);
1583 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1585 SET_L_REG (rn
, t
- 4);
1586 t
&= h8_get_mask (sd
);
1587 SET_MEMORY_L (t
, n
);
1590 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1592 SET_L_REG (rn
, t
+ 1);
1593 t
&= h8_get_mask (sd
);
1594 SET_MEMORY_B (t
, n
);
1597 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1599 SET_L_REG (rn
, t
+ 2);
1600 t
&= h8_get_mask (sd
);
1601 SET_MEMORY_W (t
, n
);
1604 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1606 SET_L_REG (rn
, t
+ 4);
1607 t
&= h8_get_mask (sd
);
1608 SET_MEMORY_L (t
, n
);
1611 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1612 t
= GET_L_REG (rn
) + abs
;
1613 t
&= h8_get_mask (sd
);
1614 SET_MEMORY_B (t
, n
);
1617 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1618 t
= GET_L_REG (rn
) + abs
;
1619 t
&= h8_get_mask (sd
);
1620 SET_MEMORY_W (t
, n
);
1623 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1624 t
= GET_L_REG (rn
) + abs
;
1625 t
&= h8_get_mask (sd
);
1626 SET_MEMORY_L (t
, n
);
1630 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1631 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1632 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1634 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1643 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1645 return store_1 (sd
, arg
, n
, 0);
1648 /* Store which follows a fetch from the same location.
1649 The difference being that we don't want to do a pre-increment
1650 or pre-decrement at this time: it was already done when we fetched. */
1653 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1655 return store_1 (sd
, arg
, n
, 1);
1658 /* Flag to be set whenever a new SIM_DESC object is created. */
1659 static int init_pointers_needed
= 1;
1662 init_pointers (SIM_DESC sd
)
1664 struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
1666 if (init_pointers_needed
)
1670 if (h8300smode
&& !h8300_normal_mode
)
1671 memory_size
= H8300S_MSIZE
;
1672 else if (h8300hmode
&& !h8300_normal_mode
)
1673 memory_size
= H8300H_MSIZE
;
1675 memory_size
= H8300_MSIZE
;
1676 /* `msize' must be a power of two. */
1677 if ((memory_size
& (memory_size
- 1)) != 0)
1681 "init_pointers: bad memory size %d, defaulting to %d.\n",
1682 memory_size
, H8300S_MSIZE
);
1683 memory_size
= H8300S_MSIZE
;
1686 if (h8_get_memory_buf (sd
))
1687 free (h8_get_memory_buf (sd
));
1689 h8_set_memory_buf (sd
, (unsigned char *)
1690 calloc (sizeof (char), memory_size
));
1691 state
->memory_size
= memory_size
;
1693 h8_set_mask (sd
, memory_size
- 1);
1695 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1697 for (i
= 0; i
< 8; i
++)
1699 /* FIXME: rewrite using local buffer. */
1700 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1701 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1702 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1703 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1704 h8_set_reg (sd
, i
, 0x00112233);
1719 wreg
[i
] = wreg
[i
+ 8] = 0;
1733 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1734 sim_io_printf (sd
, "init_pointers: internal error.\n");
1736 h8_set_reg (sd
, i
, 0);
1739 init_pointers_needed
= 0;
1743 #define OBITOP(name, f, s, op) \
1744 case O (name, SB): \
1749 if (fetch (sd, &code->dst, &ea)) \
1751 if (fetch (sd, &code->src, &tmp)) \
1753 m = 1 << (tmp & 7); \
1756 if (store (sd, &code->dst,ea)) \
1762 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
1766 int tick_start
= get_now ();
1773 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1777 const struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
1778 host_callback
*sim_callback
= STATE_CALLBACK (sd
);
1782 pc
= h8_get_pc (sd
);
1784 /* The PC should never be odd. */
1787 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGBUS
);
1791 /* Get Status Register (flags). */
1794 if (h8300smode
) /* Get exr. */
1796 trace
= (h8_get_exr (sd
) >> 7) & 1;
1797 intMask
= h8_get_exr (sd
) & 7;
1800 oldmask
= h8_get_mask (sd
);
1801 if (!h8300hmode
|| h8300_normal_mode
)
1802 h8_set_mask (sd
, 0xffff);
1805 decoded_inst _code
, *code
= &_code
;
1806 memset (code
, 0, sizeof (*code
));
1807 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, code
);
1813 printf ("%x %d %s\n", pc
, code
->opcode
,
1814 code
->op
? code
->op
->name
: "**");
1816 h8_increment_stats (sd
, code
->opcode
);
1821 cycles
+= code
->cycles
;
1825 switch (code
->opcode
)
1827 case O (O_MOVAB
, SL
):
1828 case O (O_MOVAW
, SL
):
1829 case O (O_MOVAL
, SL
):
1830 /* 1) Evaluate 2nd argument (dst).
1831 2) Mask / zero extend according to whether 1st argument (src)
1832 is INDEXB, INDEXW, or INDEXL.
1833 3) Left-shift the result by 0, 1 or 2, according to size of mova
1834 (mova/b, mova/w, mova/l).
1835 4) Add literal value of 1st argument (src).
1836 5) Store result in 3rd argument (op3).
1839 /* Alas, since this is the only instruction with 3 arguments,
1840 decode doesn't handle them very well. Some fix-up is required.
1842 a) The size of dst is determined by whether src is
1843 INDEXB or INDEXW. */
1845 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1846 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1847 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1848 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1850 /* b) If op3 == null, then this is the short form of the insn.
1851 Dst is the dispreg of src, and op3 is the 32-bit form
1852 of the same register.
1855 if (code
->op3
.type
== 0)
1857 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1858 We get to compose dst and op3 as follows:
1860 op3 is a 32-bit register, ID == src.reg.
1861 dst is the same register, but 8 or 16 bits
1862 depending on whether src is INDEXB or INDEXW.
1865 code
->op3
.type
= X (OP_REG
, SL
);
1866 code
->op3
.reg
= code
->src
.reg
;
1867 code
->op3
.literal
= 0;
1869 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1871 code
->dst
.type
= X (OP_REG
, SB
);
1872 code
->dst
.reg
= code
->op3
.reg
+ 8;
1875 code
->dst
.type
= X (OP_REG
, SW
);
1878 if (fetch (sd
, &code
->dst
, &ea
))
1881 switch (OP_KIND (code
->src
.type
)) {
1882 case OP_INDEXB
: ea
= ea
& 0xff; break;
1883 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1884 case OP_INDEXL
: break;
1885 default: goto illegal
;
1888 switch (code
->opcode
) {
1889 case O (O_MOVAB
, SL
): break;
1890 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1891 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1892 default: goto illegal
;
1895 ea
= ea
+ code
->src
.literal
;
1897 if (store (sd
, &code
->op3
, ea
))
1902 case O (O_SUBX
, SB
): /* subx, extended sub */
1903 if (fetch2 (sd
, &code
->dst
, &rd
))
1905 if (fetch (sd
, &code
->src
, &ea
))
1911 case O (O_SUBX
, SW
): /* subx, extended sub */
1912 if (fetch2 (sd
, &code
->dst
, &rd
))
1914 if (fetch (sd
, &code
->src
, &ea
))
1920 case O (O_SUBX
, SL
): /* subx, extended sub */
1921 if (fetch2 (sd
, &code
->dst
, &rd
))
1923 if (fetch (sd
, &code
->src
, &ea
))
1929 case O (O_ADDX
, SB
): /* addx, extended add */
1930 if (fetch2 (sd
, &code
->dst
, &rd
))
1932 if (fetch (sd
, &code
->src
, &ea
))
1938 case O (O_ADDX
, SW
): /* addx, extended add */
1939 if (fetch2 (sd
, &code
->dst
, &rd
))
1941 if (fetch (sd
, &code
->src
, &ea
))
1947 case O (O_ADDX
, SL
): /* addx, extended add */
1948 if (fetch2 (sd
, &code
->dst
, &rd
))
1950 if (fetch (sd
, &code
->src
, &ea
))
1956 case O (O_SUB
, SB
): /* sub.b */
1957 /* Fetch rd and ea. */
1958 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1964 case O (O_SUB
, SW
): /* sub.w */
1965 /* Fetch rd and ea. */
1966 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1972 case O (O_SUB
, SL
): /* sub.l */
1973 /* Fetch rd and ea. */
1974 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1980 case O (O_NEG
, SB
): /* neg.b */
1982 if (fetch2 (sd
, &code
->src
, &ea
))
1989 case O (O_NEG
, SW
): /* neg.w */
1991 if (fetch2 (sd
, &code
->src
, &ea
))
1998 case O (O_NEG
, SL
): /* neg.l */
2000 if (fetch2 (sd
, &code
->src
, &ea
))
2007 case O (O_ADD
, SB
): /* add.b */
2008 if (fetch2 (sd
, &code
->dst
, &rd
))
2010 if (fetch (sd
, &code
->src
, &ea
))
2015 case O (O_ADD
, SW
): /* add.w */
2016 if (fetch2 (sd
, &code
->dst
, &rd
))
2018 if (fetch (sd
, &code
->src
, &ea
))
2023 case O (O_ADD
, SL
): /* add.l */
2024 if (fetch2 (sd
, &code
->dst
, &rd
))
2026 if (fetch (sd
, &code
->src
, &ea
))
2031 case O (O_AND
, SB
): /* and.b */
2032 /* Fetch rd and ea. */
2033 if (fetch2 (sd
, &code
->dst
, &rd
) || fetch (sd
, &code
->src
, &ea
))
2038 case O (O_AND
, SW
): /* and.w */
2039 /* Fetch rd and ea. */
2040 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2045 case O (O_AND
, SL
): /* and.l */
2046 /* Fetch rd and ea. */
2047 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2052 case O (O_OR
, SB
): /* or.b */
2053 /* Fetch rd and ea. */
2054 if (fetch2 (sd
, &code
->dst
, &rd
) || fetch (sd
, &code
->src
, &ea
))
2059 case O (O_OR
, SW
): /* or.w */
2060 /* Fetch rd and ea. */
2061 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2066 case O (O_OR
, SL
): /* or.l */
2067 /* Fetch rd and ea. */
2068 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2073 case O (O_XOR
, SB
): /* xor.b */
2074 /* Fetch rd and ea. */
2075 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2080 case O (O_XOR
, SW
): /* xor.w */
2081 /* Fetch rd and ea. */
2082 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2087 case O (O_XOR
, SL
): /* xor.l */
2088 /* Fetch rd and ea. */
2089 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2095 if (fetch (sd
, &code
->src
, &res
))
2097 if (store (sd
, &code
->dst
, res
))
2099 goto just_flags_log8
;
2101 if (fetch (sd
, &code
->src
, &res
))
2103 if (store (sd
, &code
->dst
, res
))
2105 goto just_flags_log16
;
2107 if (fetch (sd
, &code
->src
, &res
))
2109 if (store (sd
, &code
->dst
, res
))
2111 goto just_flags_log32
;
2113 case O (O_MOVMD
, SB
): /* movmd.b */
2120 rd
= GET_MEMORY_B (GET_L_REG (5));
2121 SET_MEMORY_B (GET_L_REG (6), rd
);
2122 SET_L_REG (5, GET_L_REG (5) + 1);
2123 SET_L_REG (6, GET_L_REG (6) + 1);
2128 case O (O_MOVMD
, SW
): /* movmd.w */
2135 rd
= GET_MEMORY_W (GET_L_REG (5));
2136 SET_MEMORY_W (GET_L_REG (6), rd
);
2137 SET_L_REG (5, GET_L_REG (5) + 2);
2138 SET_L_REG (6, GET_L_REG (6) + 2);
2143 case O (O_MOVMD
, SL
): /* movmd.l */
2150 rd
= GET_MEMORY_L (GET_L_REG (5));
2151 SET_MEMORY_L (GET_L_REG (6), rd
);
2152 SET_L_REG (5, GET_L_REG (5) + 4);
2153 SET_L_REG (6, GET_L_REG (6) + 4);
2158 case O (O_MOVSD
, SB
): /* movsd.b */
2159 /* This instruction implements strncpy, with a conditional branch.
2160 r4 contains n, r5 contains src, and r6 contains dst.
2161 The 16-bit displacement operand is added to the pc
2162 if and only if the end of string is reached before
2163 n bytes are transferred. */
2165 ea
= GET_L_REG (4) & 0xffff;
2171 rd
= GET_MEMORY_B (GET_L_REG (5));
2172 SET_MEMORY_B (GET_L_REG (6), rd
);
2173 SET_L_REG (5, GET_L_REG (5) + 1);
2174 SET_L_REG (6, GET_L_REG (6) + 1);
2181 case O (O_EEPMOV
, SB
): /* eepmov.b */
2182 case O (O_EEPMOV
, SW
): /* eepmov.w */
2183 if (h8300hmode
|| h8300smode
)
2185 register unsigned char *_src
, *_dst
;
2186 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2187 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2188 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2190 _src
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
);
2191 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2193 _dst
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
);
2194 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2196 memcpy (_dst
, _src
, count
);
2198 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2199 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2200 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2201 ((code
->opcode
== O (O_EEPMOV
, SW
))
2202 ? (~0xffff) : (~0xff)));
2203 cycles
+= 2 * count
;
2208 case O (O_ADDS
, SL
): /* adds (.l) */
2210 * This insn only uses register operands, but still
2211 * it would be cleaner to use fetch and store... */
2212 SET_L_REG (code
->dst
.reg
,
2213 GET_L_REG (code
->dst
.reg
)
2214 + code
->src
.literal
);
2218 case O (O_SUBS
, SL
): /* subs (.l) */
2220 * This insn only uses register operands, but still
2221 * it would be cleaner to use fetch and store... */
2222 SET_L_REG (code
->dst
.reg
,
2223 GET_L_REG (code
->dst
.reg
)
2224 - code
->src
.literal
);
2227 case O (O_CMP
, SB
): /* cmp.b */
2228 if (fetch (sd
, &code
->dst
, &rd
))
2230 if (fetch (sd
, &code
->src
, &ea
))
2234 goto just_flags_alu8
;
2236 case O (O_CMP
, SW
): /* cmp.w */
2237 if (fetch (sd
, &code
->dst
, &rd
))
2239 if (fetch (sd
, &code
->src
, &ea
))
2243 goto just_flags_alu16
;
2245 case O (O_CMP
, SL
): /* cmp.l */
2246 if (fetch (sd
, &code
->dst
, &rd
))
2248 if (fetch (sd
, &code
->src
, &ea
))
2252 goto just_flags_alu32
;
2254 case O (O_DEC
, SB
): /* dec.b */
2256 * This insn only uses register operands, but still
2257 * it would be cleaner to use fetch and store... */
2258 rd
= GET_B_REG (code
->src
.reg
);
2261 SET_B_REG (code
->src
.reg
, res
);
2262 goto just_flags_inc8
;
2264 case O (O_DEC
, SW
): /* dec.w */
2266 * This insn only uses register operands, but still
2267 * it would be cleaner to use fetch and store... */
2268 rd
= GET_W_REG (code
->dst
.reg
);
2269 ea
= -code
->src
.literal
;
2271 SET_W_REG (code
->dst
.reg
, res
);
2272 goto just_flags_inc16
;
2274 case O (O_DEC
, SL
): /* dec.l */
2276 * This insn only uses register operands, but still
2277 * it would be cleaner to use fetch and store... */
2278 rd
= GET_L_REG (code
->dst
.reg
);
2279 ea
= -code
->src
.literal
;
2281 SET_L_REG (code
->dst
.reg
, res
);
2282 goto just_flags_inc32
;
2284 case O (O_INC
, SB
): /* inc.b */
2286 * This insn only uses register operands, but still
2287 * it would be cleaner to use fetch and store... */
2288 rd
= GET_B_REG (code
->src
.reg
);
2291 SET_B_REG (code
->src
.reg
, res
);
2292 goto just_flags_inc8
;
2294 case O (O_INC
, SW
): /* inc.w */
2296 * This insn only uses register operands, but still
2297 * it would be cleaner to use fetch and store... */
2298 rd
= GET_W_REG (code
->dst
.reg
);
2299 ea
= code
->src
.literal
;
2301 SET_W_REG (code
->dst
.reg
, res
);
2302 goto just_flags_inc16
;
2304 case O (O_INC
, SL
): /* inc.l */
2306 * This insn only uses register operands, but still
2307 * it would be cleaner to use fetch and store... */
2308 rd
= GET_L_REG (code
->dst
.reg
);
2309 ea
= code
->src
.literal
;
2311 SET_L_REG (code
->dst
.reg
, res
);
2312 goto just_flags_inc32
;
2314 case O (O_LDC
, SB
): /* ldc.b */
2315 if (fetch (sd
, &code
->src
, &res
))
2319 case O (O_LDC
, SW
): /* ldc.w */
2320 if (fetch (sd
, &code
->src
, &res
))
2323 /* Word operand, value from MSB, must be shifted. */
2327 case O (O_LDC
, SL
): /* ldc.l */
2328 if (fetch (sd
, &code
->src
, &res
))
2330 switch (code
->dst
.type
) {
2331 case X (OP_SBR
, SL
):
2332 h8_set_sbr (sd
, res
);
2334 case X (OP_VBR
, SL
):
2335 h8_set_vbr (sd
, res
);
2342 case O (O_STC
, SW
): /* stc.w */
2343 case O (O_STC
, SB
): /* stc.b */
2344 if (code
->src
.type
== X (OP_CCR
, SB
))
2347 res
= h8_get_ccr (sd
);
2349 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2352 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2353 res
= h8_get_exr (sd
);
2358 /* Word operand, value to MSB, must be shifted. */
2359 if (code
->opcode
== X (O_STC
, SW
))
2361 if (store (sd
, &code
->dst
, res
))
2364 case O (O_STC
, SL
): /* stc.l */
2365 switch (code
->src
.type
) {
2366 case X (OP_SBR
, SL
):
2367 res
= h8_get_sbr (sd
);
2369 case X (OP_VBR
, SL
):
2370 res
= h8_get_vbr (sd
);
2375 if (store (sd
, &code
->dst
, res
))
2379 case O (O_ANDC
, SB
): /* andc.b */
2380 if (code
->dst
.type
== X (OP_CCR
, SB
))
2383 rd
= h8_get_ccr (sd
);
2385 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2388 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2389 rd
= h8_get_exr (sd
);
2393 ea
= code
->src
.literal
;
2397 case O (O_ORC
, SB
): /* orc.b */
2398 if (code
->dst
.type
== X (OP_CCR
, SB
))
2401 rd
= h8_get_ccr (sd
);
2403 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2406 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2407 rd
= h8_get_exr (sd
);
2411 ea
= code
->src
.literal
;
2415 case O (O_XORC
, SB
): /* xorc.b */
2416 if (code
->dst
.type
== X (OP_CCR
, SB
))
2419 rd
= h8_get_ccr (sd
);
2421 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2424 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2425 rd
= h8_get_exr (sd
);
2429 ea
= code
->src
.literal
;
2433 case O (O_BRAS
, SB
): /* bra/s */
2434 /* This is basically an ordinary branch, with a delay slot. */
2435 if (fetch (sd
, &code
->src
, &res
))
2443 /* Execution continues at next instruction, but
2444 delayed_branch is set up for next cycle. */
2445 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2449 case O (O_BRAB
, SB
): /* bra rd.b */
2450 case O (O_BRAW
, SW
): /* bra rd.w */
2451 case O (O_BRAL
, SL
): /* bra erd.l */
2452 if (fetch (sd
, &code
->src
, &rd
))
2454 switch (OP_SIZE (code
->opcode
)) {
2455 case SB
: rd
&= 0xff; break;
2456 case SW
: rd
&= 0xffff; break;
2457 case SL
: rd
&= 0xffffffff; break;
2459 pc
= code
->next_pc
+ rd
;
2462 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2463 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2464 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2465 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2466 if (fetch (sd
, &code
->dst
, &rd
) ||
2467 fetch (sd
, &code
->src
, &bit
))
2470 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2471 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2473 if ((rd
& (1 << bit
))) /* no branch */
2476 else /* branch/call if set */
2478 if (!(rd
& (1 << bit
))) /* no branch */
2482 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2484 pc
= code
->next_pc
+ res
;
2486 if (code
->opcode
== O (O_BRABC
, SB
) ||
2487 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2495 case O (O_BRA
, SB
): /* bra, branch always */
2500 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2505 case O (O_BHI
, SB
): /* bhi */
2511 case O (O_BLS
, SB
): /* bls */
2516 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2521 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2526 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2530 case O (O_BGT
, SB
): /* bgt */
2531 if (((Z
|| (N
^ V
)) == 0))
2535 case O (O_BLE
, SB
): /* ble */
2536 if (((Z
|| (N
^ V
)) == 1))
2540 case O (O_BGE
, SB
): /* bge */
2544 case O (O_BLT
, SB
): /* blt */
2548 case O (O_BMI
, SB
): /* bmi */
2552 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2557 case O (O_BPL
, SB
): /* bpl */
2561 case O (O_BVC
, SB
): /* bvc */
2565 case O (O_BVS
, SB
): /* bvs */
2570 /* Trap for Command Line setup. */
2571 case O (O_SYS_CMDLINE
, SB
):
2573 int i
= 0; /* Loop counter. */
2574 int j
= 0; /* Loop counter. */
2575 int ind_arg_len
= 0; /* Length of each argument. */
2576 int no_of_args
= 0; /* The no. or cmdline args. */
2577 int current_location
= 0; /* Location of string. */
2578 int old_sp
= 0; /* The Initial Stack Pointer. */
2579 int no_of_slots
= 0; /* No. of slots required on the stack
2580 for storing cmdline args. */
2581 int sp_move
= 0; /* No. of locations by which the stack needs
2583 int new_sp
= 0; /* The final stack pointer location passed
2585 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2586 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2587 args on the stack. */
2588 int char_ptr_size
= 0; /* Size of a character pointer on
2590 int addr_cmdline
= 0; /* Memory location where cmdline has
2592 int size_cmdline
= 0; /* Size of cmdline. */
2594 /* Set the address of 256 free locations where command line is
2596 addr_cmdline
= cmdline_location();
2597 h8_set_reg (sd
, 0, addr_cmdline
);
2599 /* Counting the no. of commandline arguments. */
2600 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2603 /* No. of arguments in the command line. */
2606 /* Current location is just a temporary variable,which we are
2607 setting to the point to the start of our commandline string. */
2608 current_location
= addr_cmdline
;
2610 /* Allocating space for storing pointers of the command line
2612 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2614 /* Setting char_ptr_size to the sizeof (char *) on the different
2616 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2625 for (i
= 0; i
< no_of_args
; i
++)
2629 /* The size of the commandline argument. */
2630 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2632 /* The total size of the command line string. */
2633 size_cmdline
+= ind_arg_len
;
2635 /* As we have only 256 bytes, we need to provide a graceful
2636 exit. Anyways, a program using command line arguments
2637 where we cannot store all the command line arguments
2638 given may behave unpredictably. */
2639 if (size_cmdline
>= 256)
2641 h8_set_reg (sd
, 0, 0);
2646 /* current_location points to the memory where the next
2647 commandline argument is stored. */
2648 argv_ptrs
[i
] = current_location
;
2649 for (j
= 0; j
< ind_arg_len
; j
++)
2651 SET_MEMORY_B ((current_location
+
2652 (sizeof (char) * j
)),
2653 *(h8_get_cmdline_arg (sd
, i
) +
2654 sizeof (char) * j
));
2657 /* Setting current_location to the starting of next
2659 current_location
+= ind_arg_len
;
2663 /* This is the original position of the stack pointer. */
2664 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2666 /* We need space from the stack to store the pointers to argvs. */
2667 /* As we will infringe on the stack, we need to shift the stack
2668 pointer so that the data is not overwritten. We calculate how
2669 much space is required. */
2670 sp_move
= (no_of_args
) * (char_ptr_size
);
2672 /* The final position of stack pointer, we have thus taken some
2673 space from the stack. */
2674 new_sp
= old_sp
- sp_move
;
2676 /* Temporary variable holding value where the argv pointers need
2678 argv_ptrs_location
= new_sp
;
2680 /* The argv pointers are stored at sequential locations. As per
2682 for (i
= 0; i
< no_of_args
; i
++)
2684 /* Saving the argv pointer. */
2685 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2687 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2691 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2694 /* The next location where the pointer to the next argv
2695 string has to be stored. */
2696 argv_ptrs_location
+= char_ptr_size
;
2699 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2701 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2703 SET_MEMORY_L (old_sp
, 0x0);
2707 SET_MEMORY_W (old_sp
, 0x0);
2710 /* Freeing allocated memory. */
2712 for (i
= 0; i
<= no_of_args
; i
++)
2714 free (h8_get_cmdline_arg (sd
, i
));
2716 free (h8_get_command_line (sd
));
2718 /* The no. of argv arguments are returned in Reg 0. */
2719 h8_set_reg (sd
, 0, no_of_args
);
2720 /* The Pointer to argv in Register 1. */
2721 h8_set_reg (sd
, 1, new_sp
);
2722 /* Setting the stack pointer to the new value. */
2723 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2727 /* System call processing starts. */
2728 case O (O_SYS_OPEN
, SB
):
2730 int len
= 0; /* Length of filename. */
2731 char *filename
; /* Filename would go here. */
2732 char temp_char
; /* Temporary character */
2733 int mode
= 0; /* Mode bits for the file. */
2734 int open_return
; /* Return value of open, file descriptor. */
2735 int i
; /* Loop counter */
2736 int filename_ptr
; /* Pointer to filename in cpu memory. */
2738 /* Setting filename_ptr to first argument of open, */
2739 /* and trying to get mode. */
2740 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2742 filename_ptr
= GET_L_REG (0);
2743 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2747 filename_ptr
= GET_W_REG (0);
2748 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2751 /* Trying to find the length of the filename. */
2752 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2755 while (temp_char
!= '\0')
2757 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2761 /* Allocating space for the filename. */
2762 filename
= (char *) malloc (sizeof (char) * len
);
2764 /* String copying the filename from memory. */
2765 for (i
= 0; i
< len
; i
++)
2767 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2768 filename
[i
] = temp_char
;
2771 /* Callback to open and return the file descriptor. */
2772 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2774 /* Return value in register 0. */
2775 h8_set_reg (sd
, 0, open_return
);
2777 /* Freeing memory used for filename. */
2782 case O (O_SYS_READ
, SB
):
2784 char *char_ptr
; /* Where characters read would be stored. */
2785 int fd
; /* File descriptor */
2786 int buf_size
; /* BUF_SIZE parameter in read. */
2787 int i
= 0; /* Temporary Loop counter */
2788 int read_return
= 0; /* Return value from callback to
2791 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2792 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2794 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2796 /* Callback to read and return the no. of characters read. */
2798 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2800 /* The characters read are stored in cpu memory. */
2801 for (i
= 0; i
< buf_size
; i
++)
2803 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2804 *(char_ptr
+ (sizeof (char) * i
)));
2807 /* Return value in Register 0. */
2808 h8_set_reg (sd
, 0, read_return
);
2810 /* Freeing memory used as buffer. */
2815 case O (O_SYS_WRITE
, SB
):
2817 int fd
; /* File descriptor */
2818 char temp_char
; /* Temporary character */
2819 int len
; /* Length of write, Parameter II to write. */
2820 int char_ptr
; /* Character Pointer, Parameter I of write. */
2821 char *ptr
; /* Where characters to be written are stored.
2823 int write_return
; /* Return value from callback to write. */
2824 int i
= 0; /* Loop counter */
2826 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2827 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2828 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2830 /* Allocating space for the characters to be written. */
2831 ptr
= (char *) malloc (sizeof (char) * len
);
2833 /* Fetching the characters from cpu memory. */
2834 for (i
= 0; i
< len
; i
++)
2836 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2840 /* Callback write and return the no. of characters written. */
2841 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2843 /* Return value in Register 0. */
2844 h8_set_reg (sd
, 0, write_return
);
2846 /* Freeing memory used as buffer. */
2851 case O (O_SYS_LSEEK
, SB
):
2853 int fd
; /* File descriptor */
2854 int offset
; /* Offset */
2855 int origin
; /* Origin */
2856 int lseek_return
; /* Return value from callback to lseek. */
2858 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2859 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2860 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2862 /* Callback lseek and return offset. */
2864 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2866 /* Return value in register 0. */
2867 h8_set_reg (sd
, 0, lseek_return
);
2871 case O (O_SYS_CLOSE
, SB
):
2873 int fd
; /* File descriptor */
2874 int close_return
; /* Return value from callback to close. */
2876 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2878 /* Callback close and return. */
2879 close_return
= sim_callback
->close (sim_callback
, fd
);
2881 /* Return value in register 0. */
2882 h8_set_reg (sd
, 0, close_return
);
2886 case O (O_SYS_FSTAT
, SB
):
2888 int fd
; /* File descriptor */
2889 struct stat stat_rec
; /* Stat record */
2890 int fstat_return
; /* Return value from callback to stat. */
2891 int stat_ptr
; /* Pointer to stat record. */
2892 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2894 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2896 /* Setting stat_ptr to second argument of stat. */
2897 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2899 /* Callback stat and return. */
2900 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
2903 /* Have stat_ptr point to starting of stat_rec. */
2904 temp_stat_ptr
= (char *) (&stat_rec
);
2906 /* Setting up the stat structure returned. */
2907 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2909 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2911 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2913 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2915 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2917 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2919 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2921 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2923 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2925 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2927 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2929 /* Return value in register 0. */
2930 h8_set_reg (sd
, 0, fstat_return
);
2934 case O (O_SYS_STAT
, SB
):
2936 int len
= 0; /* Length of filename. */
2937 char *filename
; /* Filename would go here. */
2938 char temp_char
; /* Temporary character */
2939 int filename_ptr
; /* Pointer to filename in cpu memory. */
2940 struct stat stat_rec
; /* Stat record */
2941 int stat_return
; /* Return value from callback to stat */
2942 int stat_ptr
; /* Pointer to stat record. */
2943 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2944 int i
= 0; /* Loop Counter */
2946 /* Setting filename_ptr to first argument of open. */
2947 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2949 /* Trying to find the length of the filename. */
2950 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2953 while (temp_char
!= '\0')
2955 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2959 /* Allocating space for the filename. */
2960 filename
= (char *) malloc (sizeof (char) * len
);
2962 /* String copying the filename from memory. */
2963 for (i
= 0; i
< len
; i
++)
2965 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2966 filename
[i
] = temp_char
;
2969 /* Setting stat_ptr to second argument of stat. */
2970 /* stat_ptr = h8_get_reg (sd, 1); */
2971 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2973 /* Callback stat and return. */
2975 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
2977 /* Have stat_ptr point to starting of stat_rec. */
2978 temp_stat_ptr
= (char *) (&stat_rec
);
2980 /* Freeing memory used for filename. */
2983 /* Setting up the stat structure returned. */
2984 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2986 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2988 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2990 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2992 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2994 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2996 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2998 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
3000 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
3002 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
3004 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
3006 /* Return value in register 0. */
3007 h8_set_reg (sd
, 0, stat_return
);
3010 /* End of system call processing. */
3012 case O (O_NOT
, SB
): /* not.b */
3013 if (fetch2 (sd
, &code
->src
, &rd
))
3019 case O (O_NOT
, SW
): /* not.w */
3020 if (fetch2 (sd
, &code
->src
, &rd
))
3026 case O (O_NOT
, SL
): /* not.l */
3027 if (fetch2 (sd
, &code
->src
, &rd
))
3033 case O (O_SHLL
, SB
): /* shll.b */
3034 case O (O_SHLR
, SB
): /* shlr.b */
3035 if (fetch2 (sd
, &code
->dst
, &rd
))
3038 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3039 ea
= 1; /* unary op */
3040 else /* binary op */
3041 fetch (sd
, &code
->src
, &ea
);
3043 if (code
->opcode
== O (O_SHLL
, SB
))
3046 c
= rd
& (0x80 >> (ea
- 1));
3052 c
= rd
& (1 << (ea
- 1));
3053 rd
= (unsigned char) rd
>> ea
;
3057 case O (O_SHLL
, SW
): /* shll.w */
3058 case O (O_SHLR
, SW
): /* shlr.w */
3059 if (fetch2 (sd
, &code
->dst
, &rd
))
3062 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3063 ea
= 1; /* unary op */
3065 fetch (sd
, &code
->src
, &ea
);
3067 if (code
->opcode
== O (O_SHLL
, SW
))
3070 c
= rd
& (0x8000 >> (ea
- 1));
3076 c
= rd
& (1 << (ea
- 1));
3077 rd
= (unsigned short) rd
>> ea
;
3081 case O (O_SHLL
, SL
): /* shll.l */
3082 case O (O_SHLR
, SL
): /* shlr.l */
3083 if (fetch2 (sd
, &code
->dst
, &rd
))
3086 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3087 ea
= 1; /* unary op */
3089 fetch (sd
, &code
->src
, &ea
);
3091 if (code
->opcode
== O (O_SHLL
, SL
))
3094 c
= rd
& (0x80000000 >> (ea
- 1));
3100 c
= rd
& (1 << (ea
- 1));
3101 rd
= (unsigned int) rd
>> ea
;
3105 case O (O_SHAL
, SB
):
3106 case O (O_SHAR
, SB
):
3107 if (fetch2 (sd
, &code
->dst
, &rd
))
3110 if (code
->src
.type
== X (OP_IMM
, SB
))
3111 fetch (sd
, &code
->src
, &ea
);
3115 if (code
->opcode
== O (O_SHAL
, SB
))
3117 c
= rd
& (0x80 >> (ea
- 1));
3118 res
= rd
>> (7 - ea
);
3119 v
= ((res
& 1) && !(res
& 2))
3120 || (!(res
& 1) && (res
& 2));
3125 c
= rd
& (1 << (ea
- 1));
3127 rd
= ((signed char) rd
) >> ea
;
3131 case O (O_SHAL
, SW
):
3132 case O (O_SHAR
, SW
):
3133 if (fetch2 (sd
, &code
->dst
, &rd
))
3136 if (code
->src
.type
== X (OP_IMM
, SW
))
3137 fetch (sd
, &code
->src
, &ea
);
3141 if (code
->opcode
== O (O_SHAL
, SW
))
3143 c
= rd
& (0x8000 >> (ea
- 1));
3144 res
= rd
>> (15 - ea
);
3145 v
= ((res
& 1) && !(res
& 2))
3146 || (!(res
& 1) && (res
& 2));
3151 c
= rd
& (1 << (ea
- 1));
3153 rd
= ((signed short) rd
) >> ea
;
3157 case O (O_SHAL
, SL
):
3158 case O (O_SHAR
, SL
):
3159 if (fetch2 (sd
, &code
->dst
, &rd
))
3162 if (code
->src
.type
== X (OP_IMM
, SL
))
3163 fetch (sd
, &code
->src
, &ea
);
3167 if (code
->opcode
== O (O_SHAL
, SL
))
3169 c
= rd
& (0x80000000 >> (ea
- 1));
3170 res
= rd
>> (31 - ea
);
3171 v
= ((res
& 1) && !(res
& 2))
3172 || (!(res
& 1) && (res
& 2));
3177 c
= rd
& (1 << (ea
- 1));
3179 rd
= ((signed int) rd
) >> ea
;
3183 case O (O_ROTL
, SB
):
3184 case O (O_ROTR
, SB
):
3185 if (fetch2 (sd
, &code
->dst
, &rd
))
3188 if (code
->src
.type
== X (OP_IMM
, SB
))
3189 fetch (sd
, &code
->src
, &ea
);
3194 if (code
->opcode
== O (O_ROTL
, SB
))
3204 rd
= ((unsigned char) rd
) >> 1;
3212 case O (O_ROTL
, SW
):
3213 case O (O_ROTR
, SW
):
3214 if (fetch2 (sd
, &code
->dst
, &rd
))
3217 if (code
->src
.type
== X (OP_IMM
, SW
))
3218 fetch (sd
, &code
->src
, &ea
);
3223 if (code
->opcode
== O (O_ROTL
, SW
))
3233 rd
= ((unsigned short) rd
) >> 1;
3241 case O (O_ROTL
, SL
):
3242 case O (O_ROTR
, SL
):
3243 if (fetch2 (sd
, &code
->dst
, &rd
))
3246 if (code
->src
.type
== X (OP_IMM
, SL
))
3247 fetch (sd
, &code
->src
, &ea
);
3252 if (code
->opcode
== O (O_ROTL
, SL
))
3254 c
= rd
& 0x80000000;
3262 rd
= ((unsigned int) rd
) >> 1;
3270 case O (O_ROTXL
, SB
):
3271 case O (O_ROTXR
, SB
):
3272 if (fetch2 (sd
, &code
->dst
, &rd
))
3275 if (code
->src
.type
== X (OP_IMM
, SB
))
3276 fetch (sd
, &code
->src
, &ea
);
3281 if (code
->opcode
== O (O_ROTXL
, SB
))
3292 rd
= ((unsigned char) rd
) >> 1;
3301 case O (O_ROTXL
, SW
):
3302 case O (O_ROTXR
, SW
):
3303 if (fetch2 (sd
, &code
->dst
, &rd
))
3306 if (code
->src
.type
== X (OP_IMM
, SW
))
3307 fetch (sd
, &code
->src
, &ea
);
3312 if (code
->opcode
== O (O_ROTXL
, SW
))
3323 rd
= ((unsigned short) rd
) >> 1;
3332 case O (O_ROTXL
, SL
):
3333 case O (O_ROTXR
, SL
):
3334 if (fetch2 (sd
, &code
->dst
, &rd
))
3337 if (code
->src
.type
== X (OP_IMM
, SL
))
3338 fetch (sd
, &code
->src
, &ea
);
3343 if (code
->opcode
== O (O_ROTXL
, SL
))
3345 res
= rd
& 0x80000000;
3354 rd
= ((unsigned int) rd
) >> 1;
3365 case O (O_JMP
, SB
): /* jmp */
3367 fetch (sd
, &code
->src
, &pc
);
3372 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3374 if (fetch (sd
, &code
->src
, &pc
))
3377 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3379 if (h8300hmode
&& !h8300_normal_mode
)
3382 SET_MEMORY_L (tmp
, code
->next_pc
);
3387 SET_MEMORY_W (tmp
, code
->next_pc
);
3389 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3395 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3396 if (fetch (sd
, &code
->src
, &res
))
3398 pc
= code
->next_pc
+ res
;
3401 case O (O_RTE
, SN
): /* rte, return from exception */
3403 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3404 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3406 if (h8300smode
) /* pop exr */
3408 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3411 if (h8300hmode
&& !h8300_normal_mode
)
3413 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3415 pc
= GET_MEMORY_L (tmp
);
3420 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3422 pc
= GET_MEMORY_W (tmp
);
3427 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3430 case O (O_RTS
, SN
): /* rts, return from subroutine */
3432 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3434 if (h8300hmode
&& !h8300_normal_mode
)
3436 pc
= GET_MEMORY_L (tmp
);
3441 pc
= GET_MEMORY_W (tmp
);
3445 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3448 case O (O_ILL
, SB
): /* illegal */
3449 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
3452 case O (O_SLEEP
, SN
): /* sleep */
3453 /* Check for magic numbers in r1 and r2. */
3454 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3455 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3456 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3458 /* This trap comes from _exit, not from gdb. */
3459 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_exited
,
3460 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3463 /* Unfortunately this won't really work, because
3464 when we take a breakpoint trap, R0 has a "random",
3465 user-defined value. Don't see any immediate solution. */
3466 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3468 /* Pass the stop signal up to gdb. */
3469 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
,
3470 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3475 /* Treat it as a sigtrap. */
3476 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3480 case O (O_TRAPA
, SB
): /* trapa */
3481 if (fetch (sd
, &code
->src
, &res
))
3482 goto end
; /* res is vector number. */
3484 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3485 if(h8300_normal_mode
)
3488 SET_MEMORY_W (tmp
, code
->next_pc
);
3490 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3495 SET_MEMORY_L (tmp
, code
->next_pc
);
3497 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3505 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3508 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3510 if(h8300_normal_mode
)
3511 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3513 pc
= GET_MEMORY_L (0x20 + res
* 4);
3517 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3520 case O (O_BSETEQ
, SB
):
3525 case O (O_BSETNE
, SB
):
3530 case O (O_BCLREQ
, SB
):
3535 case O (O_BCLRNE
, SB
):
3540 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3541 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3543 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3545 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3546 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3547 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3548 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3549 if (C
) ea
|= m
); /* bst */
3550 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3551 if (!C
) ea
|= m
); /* bist */
3552 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3553 if (Z
) ea
|= m
); /* bstz */
3554 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3555 if (!Z
) ea
|= m
); /* bistz */
3556 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3557 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3558 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3559 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3560 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3561 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3563 case O (O_BFLD
, SB
): /* bfld */
3566 if (fetch (sd
, &code
->src
, &bit
))
3571 if (fetch (sd
, &code
->dst
, &ea
))
3581 if (store (sd
, &code
->op3
, ea
))
3586 case O(O_BFST
, SB
): /* bfst */
3587 /* bitfield store */
3588 /* NOTE: the imm8 value is in dst, and the ea value
3589 (which is actually the destination) is in op3.
3590 It has to be that way, to avoid breaking the assembler. */
3592 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3594 if (bit
== 0) /* noop -- nothing to do. */
3597 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3600 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3603 /* Left-shift the register data into position. */
3604 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3607 /* Combine it with the neighboring bits. */
3608 ea
= (ea
& ~bit
) | (rd
& bit
);
3611 if (store2 (sd
, &code
->op3
, ea
))
3615 case O (O_CLRMAC
, SN
): /* clrmac */
3616 h8_set_mach (sd
, 0);
3617 h8_set_macl (sd
, 0);
3618 h8_set_macZ (sd
, 1);
3619 h8_set_macV (sd
, 0);
3620 h8_set_macN (sd
, 0);
3623 case O (O_STMAC
, SL
): /* stmac, 260 */
3624 switch (code
->src
.type
) {
3625 case X (OP_MACH
, SL
):
3626 res
= h8_get_mach (sd
);
3627 if (res
& 0x200) /* sign extend */
3630 case X (OP_MACL
, SL
):
3631 res
= h8_get_macl (sd
);
3633 default: goto illegal
;
3635 nz
= !h8_get_macZ (sd
);
3636 n
= h8_get_macN (sd
);
3637 v
= h8_get_macV (sd
);
3639 if (store (sd
, &code
->dst
, res
))
3644 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3645 if (fetch (sd
, &code
->src
, &rd
))
3648 switch (code
->dst
.type
) {
3649 case X (OP_MACH
, SL
):
3650 rd
&= 0x3ff; /* Truncate to 10 bits */
3651 h8_set_mach (sd
, rd
);
3653 case X (OP_MACL
, SL
):
3654 h8_set_macl (sd
, rd
);
3656 default: goto illegal
;
3658 h8_set_macV (sd
, 0);
3662 if (fetch (sd
, &code
->src
, &rd
) ||
3663 fetch (sd
, &code
->dst
, &res
))
3666 /* Ye gods, this is non-portable!
3667 However, the existing mul/div code is similar. */
3668 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3670 if (h8_get_macS (sd
)) /* Saturating mode */
3672 long long mac
= h8_get_macl (sd
);
3674 if (mac
& 0x80000000) /* sign extend */
3675 mac
|= 0xffffffff00000000LL
;
3678 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3679 h8_set_macV (sd
, 1);
3680 h8_set_macZ (sd
, (mac
== 0));
3681 h8_set_macN (sd
, (mac
< 0));
3682 h8_set_macl (sd
, (int) mac
);
3684 else /* "Less Saturating" mode */
3686 long long mac
= h8_get_mach (sd
);
3688 mac
+= h8_get_macl (sd
);
3690 if (mac
& 0x20000000000LL
) /* sign extend */
3691 mac
|= 0xfffffc0000000000LL
;
3694 if (mac
> 0x1ffffffffffLL
||
3695 mac
< (long long) 0xfffffe0000000000LL
)
3696 h8_set_macV (sd
, 1);
3697 h8_set_macZ (sd
, (mac
== 0));
3698 h8_set_macN (sd
, (mac
< 0));
3699 h8_set_macl (sd
, (int) mac
);
3701 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3705 case O (O_MULS
, SW
): /* muls.w */
3706 if (fetch (sd
, &code
->src
, &ea
) ||
3707 fetch (sd
, &code
->dst
, &rd
))
3710 ea
= SEXTSHORT (ea
);
3711 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3715 if (store (sd
, &code
->dst
, res
))
3720 case O (O_MULS
, SL
): /* muls.l */
3721 if (fetch (sd
, &code
->src
, &ea
) ||
3722 fetch (sd
, &code
->dst
, &rd
))
3727 n
= res
& 0x80000000;
3728 nz
= res
& 0xffffffff;
3729 if (store (sd
, &code
->dst
, res
))
3733 case O (O_MULSU
, SL
): /* muls/u.l */
3734 if (fetch (sd
, &code
->src
, &ea
) ||
3735 fetch (sd
, &code
->dst
, &rd
))
3738 /* Compute upper 32 bits of the 64-bit result. */
3739 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3741 n
= res
& 0x80000000;
3742 nz
= res
& 0xffffffff;
3743 if (store (sd
, &code
->dst
, res
))
3747 case O (O_MULU
, SW
): /* mulu.w */
3748 if (fetch (sd
, &code
->src
, &ea
) ||
3749 fetch (sd
, &code
->dst
, &rd
))
3752 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3754 /* Don't set Z or N. */
3755 if (store (sd
, &code
->dst
, res
))
3760 case O (O_MULU
, SL
): /* mulu.l */
3761 if (fetch (sd
, &code
->src
, &ea
) ||
3762 fetch (sd
, &code
->dst
, &rd
))
3767 /* Don't set Z or N. */
3768 if (store (sd
, &code
->dst
, res
))
3773 case O (O_MULUU
, SL
): /* mulu/u.l */
3774 if (fetch (sd
, &code
->src
, &ea
) ||
3775 fetch (sd
, &code
->dst
, &rd
))
3778 /* Compute upper 32 bits of the 64-bit result. */
3779 res
= (((unsigned long long) (unsigned) ea
) *
3780 ((unsigned long long) (unsigned) rd
)) >> 32;
3782 /* Don't set Z or N. */
3783 if (store (sd
, &code
->dst
, res
))
3788 case O (O_MULXS
, SB
): /* mulxs.b */
3789 if (fetch (sd
, &code
->src
, &ea
) ||
3790 fetch (sd
, &code
->dst
, &rd
))
3794 res
= ea
* SEXTCHAR (rd
);
3798 if (store (sd
, &code
->dst
, res
))
3803 case O (O_MULXS
, SW
): /* mulxs.w */
3804 if (fetch (sd
, &code
->src
, &ea
) ||
3805 fetch (sd
, &code
->dst
, &rd
))
3808 ea
= SEXTSHORT (ea
);
3809 res
= ea
* SEXTSHORT (rd
& 0xffff);
3811 n
= res
& 0x80000000;
3812 nz
= res
& 0xffffffff;
3813 if (store (sd
, &code
->dst
, res
))
3818 case O (O_MULXU
, SB
): /* mulxu.b */
3819 if (fetch (sd
, &code
->src
, &ea
) ||
3820 fetch (sd
, &code
->dst
, &rd
))
3823 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3825 if (store (sd
, &code
->dst
, res
))
3830 case O (O_MULXU
, SW
): /* mulxu.w */
3831 if (fetch (sd
, &code
->src
, &ea
) ||
3832 fetch (sd
, &code
->dst
, &rd
))
3835 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3837 if (store (sd
, &code
->dst
, res
))
3842 case O (O_TAS
, SB
): /* tas (test and set) */
3843 if (!h8300sxmode
) /* h8sx can use any register. */
3844 switch (code
->src
.reg
)
3855 if (fetch (sd
, &code
->src
, &res
))
3857 if (store (sd
, &code
->src
, res
| 0x80))
3860 goto just_flags_log8
;
3862 case O (O_DIVU
, SW
): /* divu.w */
3863 if (fetch (sd
, &code
->src
, &ea
) ||
3864 fetch (sd
, &code
->dst
, &rd
))
3870 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
3874 if (store (sd
, &code
->dst
, res
))
3878 case O (O_DIVU
, SL
): /* divu.l */
3879 if (fetch (sd
, &code
->src
, &ea
) ||
3880 fetch (sd
, &code
->dst
, &rd
))
3883 n
= ea
& 0x80000000;
3884 nz
= ea
& 0xffffffff;
3886 res
= (unsigned) rd
/ ea
;
3890 if (store (sd
, &code
->dst
, res
))
3894 case O (O_DIVS
, SW
): /* divs.w */
3895 if (fetch (sd
, &code
->src
, &ea
) ||
3896 fetch (sd
, &code
->dst
, &rd
))
3901 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
3911 if (store (sd
, &code
->dst
, res
))
3915 case O (O_DIVS
, SL
): /* divs.l */
3916 if (fetch (sd
, &code
->src
, &ea
) ||
3917 fetch (sd
, &code
->dst
, &rd
))
3931 n
= res
& 0x80000000;
3932 if (store (sd
, &code
->dst
, res
))
3936 case O (O_DIVXU
, SB
): /* divxu.b */
3937 if (fetch (sd
, &code
->src
, &ea
) ||
3938 fetch (sd
, &code
->dst
, &rd
))
3941 rd
= UEXTSHORT (rd
);
3948 tmp
= (unsigned) rd
% ea
;
3949 res
= (unsigned) rd
/ ea
;
3957 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3961 case O (O_DIVXU
, SW
): /* divxu.w */
3962 if (fetch (sd
, &code
->src
, &ea
) ||
3963 fetch (sd
, &code
->dst
, &rd
))
3966 ea
= UEXTSHORT (ea
);
3972 tmp
= (unsigned) rd
% ea
;
3973 res
= (unsigned) rd
/ ea
;
3981 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3985 case O (O_DIVXS
, SB
): /* divxs.b */
3986 if (fetch (sd
, &code
->src
, &ea
) ||
3987 fetch (sd
, &code
->dst
, &rd
))
3990 rd
= SEXTSHORT (rd
);
3995 tmp
= (int) rd
% (int) ea
;
3996 res
= (int) rd
/ (int) ea
;
4007 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
4011 case O (O_DIVXS
, SW
): /* divxs.w */
4012 if (fetch (sd
, &code
->src
, &ea
) ||
4013 fetch (sd
, &code
->dst
, &rd
))
4016 ea
= SEXTSHORT (ea
);
4020 tmp
= (int) rd
% (int) ea
;
4021 res
= (int) rd
/ (int) ea
;
4031 n
= res
& 0x80000000;
4032 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
4036 case O (O_EXTS
, SW
): /* exts.w, signed extend */
4037 if (fetch2 (sd
, &code
->dst
, &rd
))
4039 ea
= rd
& 0x80 ? -256 : 0;
4040 res
= (rd
& 0xff) + ea
;
4043 case O (O_EXTS
, SL
): /* exts.l, signed extend */
4044 if (fetch2 (sd
, &code
->dst
, &rd
))
4046 if (code
->src
.type
== X (OP_IMM
, SL
))
4048 if (fetch (sd
, &code
->src
, &ea
))
4051 if (ea
== 2) /* exts.l #2, nn */
4053 /* Sign-extend from 8-bit to 32-bit. */
4054 ea
= rd
& 0x80 ? -256 : 0;
4055 res
= (rd
& 0xff) + ea
;
4059 /* Sign-extend from 16-bit to 32-bit. */
4060 ea
= rd
& 0x8000 ? -65536 : 0;
4061 res
= (rd
& 0xffff) + ea
;
4064 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4065 if (fetch2 (sd
, &code
->dst
, &rd
))
4068 res
= (rd
& 0xff) + ea
;
4071 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4072 if (fetch2 (sd
, &code
->dst
, &rd
))
4074 if (code
->src
.type
== X (OP_IMM
, SL
))
4076 if (fetch (sd
, &code
->src
, &ea
))
4079 if (ea
== 2) /* extu.l #2, nn */
4081 /* Zero-extend from 8-bit to 32-bit. */
4083 res
= (rd
& 0xff) + ea
;
4087 /* Zero-extend from 16-bit to 32-bit. */
4089 res
= (rd
& 0xffff) + ea
;
4092 case O (O_NOP
, SN
): /* nop */
4095 case O (O_STM
, SL
): /* stm, store to memory */
4097 int nregs
, firstreg
, i
;
4099 nregs
= GET_MEMORY_B (pc
+ 1);
4102 firstreg
= code
->src
.reg
;
4104 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4106 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4107 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4112 case O (O_LDM
, SL
): /* ldm, load from memory */
4113 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4114 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4116 int nregs
, firstreg
, i
;
4118 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4119 firstreg
= code
->dst
.reg
& 0xf;
4120 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4122 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4123 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4126 switch (code
->opcode
) {
4127 case O (O_RTEL
, SN
):
4129 case O (O_RTSL
, SN
):
4138 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4139 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4140 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4141 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4142 res
= res
; /* Value added == 0. */
4143 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4144 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4145 res
= res
+ 0x6; /* Value added == 6. */
4146 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4147 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4148 res
= res
+ 0x6; /* Value added == 6. */
4149 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4150 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4151 res
= res
+ 0x60; /* Value added == 60. */
4152 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4153 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4154 res
= res
+ 0x66; /* Value added == 66. */
4155 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4156 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4157 res
= res
+ 0x66; /* Value added == 66. */
4158 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4159 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4160 res
= res
+ 0x60; /* Value added == 60. */
4161 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4162 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4163 res
= res
+ 0x66; /* Value added == 66. */
4164 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4165 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4166 res
= res
+ 0x66; /* Value added == 66. */
4171 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4172 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4173 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4174 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4175 res
= res
; /* Value added == 0. */
4176 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4177 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4178 res
= res
+ 0xfa; /* Value added == 0xfa. */
4179 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4180 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4181 res
= res
+ 0xa0; /* Value added == 0xa0. */
4182 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4183 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4184 res
= res
+ 0x9a; /* Value added == 0x9a. */
4190 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4195 sim_io_printf (sd
, "sim_resume: internal error.\n");
4196 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4200 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4201 code
->dst
.type
== X (OP_CCR
, SW
))
4203 h8_set_ccr (sd
, res
);
4206 else if (h8300smode
&&
4207 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4208 code
->dst
.type
== X (OP_EXR
, SW
)))
4210 h8_set_exr (sd
, res
);
4211 if (h8300smode
) /* Get exr. */
4213 trace
= (h8_get_exr (sd
) >> 7) & 1;
4214 intMask
= h8_get_exr (sd
) & 7;
4223 /* When a branch works */
4224 if (fetch (sd
, &code
->src
, &res
))
4226 if (res
& 1) /* bad address */
4228 pc
= code
->next_pc
+ res
;
4231 /* Set the cond codes from res */
4234 /* Set the flags after an 8 bit inc/dec operation */
4238 v
= (rd
& 0x7f) == 0x7f;
4241 /* Set the flags after an 16 bit inc/dec operation */
4245 v
= (rd
& 0x7fff) == 0x7fff;
4248 /* Set the flags after an 32 bit inc/dec operation */
4250 n
= res
& 0x80000000;
4251 nz
= res
& 0xffffffff;
4252 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4256 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4259 if (store2 (sd
, &code
->dst
, rd
))
4264 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4267 if (store2 (sd
, &code
->dst
, rd
))
4272 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4273 n
= (rd
& 0x80000000);
4274 nz
= rd
& 0xffffffff;
4275 if (store2 (sd
, &code
->dst
, rd
))
4280 if (store2 (sd
, &code
->dst
, res
))
4284 /* flags after a 32bit logical operation */
4285 n
= res
& 0x80000000;
4286 nz
= res
& 0xffffffff;
4291 if (store2 (sd
, &code
->dst
, res
))
4295 /* flags after a 16bit logical operation */
4302 if (store2 (sd
, &code
->dst
, res
))
4312 if (store2 (sd
, &code
->dst
, res
))
4319 switch (code
->opcode
/ 4)
4323 v
= ((rd
& 0x80) == (ea
& 0x80)
4324 && (rd
& 0x80) != (res
& 0x80));
4329 v
= ((rd
& 0x80) != (-ea
& 0x80)
4330 && (rd
& 0x80) != (res
& 0x80));
4337 break; /* No effect on v flag. */
4342 if (store2 (sd
, &code
->dst
, res
))
4348 c
= (res
& 0x10000);
4349 switch (code
->opcode
/ 4)
4353 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4354 && (rd
& 0x8000) != (res
& 0x8000));
4359 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4360 && (rd
& 0x8000) != (res
& 0x8000));
4369 if (store2 (sd
, &code
->dst
, res
))
4373 n
= res
& 0x80000000;
4374 nz
= res
& 0xffffffff;
4375 switch (code
->opcode
/ 4)
4379 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4380 && (rd
& 0x80000000) != (res
& 0x80000000));
4381 c
= ((unsigned) res
< (unsigned) rd
) ||
4382 ((unsigned) res
< (unsigned) ea
);
4387 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4388 && (rd
& 0x80000000) != (res
& 0x80000000));
4389 c
= (unsigned) rd
< (unsigned) -ea
;
4392 v
= (rd
== 0x80000000);
4399 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4402 h8_set_delayed_branch (sd
, 0);
4410 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4411 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4412 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4417 h8_set_exr (sd
, (trace
<<7) | intMask
);
4419 h8_set_mask (sd
, oldmask
);
4423 sim_engine_run (SIM_DESC sd
,
4424 int next_cpu_nr
, /* ignore */
4425 int nr_cpus
, /* ignore */
4430 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4432 cpu
= STATE_CPU (sd
, 0);
4436 step_once (sd
, cpu
);
4437 if (sim_events_tick (sd
))
4438 sim_events_process (sd
);
4443 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4450 for (i
= 0; i
< size
; i
++)
4452 if (addr
< memory_size
)
4454 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4463 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4468 if (addr
+ size
< memory_size
)
4469 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4476 h8300_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *value
, int length
)
4481 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4482 shortval
= (value
[0] << 8) | (value
[1]);
4483 intval
= h8300hmode
? longval
: shortval
;
4485 init_pointers (CPU_STATE (cpu
));
4489 if(h8300_normal_mode
)
4490 cpu
->pc
= shortval
; /* PC for Normal mode is 2 bytes */
4510 cpu
->regs
[rn
] = intval
;
4515 cpu
->regs
[rn
] = longval
;
4522 h8300_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *buf
, int length
)
4527 init_pointers (CPU_STATE (cpu
));
4529 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4564 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4565 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4582 sim_info (SIM_DESC sd
, int verbose
)
4584 const struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
4585 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4586 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4588 sim_io_printf (sd
, "\n\n#instructions executed %10d\n", h8_get_insts (sd
));
4589 sim_io_printf (sd
, "#cycles (v approximate) %10d\n", h8_get_cycles (sd
));
4590 sim_io_printf (sd
, "#real time taken %10.4f\n", timetaken
);
4591 sim_io_printf (sd
, "#virtual time taken %10.4f\n", virttime
);
4592 if (timetaken
!= 0.0)
4593 sim_io_printf (sd
, "#simulation ratio %10.4f\n", virttime
/ timetaken
);
4596 /* This to be conditional on `what' (aka `verbose'),
4597 however it was never passed as non-zero. */
4601 for (i
= 0; i
< O_LAST
; i
++)
4603 if (h8_get_stats (sd
, i
))
4604 sim_io_printf (sd
, "%d: %d\n", i
, h8_get_stats (sd
, i
));
4610 /* Indicate whether the cpu is an H8/300 or H8/300H.
4611 FLAG is non-zero for the H8/300H. */
4614 set_h8300h (unsigned long machine
)
4616 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4617 This function being replaced by a sim_open:ARGV configuration
4620 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4622 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4625 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4628 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4631 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4632 h8300_normal_mode
= 1;
4635 /* H8300-specific options.
4636 TODO: These really should be merged into the common model modules. */
4644 h8300_option_handler (SIM_DESC sd
, sim_cpu
*cpu ATTRIBUTE_UNUSED
, int opt
,
4645 char *arg
, int is_command ATTRIBUTE_UNUSED
)
4647 switch ((H8300_OPTIONS
) opt
)
4650 set_h8300h (bfd_mach_h8300h
);
4653 set_h8300h (bfd_mach_h8300s
);
4655 case OPTION_H8300SX
:
4656 set_h8300h (bfd_mach_h8300sx
);
4660 /* We'll actually never get here; the caller handles the error
4662 sim_io_eprintf (sd
, "Unknown option `%s'\n", arg
);
4669 static const OPTION h8300_options
[] =
4671 { {"h8300h", no_argument
, NULL
, OPTION_H8300H
},
4672 'h', NULL
, "Indicate the CPU is H8/300H",
4673 h8300_option_handler
},
4674 { {"h8300s", no_argument
, NULL
, OPTION_H8300S
},
4675 'S', NULL
, "Indicate the CPU is H8S",
4676 h8300_option_handler
},
4677 { {"h8300sx", no_argument
, NULL
, OPTION_H8300SX
},
4678 'x', NULL
, "Indicate the CPU is H8SX",
4679 h8300_option_handler
},
4680 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
4684 h8300_pc_get (sim_cpu
*cpu
)
4690 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4695 /* Cover function of sim_state_free to free the cpu buffers as well. */
4698 free_state (SIM_DESC sd
)
4700 if (STATE_MODULES (sd
) != NULL
)
4701 sim_module_uninstall (sd
);
4703 /* Fixme: free buffers in _sim_cpu. */
4704 sim_state_free (sd
);
4708 sim_open (SIM_OPEN_KIND kind
,
4709 struct host_callback_struct
*callback
,
4717 sd
= sim_state_alloc_extra (kind
, callback
, sizeof (struct h8300_sim_state
));
4719 /* The cpu data is kept in a separately allocated chunk of memory. */
4720 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
4726 cpu
= STATE_CPU (sd
, 0);
4727 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4728 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
4729 /* sim_cpu object is new, so some initialization is needed. */
4730 init_pointers_needed
= 1;
4732 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4738 if (sim_add_option_table (sd
, NULL
, h8300_options
) != SIM_RC_OK
)
4744 /* The parser will print an error message for us, so we silently return. */
4745 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4747 /* Uninstall the modules to avoid memory leaks,
4748 file descriptor leaks, etc. */
4753 /* Check for/establish the a reference program image. */
4754 if (sim_analyze_program (sd
,
4755 (STATE_PROG_ARGV (sd
) != NULL
4756 ? *STATE_PROG_ARGV (sd
)
4757 : NULL
), abfd
) != SIM_RC_OK
)
4763 /* Establish any remaining configuration options. */
4764 if (sim_config (sd
) != SIM_RC_OK
)
4770 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4772 /* Uninstall the modules to avoid memory leaks,
4773 file descriptor leaks, etc. */
4778 /* CPU specific initialization. */
4779 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4781 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4783 CPU_REG_FETCH (cpu
) = h8300_reg_fetch
;
4784 CPU_REG_STORE (cpu
) = h8300_reg_store
;
4785 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4786 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4789 /* sim_hw_configure (sd); */
4791 /* FIXME: Much of the code in sim_load can be moved here. */
4796 /* Called by gdb to load a program into memory. */
4799 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4801 struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
4804 /* FIXME: The code below that sets a specific variant of the H8/300
4805 being simulated should be moved to sim_open(). */
4807 /* See if the file is for the H8/300 or H8/300H. */
4808 /* ??? This may not be the most efficient way. The z8k simulator
4809 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4813 prog_bfd
= bfd_openr (prog
, NULL
);
4814 if (prog_bfd
!= NULL
)
4816 /* Set the cpu type. We ignore failure from bfd_check_format
4817 and bfd_openr as sim_load_file checks too. */
4818 if (bfd_check_format (prog_bfd
, bfd_object
))
4820 set_h8300h (bfd_get_mach (prog_bfd
));
4824 /* If we're using gdb attached to the simulator, then we have to
4825 reallocate memory for the simulator.
4827 When gdb first starts, it calls fetch_registers (among other
4828 functions), which in turn calls init_pointers, which allocates
4831 The problem is when we do that, we don't know whether we're
4832 debugging an H8/300 or H8/300H program.
4834 This is the first point at which we can make that determination,
4835 so we just reallocate memory now; this will also allow us to handle
4836 switching between H8/300 and H8/300H programs without exiting
4839 if (h8300smode
&& !h8300_normal_mode
)
4840 memory_size
= H8300S_MSIZE
;
4841 else if (h8300hmode
&& !h8300_normal_mode
)
4842 memory_size
= H8300H_MSIZE
;
4844 memory_size
= H8300_MSIZE
;
4846 if (h8_get_memory_buf (sd
))
4847 free (h8_get_memory_buf (sd
));
4849 h8_set_memory_buf (sd
, (unsigned char *)
4850 calloc (sizeof (char), memory_size
));
4851 state
->memory_size
= memory_size
;
4853 /* `msize' must be a power of two. */
4854 if ((memory_size
& (memory_size
- 1)) != 0)
4856 sim_io_printf (sd
, "sim_load: bad memory size.\n");
4859 h8_set_mask (sd
, memory_size
- 1);
4861 if (sim_load_file (sd
, STATE_MY_NAME (sd
), STATE_CALLBACK (sd
), prog
,
4862 prog_bfd
, STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
,
4866 /* Close the bfd if we opened it. */
4867 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4868 bfd_close (prog_bfd
);
4872 /* Close the bfd if we opened it. */
4873 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4874 bfd_close (prog_bfd
);
4879 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
4880 char * const *argv
, char * const *env
)
4887 h8_set_pc (sd
, bfd_get_start_address (abfd
));
4891 /* Command Line support. */
4894 /* Counting the no. of commandline arguments. */
4895 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
4898 /* Allocating memory for the argv pointers. */
4899 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
4900 * (no_of_args
+ 1)));
4902 for (i
= 0; i
< no_of_args
; i
++)
4904 /* Copying the argument string. */
4905 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
4907 h8_set_cmdline_arg (sd
, i
, NULL
);