]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/h8300/compile.c
2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
35 #include "gdb/callback.h"
36 #include "gdb/remote-sim.h"
37 #include "gdb/sim-h8300.h"
45 host_callback
*sim_callback
;
47 static SIM_OPEN_KIND sim_kind
;
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
54 void sim_set_simcache_size
PARAMS ((int));
56 #define X(op, size) op * 4 + size
58 #define SP (h8300hmode ? SL : SW)
72 #define h8_opcodes ops
74 #include "opcode/h8300.h"
78 /* The rate at which to call the host's poll_quit callback. */
80 #define POLL_QUIT_INTERVAL 0x80000
82 #define LOW_BYTE(x) ((x) & 0xff)
83 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
84 #define P(X,Y) ((X << 8) | Y)
87 cpu.ccr = ((I << 7) | (UI << 6) | (H << 5) | (U << 4) \
88 | (N << 3) | (Z << 2) | (V << 1) | C);
91 if (h8300smode) cpu.exr = (trace<<7) | intMask;
94 c = (cpu.ccr >> 0) & 1;\
95 v = (cpu.ccr >> 1) & 1;\
96 nz = !((cpu.ccr >> 2) & 1);\
97 n = (cpu.ccr >> 3) & 1;\
98 u = (cpu.ccr >> 4) & 1;\
99 h = (cpu.ccr >> 5) & 1;\
100 ui = ((cpu.ccr >> 6) & 1);\
101 intMaskBit = (cpu.ccr >> 7) & 1;
106 trace = (cpu.exr >> 7) & 1; \
107 intMask = cpu.exr & 7; \
110 #ifdef __CHAR_IS_SIGNED__
111 #define SEXTCHAR(x) ((char) (x))
115 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
118 #define UEXTCHAR(x) ((x) & 0xff)
119 #define UEXTSHORT(x) ((x) & 0xffff)
120 #define SEXTSHORT(x) ((short) (x))
122 static cpu_state_type cpu
;
127 static int memory_size
;
132 return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */
153 return h8300hmode
? SL
: SW
;
158 lvalue (int x
, int rn
)
165 return X (OP_IMM
, SP
);
167 return X (OP_REG
, SP
);
170 return X (OP_MEM
, SP
);
173 abort (); /* ?? May be something more usefull? */
178 decode (int addr
, unsigned char *data
, decoded_inst
*dst
)
192 /* Find the exact opcode/arg combo. */
193 for (q
= h8_opcodes
; q
->name
; q
++)
195 op_type
*nib
= q
->data
.nib
;
196 unsigned int len
= 0;
200 op_type looking_for
= *nib
;
201 int thisnib
= data
[len
>> 1];
203 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
205 if (looking_for
< 16 && looking_for
>= 0)
207 if (looking_for
!= thisnib
)
212 if ((int) looking_for
& (int) B31
)
214 if (!(((int) thisnib
& 0x8) != 0))
217 looking_for
= (op_type
) ((int) looking_for
& ~(int) B31
);
221 if ((int) looking_for
& (int) B30
)
223 if (!(((int) thisnib
& 0x8) == 0))
226 looking_for
= (op_type
) ((int) looking_for
& ~(int) B30
);
229 if (looking_for
& DBIT
)
231 /* Exclude adds/subs by looking at bit 0 and 2, and
232 make sure the operand size, either w or l,
233 matches by looking at bit 1. */
234 if ((looking_for
& 7) != (thisnib
& 7))
237 abs
= (thisnib
& 0x8) ? 2 : 1;
239 else if (looking_for
& (REG
| IND
| INC
| DEC
))
241 if (looking_for
& REG
)
243 /* Can work out size from the register. */
244 size
= bitfrom (looking_for
);
246 if (looking_for
& SRC
)
251 else if (looking_for
& L_16
)
253 abs
= (data
[len
>> 1]) * 256 + data
[(len
+ 2) >> 1];
255 if (looking_for
& (PCREL
| DISP
))
260 else if (looking_for
& ABSJMP
)
262 abs
= (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
264 else if (looking_for
& MEMIND
)
268 else if (looking_for
& L_32
)
272 abs
= (data
[i
] << 24)
273 | (data
[i
+ 1] << 16)
279 else if (looking_for
& L_24
)
283 abs
= (data
[i
] << 16) | (data
[i
+ 1] << 8) | (data
[i
+ 2]);
286 else if (looking_for
& IGNORE
)
290 else if (looking_for
& DISPREG
)
292 rdisp
= thisnib
& 0x7;
294 else if (looking_for
& KBIT
)
311 else if (looking_for
& L_8
)
315 if (looking_for
& PCREL
)
317 abs
= SEXTCHAR (data
[len
>> 1]);
319 else if (looking_for
& ABS8MEM
)
322 abs
= h8300hmode
? ~0xff0000ff : ~0xffff00ff;
323 abs
|= data
[len
>> 1] & 0xff;
327 abs
= data
[len
>> 1] & 0xff;
330 else if (looking_for
& L_3
)
336 else if (looking_for
== E
)
340 /* Fill in the args. */
342 op_type
*args
= q
->args
.nib
;
348 int rn
= (x
& DST
) ? rd
: rs
;
358 p
->type
= X (OP_IMM
, size
);
361 else if (x
& (IMM
| KBIT
| DBIT
))
363 p
->type
= X (OP_IMM
, size
);
369 Some ops (like mul) have two sizes. */
372 p
->type
= X (OP_REG
, size
);
377 p
->type
= X (OP_INC
, size
);
382 p
->type
= X (OP_DEC
, size
);
387 p
->type
= X (OP_DISP
, size
);
391 else if (x
& (ABS
| ABSJMP
| ABS8MEM
))
393 p
->type
= X (OP_DISP
, size
);
399 p
->type
= X (OP_MEM
, size
);
404 p
->type
= X (OP_PCREL
, size
);
405 p
->literal
= abs
+ addr
+ 2;
411 p
->type
= X (OP_IMM
, SP
);
416 p
->type
= X (OP_DISP
, size
);
418 p
->reg
= rdisp
& 0x7;
429 printf ("Hmmmm %x", x
);
435 /* But a jmp or a jsr gets automagically lvalued,
436 since we branch to their address not their
438 if (q
->how
== O (O_JSR
, SB
)
439 || q
->how
== O (O_JMP
, SB
))
441 dst
->src
.type
= lvalue (dst
->src
.type
, dst
->src
.reg
);
444 if (dst
->dst
.type
== -1)
447 dst
->opcode
= q
->how
;
448 dst
->cycles
= q
->time
;
450 /* And a jsr to 0xc4 is turned into a magic trap. */
452 if (dst
->opcode
== O (O_JSR
, SB
))
454 if (dst
->src
.literal
== 0xc4)
456 dst
->opcode
= O (O_SYSCALL
, SB
);
460 dst
->next_pc
= addr
+ len
/ 2;
464 printf ("Don't understand %x \n", looking_for
);
475 /* Fell off the end. */
476 dst
->opcode
= O (O_ILL
, SB
);
484 /* Find the next cache entry to use. */
485 idx
= cpu
.cache_top
+ 1;
487 if (idx
>= cpu
.csize
)
493 /* Throw away its old meaning. */
494 cpu
.cache_idx
[cpu
.cache
[idx
].oldpc
] = 0;
496 /* Set to new address. */
497 cpu
.cache
[idx
].oldpc
= pc
;
499 /* Fill in instruction info. */
500 decode (pc
, cpu
.memory
+ pc
, cpu
.cache
+ idx
);
502 /* Point to new cache entry. */
503 cpu
.cache_idx
[pc
] = idx
;
507 static unsigned char *breg
[18];
508 static unsigned short *wreg
[18];
509 static unsigned int *lreg
[18];
511 #define GET_B_REG(x) *(breg[x])
512 #define SET_B_REG(x,y) (*(breg[x])) = (y)
513 #define GET_W_REG(x) *(wreg[x])
514 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
516 #define GET_L_REG(x) *(lreg[x])
517 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
519 #define GET_MEMORY_L(x) \
521 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
522 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
523 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
524 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
526 #define GET_MEMORY_W(x) \
528 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
529 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
532 #define GET_MEMORY_B(x) \
533 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
535 #define SET_MEMORY_L(x,y) \
536 { register unsigned char *_p; register int __y = y; \
537 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
538 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
539 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
541 #define SET_MEMORY_W(x,y) \
542 { register unsigned char *_p; register int __y = y; \
543 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
544 _p[0] = (__y)>>8; _p[1] =(__y);}
546 #define SET_MEMORY_B(x,y) \
547 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
553 int abs
= arg
->literal
;
560 return GET_B_REG (rn
);
562 return GET_W_REG (rn
);
564 return GET_L_REG (rn
);
575 r
= GET_MEMORY_B (t
);
584 r
= GET_MEMORY_W (t
);
592 r
= GET_MEMORY_L (t
);
599 case X (OP_DISP
, SB
):
600 t
= GET_L_REG (rn
) + abs
;
602 return GET_MEMORY_B (t
);
604 case X (OP_DISP
, SW
):
605 t
= GET_L_REG (rn
) + abs
;
607 return GET_MEMORY_W (t
);
609 case X (OP_DISP
, SL
):
610 t
= GET_L_REG (rn
) + abs
;
612 return GET_MEMORY_L (t
);
615 t
= GET_MEMORY_L (abs
);
620 t
= GET_MEMORY_W (abs
);
625 abort (); /* ?? May be something more usefull? */
632 store (ea_type
*arg
, int n
)
635 int abs
= arg
->literal
;
651 t
= GET_L_REG (rn
) - 1;
658 t
= (GET_L_REG (rn
) - 2) & cpu
.mask
;
664 t
= (GET_L_REG (rn
) - 4) & cpu
.mask
;
669 case X (OP_DISP
, SB
):
670 t
= GET_L_REG (rn
) + abs
;
675 case X (OP_DISP
, SW
):
676 t
= GET_L_REG (rn
) + abs
;
681 case X (OP_DISP
, SL
):
682 t
= GET_L_REG (rn
) + abs
;
718 memory_size
= H8300S_MSIZE
;
720 memory_size
= H8300H_MSIZE
;
722 memory_size
= H8300_MSIZE
;
723 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
724 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
725 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
727 /* `msize' must be a power of two. */
728 if ((memory_size
& (memory_size
- 1)) != 0)
730 cpu
.mask
= memory_size
- 1;
732 for (i
= 0; i
< 9; i
++)
737 for (i
= 0; i
< 8; i
++)
739 unsigned char *p
= (unsigned char *) (cpu
.regs
+ i
);
740 unsigned char *e
= (unsigned char *) (cpu
.regs
+ i
+ 1);
741 unsigned short *q
= (unsigned short *) (cpu
.regs
+ i
);
742 unsigned short *u
= (unsigned short *) (cpu
.regs
+ i
+ 1);
743 cpu
.regs
[i
] = 0x00112233;
756 wreg
[i
] = wreg
[i
+ 8] = 0;
769 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
772 lreg
[i
] = &cpu
.regs
[i
];
775 lreg
[8] = &cpu
.regs
[8];
777 /* Initialize the seg registers. */
779 sim_set_simcache_size (CSIZE
);
786 cpu
.state
= SIM_STATE_STOPPED
;
787 cpu
.exception
= SIGINT
;
797 #define I (intMaskBit != 0)
800 mop (decoded_inst
*code
, int bsize
, int sign
)
810 bsize
? SEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
811 SEXTSHORT (GET_W_REG (code
->dst
.reg
));
813 bsize
? SEXTCHAR (GET_B_REG (code
->src
.reg
)) :
814 SEXTSHORT (GET_W_REG (code
->src
.reg
));
818 multiplicand
= bsize
? UEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
819 UEXTSHORT (GET_W_REG (code
->dst
.reg
));
821 bsize
? UEXTCHAR (GET_B_REG (code
->src
.reg
)) :
822 UEXTSHORT (GET_W_REG (code
->src
.reg
));
825 result
= multiplier
* multiplicand
;
829 n
= result
& (bsize
? 0x8000 : 0x80000000);
830 nz
= result
& (bsize
? 0xffff : 0xffffffff);
834 SET_W_REG (code
->dst
.reg
, result
);
838 SET_L_REG (code
->dst
.reg
, result
);
841 return ((n
== 1) << 1) | (nz
== 1);
845 #define ONOT(name, how) \
850 rd = GET_B_REG (code->src.reg); \
858 rd = GET_W_REG (code->src.reg); \
865 int hm = 0x80000000; \
866 rd = GET_L_REG (code->src.reg); \
871 #define OSHIFTS(name, how1, how2) \
876 rd = GET_B_REG (code->src.reg); \
877 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
891 rd = GET_W_REG (code->src.reg); \
892 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
905 int hm = 0x80000000; \
906 rd = GET_L_REG (code->src.reg); \
907 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
918 #define OBITOP(name,f, s, op) \
923 if (f) ea = fetch (&code->dst); \
924 m=1<< fetch (&code->src); \
926 if (s) store (&code->dst,ea); goto next; \
930 sim_stop (SIM_DESC sd
)
932 cpu
.state
= SIM_STATE_STOPPED
;
933 cpu
.exception
= SIGINT
;
946 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
947 #define FP_REGNUM R6_REGNUM /* Contains address of executing
950 #define CCR_REGNUM 8 /* Contains processor status */
951 #define PC_REGNUM 9 /* Contains program counter */
953 #define CYCLE_REGNUM 10
955 #define EXR_REGNUM 11
956 #define INST_REGNUM 12
957 #define TICK_REGNUM 13
960 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
965 int tick_start
= get_now ();
974 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
979 prev
= signal (SIGINT
, control_c
);
983 cpu
.state
= SIM_STATE_STOPPED
;
984 cpu
.exception
= SIGTRAP
;
988 cpu
.state
= SIM_STATE_RUNNING
;
994 /* The PC should never be odd. */
1010 cidx
= cpu
.cache_idx
[pc
];
1011 code
= cpu
.cache
+ cidx
;
1014 #define ALUOP(STORE, NAME, HOW) \
1015 case O (NAME, SB): HOW; if (STORE) goto alu8; else goto just_flags_alu8; \
1016 case O (NAME, SW): HOW; if (STORE) goto alu16; else goto just_flags_alu16; \
1017 case O (NAME, SL): HOW; if (STORE) goto alu32; else goto just_flags_alu32;
1020 #define LOGOP(NAME, HOW) \
1021 case O (NAME, SB): HOW; goto log8; \
1022 case O (NAME, SW): HOW; goto log16; \
1023 case O (NAME, SL): HOW; goto log32;
1030 printf ("%x %d %s\n", pc
, code
->opcode
,
1031 code
->op
? code
->op
->name
: "**");
1033 cpu
.stats
[code
->opcode
]++;
1039 cycles
+= code
->cycles
;
1043 switch (code
->opcode
)
1047 * This opcode is a fake for when we get to an
1048 * instruction which hasnt been compiled
1055 case O (O_SUBX
, SB
):
1056 rd
= fetch (&code
->dst
);
1057 ea
= fetch (&code
->src
);
1062 case O (O_ADDX
, SB
):
1063 rd
= fetch (&code
->dst
);
1064 ea
= fetch (&code
->src
);
1069 #define EA ea = fetch (&code->src);
1070 #define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst);
1072 ALUOP (1, O_SUB
, RD_EA
;
1075 ALUOP (1, O_NEG
, EA
;
1081 rd
= GET_B_REG (code
->dst
.reg
);
1082 ea
= fetch (&code
->src
);
1086 rd
= GET_W_REG (code
->dst
.reg
);
1087 ea
= fetch (&code
->src
);
1091 rd
= GET_L_REG (code
->dst
.reg
);
1092 ea
= fetch (&code
->src
);
1097 LOGOP (O_AND
, RD_EA
;
1103 LOGOP (O_XOR
, RD_EA
;
1107 case O (O_MOV_TO_MEM
, SB
):
1108 res
= GET_B_REG (code
->src
.reg
);
1110 case O (O_MOV_TO_MEM
, SW
):
1111 res
= GET_W_REG (code
->src
.reg
);
1113 case O (O_MOV_TO_MEM
, SL
):
1114 res
= GET_L_REG (code
->src
.reg
);
1118 case O (O_MOV_TO_REG
, SB
):
1119 res
= fetch (&code
->src
);
1120 SET_B_REG (code
->dst
.reg
, res
);
1121 goto just_flags_log8
;
1122 case O (O_MOV_TO_REG
, SW
):
1123 res
= fetch (&code
->src
);
1124 SET_W_REG (code
->dst
.reg
, res
);
1125 goto just_flags_log16
;
1126 case O (O_MOV_TO_REG
, SL
):
1127 res
= fetch (&code
->src
);
1128 SET_L_REG (code
->dst
.reg
, res
);
1129 goto just_flags_log32
;
1131 case O (O_EEPMOV
, SB
):
1132 case O (O_EEPMOV
, SW
):
1133 if (h8300hmode
|| h8300smode
)
1135 register unsigned char *_src
, *_dst
;
1136 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
1137 ? cpu
.regs
[R4_REGNUM
] & 0xffff
1138 : cpu
.regs
[R4_REGNUM
] & 0xff);
1140 _src
= (cpu
.regs
[R5_REGNUM
] < memory_size
1141 ? cpu
.memory
+ cpu
.regs
[R5_REGNUM
]
1142 : cpu
.eightbit
+ (cpu
.regs
[R5_REGNUM
] & 0xff));
1143 if ((_src
+ count
) >= (cpu
.memory
+ memory_size
))
1145 if ((_src
+ count
) >= (cpu
.eightbit
+ 0x100))
1148 _dst
= (cpu
.regs
[R6_REGNUM
] < memory_size
1149 ? cpu
.memory
+ cpu
.regs
[R6_REGNUM
]
1150 : cpu
.eightbit
+ (cpu
.regs
[R6_REGNUM
] & 0xff));
1151 if ((_dst
+ count
) >= (cpu
.memory
+ memory_size
))
1153 if ((_dst
+ count
) >= (cpu
.eightbit
+ 0x100))
1156 memcpy (_dst
, _src
, count
);
1158 cpu
.regs
[R5_REGNUM
] += count
;
1159 cpu
.regs
[R6_REGNUM
] += count
;
1160 cpu
.regs
[R4_REGNUM
] &= ((code
->opcode
== O (O_EEPMOV
, SW
))
1161 ? (~0xffff) : (~0xff));
1162 cycles
+= 2 * count
;
1167 case O (O_ADDS
, SL
):
1168 SET_L_REG (code
->dst
.reg
,
1169 GET_L_REG (code
->dst
.reg
)
1170 + code
->src
.literal
);
1174 case O (O_SUBS
, SL
):
1175 SET_L_REG (code
->dst
.reg
,
1176 GET_L_REG (code
->dst
.reg
)
1177 - code
->src
.literal
);
1181 rd
= fetch (&code
->dst
);
1182 ea
= fetch (&code
->src
);
1185 goto just_flags_alu8
;
1188 rd
= fetch (&code
->dst
);
1189 ea
= fetch (&code
->src
);
1192 goto just_flags_alu16
;
1195 rd
= fetch (&code
->dst
);
1196 ea
= fetch (&code
->src
);
1199 goto just_flags_alu32
;
1203 rd
= GET_B_REG (code
->src
.reg
);
1206 SET_B_REG (code
->src
.reg
, res
);
1207 goto just_flags_inc8
;
1210 rd
= GET_W_REG (code
->dst
.reg
);
1211 ea
= -code
->src
.literal
;
1213 SET_W_REG (code
->dst
.reg
, res
);
1214 goto just_flags_inc16
;
1217 rd
= GET_L_REG (code
->dst
.reg
);
1218 ea
= -code
->src
.literal
;
1220 SET_L_REG (code
->dst
.reg
, res
);
1221 goto just_flags_inc32
;
1225 rd
= GET_B_REG (code
->src
.reg
);
1228 SET_B_REG (code
->src
.reg
, res
);
1229 goto just_flags_inc8
;
1232 rd
= GET_W_REG (code
->dst
.reg
);
1233 ea
= code
->src
.literal
;
1235 SET_W_REG (code
->dst
.reg
, res
);
1236 goto just_flags_inc16
;
1239 rd
= GET_L_REG (code
->dst
.reg
);
1240 ea
= code
->src
.literal
;
1242 SET_L_REG (code
->dst
.reg
, res
);
1243 goto just_flags_inc32
;
1245 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1246 #define GET_EXR(x) BUILDEXR ();x = cpu.exr
1250 res
= fetch (&code
->src
);
1254 if (code
->src
.type
== OP_CCR
)
1258 else if (code
->src
.type
== OP_EXR
&& h8300smode
)
1264 store (&code
->dst
, res
);
1267 case O (O_ANDC
, SB
):
1268 if (code
->dst
.type
== OP_CCR
)
1272 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1278 ea
= code
->src
.literal
;
1283 if (code
->dst
.type
== OP_CCR
)
1287 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1293 ea
= code
->src
.literal
;
1297 case O (O_XORC
, SB
):
1298 if (code
->dst
.type
== OP_CCR
)
1302 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1308 ea
= code
->src
.literal
;
1349 if (((Z
|| (N
^ V
)) == 0))
1355 if (((Z
|| (N
^ V
)) == 1))
1389 case O (O_SYSCALL
, SB
):
1391 char c
= cpu
.regs
[2];
1392 sim_callback
->write_stdout (sim_callback
, &c
, 1);
1396 ONOT (O_NOT
, rd
= ~rd
; v
= 0;);
1398 c
= rd
& hm
; v
= 0; rd
<<= 1,
1399 c
= rd
& (hm
>> 1); v
= 0; rd
<<= 2);
1401 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1,
1402 c
= rd
& 2; v
= 0; rd
= (unsigned int) rd
>> 2);
1404 c
= rd
& hm
; v
= (rd
& hm
) != ((rd
& (hm
>> 1)) << 1); rd
<<= 1,
1405 c
= rd
& (hm
>> 1); v
= (rd
& (hm
>> 1)) != ((rd
& (hm
>> 2)) << 2); rd
<<= 2);
1407 t
= rd
& hm
; c
= rd
& 1; v
= 0; rd
>>= 1; rd
|= t
,
1408 t
= rd
& hm
; c
= rd
& 2; v
= 0; rd
>>= 2; rd
|= t
| t
>> 1);
1410 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
,
1411 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
; c
= rd
& hm
; rd
<<= 1; rd
|= C
);
1413 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
,
1414 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
; c
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
);
1416 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0,
1417 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0; t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
);
1419 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0,
1420 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0; t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
);
1424 pc
= fetch (&code
->src
);
1432 pc
= fetch (&code
->src
);
1439 SET_MEMORY_L (tmp
, code
->next_pc
);
1444 SET_MEMORY_W (tmp
, code
->next_pc
);
1451 pc
= code
->src
.literal
;
1462 pc
= GET_MEMORY_L (tmp
);
1467 pc
= GET_MEMORY_W (tmp
);
1476 cpu
.state
= SIM_STATE_STOPPED
;
1477 cpu
.exception
= SIGILL
;
1479 case O (O_SLEEP
, SN
):
1480 /* FIXME: Doesn't this break for breakpoints when r0
1481 contains just the right (er, wrong) value? */
1482 cpu
.state
= SIM_STATE_STOPPED
;
1483 /* The format of r0 is defined by target newlib. Expand
1484 the macros here instead of looking for .../sys/wait.h. */
1485 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1486 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1487 if (! SIM_WIFEXITED (cpu
.regs
[0]) && SIM_WIFSIGNALED (cpu
.regs
[0]))
1488 cpu
.exception
= SIGILL
;
1490 cpu
.exception
= SIGTRAP
;
1493 cpu
.state
= SIM_STATE_STOPPED
;
1494 cpu
.exception
= SIGTRAP
;
1497 OBITOP (O_BNOT
, 1, 1, ea
^= m
);
1498 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
);
1499 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
);
1500 OBITOP (O_BSET
, 1, 1, ea
|= m
);
1501 OBITOP (O_BLD
, 1, 0, c
= ea
& m
);
1502 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
));
1503 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
1505 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
1507 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
);
1508 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
);
1509 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
);
1510 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
);
1511 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0) != C
);
1512 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
);
1514 #define MOP(bsize, signed) \
1515 mop (code, bsize, signed); \
1518 case O (O_MULS
, SB
):
1521 case O (O_MULS
, SW
):
1524 case O (O_MULU
, SB
):
1527 case O (O_MULU
, SW
):
1532 if (!h8300smode
|| code
->src
.type
!= X (OP_REG
, SL
))
1534 switch (code
->src
.reg
)
1544 res
= fetch (&code
->src
);
1545 store (&code
->src
, res
| 0x80);
1546 goto just_flags_log8
;
1548 case O (O_DIVU
, SB
):
1550 rd
= GET_W_REG (code
->dst
.reg
);
1551 ea
= GET_B_REG (code
->src
.reg
);
1554 tmp
= (unsigned) rd
% ea
;
1555 rd
= (unsigned) rd
/ ea
;
1557 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1563 case O (O_DIVU
, SW
):
1565 rd
= GET_L_REG (code
->dst
.reg
);
1566 ea
= GET_W_REG (code
->src
.reg
);
1571 tmp
= (unsigned) rd
% ea
;
1572 rd
= (unsigned) rd
/ ea
;
1574 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1578 case O (O_DIVS
, SB
):
1581 rd
= SEXTSHORT (GET_W_REG (code
->dst
.reg
));
1582 ea
= SEXTCHAR (GET_B_REG (code
->src
.reg
));
1585 tmp
= (int) rd
% (int) ea
;
1586 rd
= (int) rd
/ (int) ea
;
1592 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1595 case O (O_DIVS
, SW
):
1597 rd
= GET_L_REG (code
->dst
.reg
);
1598 ea
= SEXTSHORT (GET_W_REG (code
->src
.reg
));
1601 tmp
= (int) rd
% (int) ea
;
1602 rd
= (int) rd
/ (int) ea
;
1603 n
= rd
& 0x80000000;
1608 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1611 case O (O_EXTS
, SW
):
1612 rd
= GET_W_REG (code
->src
.reg
) & 0xff; /* Yes, src, not dst. */
1613 ea
= rd
& 0x80 ? -256 : 0;
1616 case O (O_EXTS
, SL
):
1617 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1618 ea
= rd
& 0x8000 ? -65536 : 0;
1621 case O (O_EXTU
, SW
):
1622 rd
= GET_W_REG (code
->src
.reg
) & 0xff;
1626 case O (O_EXTU
, SL
):
1627 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1637 int nregs
, firstreg
, i
;
1639 nregs
= GET_MEMORY_B (pc
+ 1);
1642 firstreg
= GET_MEMORY_B (pc
+ 3);
1644 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
1647 SET_MEMORY_L (cpu
.regs
[7], cpu
.regs
[i
]);
1654 int nregs
, firstreg
, i
;
1656 nregs
= GET_MEMORY_B (pc
+ 1);
1659 firstreg
= GET_MEMORY_B (pc
+ 3);
1661 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
1663 cpu
.regs
[i
] = GET_MEMORY_L (cpu
.regs
[7]);
1671 cpu
.state
= SIM_STATE_STOPPED
;
1672 cpu
.exception
= SIGILL
;
1679 if (code
->dst
.type
== OP_CCR
)
1684 else if (code
->dst
.type
== OP_EXR
&& h8300smode
)
1695 /* When a branch works */
1696 pc
= code
->src
.literal
;
1699 /* Set the cond codes from res */
1702 /* Set the flags after an 8 bit inc/dec operation */
1706 v
= (rd
& 0x7f) == 0x7f;
1710 /* Set the flags after an 16 bit inc/dec operation */
1714 v
= (rd
& 0x7fff) == 0x7fff;
1718 /* Set the flags after an 32 bit inc/dec operation */
1720 n
= res
& 0x80000000;
1721 nz
= res
& 0xffffffff;
1722 v
= (rd
& 0x7fffffff) == 0x7fffffff;
1727 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1730 SET_B_REG (code
->src
.reg
, rd
);
1734 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1737 SET_W_REG (code
->src
.reg
, rd
);
1741 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1742 n
= (rd
& 0x80000000);
1743 nz
= rd
& 0xffffffff;
1744 SET_L_REG (code
->src
.reg
, rd
);
1748 store (&code
->dst
, res
);
1750 /* flags after a 32bit logical operation */
1751 n
= res
& 0x80000000;
1752 nz
= res
& 0xffffffff;
1757 store (&code
->dst
, res
);
1759 /* flags after a 16bit logical operation */
1767 store (&code
->dst
, res
);
1775 SET_B_REG (code
->dst
.reg
, res
);
1780 switch (code
->opcode
/ 4)
1783 v
= ((rd
& 0x80) == (ea
& 0x80)
1784 && (rd
& 0x80) != (res
& 0x80));
1788 v
= ((rd
& 0x80) != (-ea
& 0x80)
1789 && (rd
& 0x80) != (res
& 0x80));
1798 SET_W_REG (code
->dst
.reg
, res
);
1802 c
= (res
& 0x10000);
1803 switch (code
->opcode
/ 4)
1806 v
= ((rd
& 0x8000) == (ea
& 0x8000)
1807 && (rd
& 0x8000) != (res
& 0x8000));
1811 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
1812 && (rd
& 0x8000) != (res
& 0x8000));
1821 SET_L_REG (code
->dst
.reg
, res
);
1823 n
= res
& 0x80000000;
1824 nz
= res
& 0xffffffff;
1825 switch (code
->opcode
/ 4)
1828 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
1829 && (rd
& 0x80000000) != (res
& 0x80000000));
1830 c
= ((unsigned) res
< (unsigned) rd
) || ((unsigned) res
< (unsigned) ea
);
1834 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
1835 && (rd
& 0x80000000) != (res
& 0x80000000));
1836 c
= (unsigned) rd
< (unsigned) -ea
;
1839 v
= (rd
== 0x80000000);
1855 if (--poll_count
< 0)
1857 poll_count
= POLL_QUIT_INTERVAL
;
1858 if ((*sim_callback
->poll_quit
) != NULL
1859 && (*sim_callback
->poll_quit
) (sim_callback
))
1864 while (cpu
.state
== SIM_STATE_RUNNING
);
1865 cpu
.ticks
+= get_now () - tick_start
;
1866 cpu
.cycles
+= cycles
;
1873 signal (SIGINT
, prev
);
1877 sim_trace (SIM_DESC sd
)
1879 /* FIXME: Unfinished. */
1884 sim_write (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
1891 for (i
= 0; i
< size
; i
++)
1893 if (addr
< memory_size
)
1895 cpu
.memory
[addr
+ i
] = buffer
[i
];
1896 cpu
.cache_idx
[addr
+ i
] = 0;
1899 cpu
.eightbit
[(addr
+ i
) & 0xff] = buffer
[i
];
1905 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
1910 if (addr
< memory_size
)
1911 memcpy (buffer
, cpu
.memory
+ addr
, size
);
1913 memcpy (buffer
, cpu
.eightbit
+ (addr
& 0xff), size
);
1919 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *value
, int length
)
1924 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
1925 shortval
= (value
[0] << 8) | (value
[1]);
1926 intval
= h8300hmode
? longval
: shortval
;
1944 cpu
.regs
[rn
] = intval
;
1953 cpu
.cycles
= longval
;
1957 cpu
.insts
= longval
;
1961 cpu
.ticks
= longval
;
1968 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *buf
, int length
)
1975 if (!h8300smode
&& rn
>= EXR_REGNUM
)
2013 if (h8300hmode
|| longreg
)
2029 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
2031 #if 0 /* FIXME: This should work but we can't use it.
2032 grep for SLEEP above. */
2035 case SIM_STATE_EXITED
: *reason
= sim_exited
; break;
2036 case SIM_STATE_SIGNALLED
: *reason
= sim_signalled
; break;
2037 case SIM_STATE_STOPPED
: *reason
= sim_stopped
; break;
2041 *reason
= sim_stopped
;
2043 *sigrc
= cpu
.exception
;
2046 /* FIXME: Rename to sim_set_mem_size. */
2051 /* Memory size is fixed. */
2055 sim_set_simcache_size (int n
)
2061 cpu
.cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
2062 memset (cpu
.cache
, 0, sizeof (decoded_inst
) * n
);
2068 sim_info (SIM_DESC sd
, int verbose
)
2070 double timetaken
= (double) cpu
.ticks
/ (double) now_persec ();
2071 double virttime
= cpu
.cycles
/ 10.0e6
;
2073 (*sim_callback
->printf_filtered
) (sim_callback
,
2074 "\n\n#instructions executed %10d\n",
2076 (*sim_callback
->printf_filtered
) (sim_callback
,
2077 "#cycles (v approximate) %10d\n",
2079 (*sim_callback
->printf_filtered
) (sim_callback
,
2080 "#real time taken %10.4f\n",
2082 (*sim_callback
->printf_filtered
) (sim_callback
,
2083 "#virtual time taked %10.4f\n",
2085 if (timetaken
!= 0.0)
2086 (*sim_callback
->printf_filtered
) (sim_callback
,
2087 "#simulation ratio %10.4f\n",
2088 virttime
/ timetaken
);
2089 (*sim_callback
->printf_filtered
) (sim_callback
,
2092 (*sim_callback
->printf_filtered
) (sim_callback
,
2093 "#cache size %10d\n",
2097 /* This to be conditional on `what' (aka `verbose'),
2098 however it was never passed as non-zero. */
2102 for (i
= 0; i
< O_LAST
; i
++)
2105 (*sim_callback
->printf_filtered
) (sim_callback
,
2106 "%d: %d\n", i
, cpu
.stats
[i
]);
2112 /* Indicate whether the cpu is an H8/300 or H8/300H.
2113 FLAG is non-zero for the H8/300H. */
2116 set_h8300h (int h_flag
, int s_flag
)
2118 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2119 This function being replaced by a sim_open:ARGV configuration
2121 h8300hmode
= h_flag
;
2122 h8300smode
= s_flag
;
2126 sim_open (SIM_OPEN_KIND kind
,
2127 struct host_callback_struct
*ptr
,
2131 /* FIXME: Much of the code in sim_load can be moved here. */
2136 /* Fudge our descriptor. */
2137 return (SIM_DESC
) 1;
2141 sim_close (SIM_DESC sd
, int quitting
)
2143 /* Nothing to do. */
2146 /* Called by gdb to load a program into memory. */
2149 sim_load (SIM_DESC sd
, char *prog
, bfd
*abfd
, int from_tty
)
2153 /* FIXME: The code below that sets a specific variant of the H8/300
2154 being simulated should be moved to sim_open(). */
2156 /* See if the file is for the H8/300 or H8/300H. */
2157 /* ??? This may not be the most efficient way. The z8k simulator
2158 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2162 prog_bfd
= bfd_openr (prog
, "coff-h8300");
2163 if (prog_bfd
!= NULL
)
2165 /* Set the cpu type. We ignore failure from bfd_check_format
2166 and bfd_openr as sim_load_file checks too. */
2167 if (bfd_check_format (prog_bfd
, bfd_object
))
2169 unsigned long mach
= bfd_get_mach (prog_bfd
);
2170 set_h8300h (mach
== bfd_mach_h8300h
|| mach
== bfd_mach_h8300s
,
2171 mach
== bfd_mach_h8300s
);
2175 /* If we're using gdb attached to the simulator, then we have to
2176 reallocate memory for the simulator.
2178 When gdb first starts, it calls fetch_registers (among other
2179 functions), which in turn calls init_pointers, which allocates
2182 The problem is when we do that, we don't know whether we're
2183 debugging an H8/300 or H8/300H program.
2185 This is the first point at which we can make that determination,
2186 so we just reallocate memory now; this will also allow us to handle
2187 switching between H8/300 and H8/300H programs without exiting
2191 memory_size
= H8300S_MSIZE
;
2192 else if (h8300hmode
)
2193 memory_size
= H8300H_MSIZE
;
2195 memory_size
= H8300_MSIZE
;
2200 free (cpu
.cache_idx
);
2202 free (cpu
.eightbit
);
2204 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
2205 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
2206 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
2208 /* `msize' must be a power of two. */
2209 if ((memory_size
& (memory_size
- 1)) != 0)
2211 cpu
.mask
= memory_size
- 1;
2213 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
2214 sim_kind
== SIM_OPEN_DEBUG
,
2218 /* Close the bfd if we opened it. */
2219 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2220 bfd_close (prog_bfd
);
2224 /* Close the bfd if we opened it. */
2225 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2226 bfd_close (prog_bfd
);
2231 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
2234 cpu
.pc
= bfd_get_start_address (abfd
);
2241 sim_do_command (SIM_DESC sd
, char *cmd
)
2243 (*sim_callback
->printf_filtered
) (sim_callback
,
2244 "This simulator does not accept any commands.\n");
2248 sim_set_callbacks (struct host_callback_struct
*ptr
)