]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/h8300/compile.c
2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
29 #ifdef HAVE_SYS_PARAM_H
30 #include <sys/param.h>
36 #include "remote-sim.h"
44 host_callback
*sim_callback
;
46 static SIM_OPEN_KIND sim_kind
;
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
53 void sim_set_simcache_size
PARAMS ((int));
55 #define X(op, size) op*4+size
57 #define SP (h8300hmode ? SL:SW)
70 #define h8_opcodes ops
72 #include "opcode/h8300.h"
76 #define LOW_BYTE(x) ((x) & 0xff)
77 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
78 #define P(X,Y) ((X<<8) | Y)
80 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
83 c = (cpu.ccr >> 0) & 1;\
84 v = (cpu.ccr >> 1) & 1;\
85 nz = !((cpu.ccr >> 2) & 1);\
86 n = (cpu.ccr >> 3) & 1;
88 #ifdef __CHAR_IS_SIGNED__
89 #define SEXTCHAR(x) ((char)(x))
93 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
96 #define UEXTCHAR(x) ((x) & 0xff)
97 #define UEXTSHORT(x) ((x) & 0xffff)
98 #define SEXTSHORT(x) ((short)(x))
100 static cpu_state_type cpu
;
105 static int memory_size
;
136 return h8300hmode
? SL
: SW
;
149 return X (OP_IMM
, SP
);
151 return X (OP_REG
, SP
);
155 return X (OP_MEM
, SP
);
162 decode (addr
, data
, dst
)
175 struct h8_opcode
*q
= h8_opcodes
;
179 /* Find the exact opcode/arg combo */
183 unsigned int len
= 0;
189 op_type looking_for
= *nib
;
190 int thisnib
= data
[len
>> 1];
192 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
194 if (looking_for
< 16 && looking_for
>= 0)
196 if (looking_for
!= thisnib
)
201 if ((int) looking_for
& (int) B31
)
203 if (!(((int) thisnib
& 0x8) != 0))
205 looking_for
= (op_type
) ((int) looking_for
& ~(int)
209 if ((int) looking_for
& (int) B30
)
211 if (!(((int) thisnib
& 0x8) == 0))
213 looking_for
= (op_type
) ((int) looking_for
& ~(int) B30
);
215 if (looking_for
& DBIT
)
217 if ((looking_for
& 5) != (thisnib
& 5))
219 abs
= (thisnib
& 0x8) ? 2 : 1;
221 else if (looking_for
& (REG
| IND
| INC
| DEC
))
223 if (looking_for
& REG
)
226 * Can work out size from the
229 size
= bitfrom (looking_for
);
231 if (looking_for
& SRC
)
240 else if (looking_for
& L_16
)
242 abs
= (data
[len
>> 1]) * 256 + data
[(len
+ 2) >> 1];
244 if (looking_for
& (PCREL
| DISP
))
249 else if (looking_for
& ABSJMP
)
256 else if (looking_for
& MEMIND
)
260 else if (looking_for
& L_32
)
263 abs
= (data
[i
] << 24)
264 | (data
[i
+ 1] << 16)
270 else if (looking_for
& L_24
)
273 abs
= (data
[i
] << 16) | (data
[i
+ 1] << 8) | (data
[i
+ 2]);
276 else if (looking_for
& IGNORE
)
280 else if (looking_for
& DISPREG
)
282 rdisp
= thisnib
& 0x7;
284 else if (looking_for
& KBIT
)
299 else if (looking_for
& L_8
)
303 if (looking_for
& PCREL
)
305 abs
= SEXTCHAR (data
[len
>> 1]);
307 else if (looking_for
& ABS8MEM
)
310 abs
= h8300hmode
? ~0xff0000ff : ~0xffff00ff;
311 abs
|= data
[len
>> 1] & 0xff ;
315 abs
= data
[len
>> 1] & 0xff;
318 else if (looking_for
& L_3
)
324 else if (looking_for
== E
)
328 /* Fill in the args */
330 op_type
*args
= q
->args
.nib
;
336 int rn
= (x
& DST
) ? rd
: rs
;
350 p
->type
= X (OP_IMM
, size
);
353 else if (x
& (IMM
| KBIT
| DBIT
))
355 p
->type
= X (OP_IMM
, size
);
360 /* Reset the size, some
361 ops (like mul) have two sizes */
364 p
->type
= X (OP_REG
, size
);
369 p
->type
= X (OP_INC
, size
);
374 p
->type
= X (OP_DEC
, size
);
379 p
->type
= X (OP_DISP
, size
);
383 else if (x
& (ABS
| ABSJMP
| ABS8MEM
))
385 p
->type
= X (OP_DISP
, size
);
391 p
->type
= X (OP_MEM
, size
);
396 p
->type
= X (OP_PCREL
, size
);
397 p
->literal
= abs
+ addr
+ 2;
403 p
->type
= X (OP_IMM
, SP
);
408 p
->type
= X (OP_DISP
, size
);
410 p
->reg
= rdisp
& 0x7;
417 printf ("Hmmmm %x", x
);
424 * But a jmp or a jsr gets
425 * automagically lvalued, since we
426 * branch to their address not their
429 if (q
->how
== O (O_JSR
, SB
)
430 || q
->how
== O (O_JMP
, SB
))
432 dst
->src
.type
= lvalue (dst
->src
.type
, dst
->src
.reg
);
435 if (dst
->dst
.type
== -1)
438 dst
->opcode
= q
->how
;
439 dst
->cycles
= q
->time
;
441 /* And a jsr to 0xc4 is turned into a magic trap */
443 if (dst
->opcode
== O (O_JSR
, SB
))
445 if (dst
->src
.literal
== 0xc4)
447 dst
->opcode
= O (O_SYSCALL
, SB
);
451 dst
->next_pc
= addr
+ len
/ 2;
456 printf ("Dont understand %x \n", looking_for
);
468 dst
->opcode
= O (O_ILL
, SB
);
477 /* find the next cache entry to use */
479 idx
= cpu
.cache_top
+ 1;
481 if (idx
>= cpu
.csize
)
487 /* Throw away its old meaning */
488 cpu
.cache_idx
[cpu
.cache
[idx
].oldpc
] = 0;
490 /* set to new address */
491 cpu
.cache
[idx
].oldpc
= pc
;
493 /* fill in instruction info */
494 decode (pc
, cpu
.memory
+ pc
, cpu
.cache
+ idx
);
496 /* point to new cache entry */
497 cpu
.cache_idx
[pc
] = idx
;
501 static unsigned char *breg
[18];
502 static unsigned short *wreg
[18];
503 static unsigned int *lreg
[18];
505 #define GET_B_REG(x) *(breg[x])
506 #define SET_B_REG(x,y) (*(breg[x])) = (y)
507 #define GET_W_REG(x) *(wreg[x])
508 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
510 #define GET_L_REG(x) *(lreg[x])
511 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
513 #define GET_MEMORY_L(x) \
515 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
516 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
517 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
518 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
520 #define GET_MEMORY_W(x) \
522 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
523 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
526 #define GET_MEMORY_B(x) \
527 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
529 #define SET_MEMORY_L(x,y) \
530 { register unsigned char *_p; register int __y = y; \
531 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
532 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
533 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
535 #define SET_MEMORY_W(x,y) \
536 { register unsigned char *_p; register int __y = y; \
537 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
538 _p[0] = (__y)>>8; _p[1] =(__y);}
540 #define SET_MEMORY_B(x,y) \
541 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
548 int abs
= arg
->literal
;
555 return GET_B_REG (rn
);
557 return GET_W_REG (rn
);
559 return GET_L_REG (rn
);
570 r
= GET_MEMORY_B (t
);
579 r
= GET_MEMORY_W (t
);
587 r
= GET_MEMORY_L (t
);
594 case X (OP_DISP
, SB
):
595 t
= GET_L_REG (rn
) + abs
;
597 return GET_MEMORY_B (t
);
599 case X (OP_DISP
, SW
):
600 t
= GET_L_REG (rn
) + abs
;
602 return GET_MEMORY_W (t
);
604 case X (OP_DISP
, SL
):
605 t
= GET_L_REG (rn
) + abs
;
607 return GET_MEMORY_L (t
);
610 t
= GET_MEMORY_L (abs
);
615 t
= GET_MEMORY_W (abs
);
633 int abs
= arg
->literal
;
649 t
= GET_L_REG (rn
) - 1;
656 t
= (GET_L_REG (rn
) - 2) & cpu
.mask
;
662 t
= (GET_L_REG (rn
) - 4) & cpu
.mask
;
667 case X (OP_DISP
, SB
):
668 t
= GET_L_REG (rn
) + abs
;
673 case X (OP_DISP
, SW
):
674 t
= GET_L_REG (rn
) + abs
;
679 case X (OP_DISP
, SL
):
680 t
= GET_L_REG (rn
) + abs
;
717 memory_size
= H8300H_MSIZE
;
719 memory_size
= H8300_MSIZE
;
720 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
721 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
722 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
724 /* `msize' must be a power of two */
725 if ((memory_size
& (memory_size
- 1)) != 0)
727 cpu
.mask
= memory_size
- 1;
729 for (i
= 0; i
< 9; i
++)
734 for (i
= 0; i
< 8; i
++)
736 unsigned char *p
= (unsigned char *) (cpu
.regs
+ i
);
737 unsigned char *e
= (unsigned char *) (cpu
.regs
+ i
+ 1);
738 unsigned short *q
= (unsigned short *) (cpu
.regs
+ i
);
739 unsigned short *u
= (unsigned short *) (cpu
.regs
+ i
+ 1);
740 cpu
.regs
[i
] = 0x00112233;
766 lreg
[i
] = &cpu
.regs
[i
];
769 lreg
[8] = &cpu
.regs
[8];
771 /* initialize the seg registers */
773 sim_set_simcache_size (CSIZE
);
778 control_c (sig
, code
, scp
, addr
)
784 cpu
.state
= SIM_STATE_STOPPED
;
785 cpu
.exception
= SIGINT
;
794 mop (code
, bsize
, sign
)
807 bsize
? SEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
808 SEXTSHORT (GET_W_REG (code
->dst
.reg
));
810 bsize
? SEXTCHAR (GET_B_REG (code
->src
.reg
)) :
811 SEXTSHORT (GET_W_REG (code
->src
.reg
));
815 multiplicand
= bsize
? UEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
816 UEXTSHORT (GET_W_REG (code
->dst
.reg
));
818 bsize
? UEXTCHAR (GET_B_REG (code
->src
.reg
)) :
819 UEXTSHORT (GET_W_REG (code
->src
.reg
));
822 result
= multiplier
* multiplicand
;
826 n
= result
& (bsize
? 0x8000 : 0x80000000);
827 nz
= result
& (bsize
? 0xffff : 0xffffffff);
831 SET_W_REG (code
->dst
.reg
, result
);
835 SET_L_REG (code
->dst
.reg
, result
);
837 /* return ((n==1) << 1) | (nz==1); */
841 #define ONOT(name, how) \
846 rd = GET_B_REG (code->src.reg); \
854 rd = GET_W_REG (code->src.reg); \
861 int hm = 0x80000000; \
862 rd = GET_L_REG (code->src.reg); \
867 #define OSHIFTS(name, how1, how2) \
872 rd = GET_B_REG (code->src.reg); \
873 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
887 rd = GET_W_REG (code->src.reg); \
888 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
901 int hm = 0x80000000; \
902 rd = GET_L_REG (code->src.reg); \
903 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
914 #define OBITOP(name,f, s, op) \
919 if (f) ea = fetch (&code->dst); \
920 m=1<< fetch(&code->src); \
922 if(s) store (&code->dst,ea); goto next; \
929 cpu
.state
= SIM_STATE_STOPPED
;
930 cpu
.exception
= SIGINT
;
935 sim_resume (sd
, step
, siggnal
)
941 int tick_start
= get_now ();
954 prev
= signal (SIGINT
, control_c
);
958 cpu
.state
= SIM_STATE_STOPPED
;
959 cpu
.exception
= SIGTRAP
;
963 cpu
.state
= SIM_STATE_RUNNING
;
969 /* The PC should never be odd. */
983 cidx
= cpu
.cache_idx
[pc
];
984 code
= cpu
.cache
+ cidx
;
987 #define ALUOP(STORE, NAME, HOW) \
988 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
989 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
990 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
993 #define LOGOP(NAME, HOW) \
994 case O(NAME,SB): HOW; goto log8;\
995 case O(NAME, SW): HOW; goto log16;\
996 case O(NAME,SL): HOW; goto log32;
1003 printf ("%x %d %s\n", pc
, code
->opcode
,
1004 code
->op
? code
->op
->name
: "**");
1006 cpu
.stats
[code
->opcode
]++;
1010 cycles
+= code
->cycles
;
1012 switch (code
->opcode
)
1016 * This opcode is a fake for when we get to an
1017 * instruction which hasnt been compiled
1024 case O (O_SUBX
, SB
):
1025 rd
= fetch (&code
->dst
);
1026 ea
= fetch (&code
->src
);
1031 case O (O_ADDX
, SB
):
1032 rd
= fetch (&code
->dst
);
1033 ea
= fetch (&code
->src
);
1038 #define EA ea = fetch(&code->src);
1039 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1041 ALUOP (1, O_SUB
, RD_EA
;
1044 ALUOP (1, O_NEG
, EA
;
1050 rd
= GET_B_REG (code
->dst
.reg
);
1051 ea
= fetch (&code
->src
);
1055 rd
= GET_W_REG (code
->dst
.reg
);
1056 ea
= fetch (&code
->src
);
1060 rd
= GET_L_REG (code
->dst
.reg
);
1061 ea
= fetch (&code
->src
);
1066 LOGOP (O_AND
, RD_EA
;
1072 LOGOP (O_XOR
, RD_EA
;
1076 case O (O_MOV_TO_MEM
, SB
):
1077 res
= GET_B_REG (code
->src
.reg
);
1079 case O (O_MOV_TO_MEM
, SW
):
1080 res
= GET_W_REG (code
->src
.reg
);
1082 case O (O_MOV_TO_MEM
, SL
):
1083 res
= GET_L_REG (code
->src
.reg
);
1087 case O (O_MOV_TO_REG
, SB
):
1088 res
= fetch (&code
->src
);
1089 SET_B_REG (code
->dst
.reg
, res
);
1090 goto just_flags_log8
;
1091 case O (O_MOV_TO_REG
, SW
):
1092 res
= fetch (&code
->src
);
1093 SET_W_REG (code
->dst
.reg
, res
);
1094 goto just_flags_log16
;
1095 case O (O_MOV_TO_REG
, SL
):
1096 res
= fetch (&code
->src
);
1097 SET_L_REG (code
->dst
.reg
, res
);
1098 goto just_flags_log32
;
1101 case O (O_ADDS
, SL
):
1102 SET_L_REG (code
->dst
.reg
,
1103 GET_L_REG (code
->dst
.reg
)
1104 + code
->src
.literal
);
1108 case O (O_SUBS
, SL
):
1109 SET_L_REG (code
->dst
.reg
,
1110 GET_L_REG (code
->dst
.reg
)
1111 - code
->src
.literal
);
1115 rd
= fetch (&code
->dst
);
1116 ea
= fetch (&code
->src
);
1119 goto just_flags_alu8
;
1122 rd
= fetch (&code
->dst
);
1123 ea
= fetch (&code
->src
);
1126 goto just_flags_alu16
;
1129 rd
= fetch (&code
->dst
);
1130 ea
= fetch (&code
->src
);
1133 goto just_flags_alu32
;
1137 rd
= GET_B_REG (code
->src
.reg
);
1140 SET_B_REG (code
->src
.reg
, res
);
1141 goto just_flags_inc8
;
1144 rd
= GET_W_REG (code
->dst
.reg
);
1145 ea
= -code
->src
.literal
;
1147 SET_W_REG (code
->dst
.reg
, res
);
1148 goto just_flags_inc16
;
1151 rd
= GET_L_REG (code
->dst
.reg
);
1152 ea
= -code
->src
.literal
;
1154 SET_L_REG (code
->dst
.reg
, res
);
1155 goto just_flags_inc32
;
1159 rd
= GET_B_REG (code
->src
.reg
);
1162 SET_B_REG (code
->src
.reg
, res
);
1163 goto just_flags_inc8
;
1166 rd
= GET_W_REG (code
->dst
.reg
);
1167 ea
= code
->src
.literal
;
1169 SET_W_REG (code
->dst
.reg
, res
);
1170 goto just_flags_inc16
;
1173 rd
= GET_L_REG (code
->dst
.reg
);
1174 ea
= code
->src
.literal
;
1176 SET_L_REG (code
->dst
.reg
, res
);
1177 goto just_flags_inc32
;
1180 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1182 case O (O_ANDC
, SB
):
1184 ea
= code
->src
.literal
;
1190 ea
= code
->src
.literal
;
1194 case O (O_XORC
, SB
):
1196 ea
= code
->src
.literal
;
1237 if (((Z
|| (N
^ V
)) == 0))
1243 if (((Z
|| (N
^ V
)) == 1))
1277 case O (O_SYSCALL
, SB
):
1279 char c
= cpu
.regs
[2];
1280 sim_callback
->write_stdout (sim_callback
, &c
, 1);
1284 ONOT (O_NOT
, rd
= ~rd
; v
= 0;);
1286 c
= rd
& hm
; v
= 0; rd
<<= 1,
1287 c
= rd
& (hm
>> 1); v
= 0; rd
<<= 2);
1289 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1,
1290 c
= rd
& 2; v
= 0; rd
= (unsigned int) rd
>> 2);
1292 c
= rd
& hm
; v
= (rd
& hm
) != ((rd
& (hm
>> 1)) << 1); rd
<<= 1,
1293 c
= rd
& (hm
>> 1); v
= (rd
& (hm
>> 1)) != ((rd
& (hm
>> 2)) << 2); rd
<<= 2);
1295 t
= rd
& hm
; c
= rd
& 1; v
= 0; rd
>>= 1; rd
|= t
,
1296 t
= rd
& hm
; c
= rd
& 2; v
= 0; rd
>>= 2; rd
|= t
| t
>> 1 );
1298 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
,
1299 c
= rd
& hm
; v
= 0; rd
<<= 1; rd
|= C
; c
= rd
& hm
; rd
<<= 1; rd
|= C
);
1301 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
,
1302 c
= rd
& 1; v
= 0; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
; c
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (c
) rd
|= hm
);
1304 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0,
1305 t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
; v
= 0; t
= rd
& hm
; rd
<<= 1; rd
|= C
; c
= t
);
1307 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0,
1308 t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
; v
= 0; t
= rd
& 1; rd
= (unsigned int) rd
>> 1; if (C
) rd
|= hm
; c
= t
);
1312 pc
= fetch (&code
->src
);
1320 pc
= fetch (&code
->src
);
1327 SET_MEMORY_L (tmp
, code
->next_pc
);
1332 SET_MEMORY_W (tmp
, code
->next_pc
);
1339 pc
= code
->src
.literal
;
1350 pc
= GET_MEMORY_L (tmp
);
1355 pc
= GET_MEMORY_W (tmp
);
1364 cpu
.state
= SIM_STATE_STOPPED
;
1365 cpu
.exception
= SIGILL
;
1367 case O (O_SLEEP
, SN
):
1368 /* The format of r0 is defined by devo/include/wait.h. */
1369 #if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */
1370 if (WIFEXITED (cpu
.regs
[0]))
1372 cpu
.state
= SIM_STATE_EXITED
;
1373 cpu
.exception
= WEXITSTATUS (cpu
.regs
[0]);
1375 else if (WIFSTOPPED (cpu
.regs
[0]))
1377 cpu
.state
= SIM_STATE_STOPPED
;
1378 cpu
.exception
= WSTOPSIG (cpu
.regs
[0]);
1382 cpu
.state
= SIM_STATE_SIGNALLED
;
1383 cpu
.exception
= WTERMSIG (cpu
.regs
[0]);
1386 /* FIXME: Doesn't this break for breakpoints when r0
1387 contains just the right (er, wrong) value? */
1388 cpu
.state
= SIM_STATE_STOPPED
;
1389 if (! WIFEXITED (cpu
.regs
[0]) && WIFSIGNALED (cpu
.regs
[0]))
1390 cpu
.exception
= SIGILL
;
1392 cpu
.exception
= SIGTRAP
;
1396 cpu
.state
= SIM_STATE_STOPPED
;
1397 cpu
.exception
= SIGTRAP
;
1400 OBITOP (O_BNOT
, 1, 1, ea
^= m
);
1401 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
);
1402 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
);
1403 OBITOP (O_BSET
, 1, 1, ea
|= m
);
1404 OBITOP (O_BLD
, 1, 0, c
= ea
& m
);
1405 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
));
1406 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
1408 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
1410 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
);
1411 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
);
1412 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
);
1413 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
);
1414 OBITOP (O_BXOR
, 1, 0, c
= (ea
& m
) != C
);
1415 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
);
1418 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1420 case O (O_MULS
, SB
):
1423 case O (O_MULS
, SW
):
1426 case O (O_MULU
, SB
):
1429 case O (O_MULU
, SW
):
1434 case O (O_DIVU
, SB
):
1436 rd
= GET_W_REG (code
->dst
.reg
);
1437 ea
= GET_B_REG (code
->src
.reg
);
1440 tmp
= (unsigned)rd
% ea
;
1441 rd
= (unsigned)rd
/ ea
;
1443 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1449 case O (O_DIVU
, SW
):
1451 rd
= GET_L_REG (code
->dst
.reg
);
1452 ea
= GET_W_REG (code
->src
.reg
);
1457 tmp
= (unsigned)rd
% ea
;
1458 rd
= (unsigned)rd
/ ea
;
1460 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1464 case O (O_DIVS
, SB
):
1467 rd
= SEXTSHORT (GET_W_REG (code
->dst
.reg
));
1468 ea
= SEXTCHAR (GET_B_REG (code
->src
.reg
));
1471 tmp
= (int) rd
% (int) ea
;
1472 rd
= (int) rd
/ (int) ea
;
1478 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1481 case O (O_DIVS
, SW
):
1483 rd
= GET_L_REG (code
->dst
.reg
);
1484 ea
= SEXTSHORT (GET_W_REG (code
->src
.reg
));
1487 tmp
= (int) rd
% (int) ea
;
1488 rd
= (int) rd
/ (int) ea
;
1489 n
= rd
& 0x80000000;
1494 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1497 case O (O_EXTS
, SW
):
1498 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff; /* Yes, src, not dst. */
1499 ea
= rd
& 0x80 ? -256 : 0;
1502 case O (O_EXTS
, SL
):
1503 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1504 ea
= rd
& 0x8000 ? -65536 : 0;
1507 case O (O_EXTU
, SW
):
1508 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff;
1512 case O (O_EXTU
, SL
):
1513 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1523 int nregs
, firstreg
, i
;
1525 nregs
= GET_MEMORY_B (pc
+ 1);
1528 firstreg
= GET_MEMORY_B (pc
+ 3);
1530 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
1533 SET_MEMORY_L (cpu
.regs
[7], cpu
.regs
[i
]);
1540 int nregs
, firstreg
, i
;
1542 nregs
= GET_MEMORY_B (pc
+ 1);
1545 firstreg
= GET_MEMORY_B (pc
+ 3);
1547 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
1549 cpu
.regs
[i
] = GET_MEMORY_L (cpu
.regs
[7]);
1556 cpu
.state
= SIM_STATE_STOPPED
;
1557 cpu
.exception
= SIGILL
;
1569 /* When a branch works */
1570 pc
= code
->src
.literal
;
1573 /* Set the cond codes from res */
1576 /* Set the flags after an 8 bit inc/dec operation */
1580 v
= (rd
& 0x7f) == 0x7f;
1584 /* Set the flags after an 16 bit inc/dec operation */
1588 v
= (rd
& 0x7fff) == 0x7fff;
1592 /* Set the flags after an 32 bit inc/dec operation */
1594 n
= res
& 0x80000000;
1595 nz
= res
& 0xffffffff;
1596 v
= (rd
& 0x7fffffff) == 0x7fffffff;
1601 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1604 SET_B_REG (code
->src
.reg
, rd
);
1608 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1611 SET_W_REG (code
->src
.reg
, rd
);
1615 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1616 n
= (rd
& 0x80000000);
1617 nz
= rd
& 0xffffffff;
1618 SET_L_REG (code
->src
.reg
, rd
);
1622 store (&code
->dst
, res
);
1624 /* flags after a 32bit logical operation */
1625 n
= res
& 0x80000000;
1626 nz
= res
& 0xffffffff;
1631 store (&code
->dst
, res
);
1633 /* flags after a 16bit logical operation */
1641 store (&code
->dst
, res
);
1649 SET_B_REG (code
->dst
.reg
, res
);
1654 switch (code
->opcode
/ 4)
1657 v
= ((rd
& 0x80) == (ea
& 0x80)
1658 && (rd
& 0x80) != (res
& 0x80));
1662 v
= ((rd
& 0x80) != (-ea
& 0x80)
1663 && (rd
& 0x80) != (res
& 0x80));
1672 SET_W_REG (code
->dst
.reg
, res
);
1676 c
= (res
& 0x10000);
1677 switch (code
->opcode
/ 4)
1680 v
= ((rd
& 0x8000) == (ea
& 0x8000)
1681 && (rd
& 0x8000) != (res
& 0x8000));
1685 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
1686 && (rd
& 0x8000) != (res
& 0x8000));
1695 SET_L_REG (code
->dst
.reg
, res
);
1697 n
= res
& 0x80000000;
1698 nz
= res
& 0xffffffff;
1699 switch (code
->opcode
/ 4)
1702 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
1703 && (rd
& 0x80000000) != (res
& 0x80000000));
1704 c
= ((unsigned) res
< (unsigned) rd
) || ((unsigned) res
< (unsigned) ea
);
1708 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
1709 && (rd
& 0x80000000) != (res
& 0x80000000));
1710 c
= (unsigned) rd
< (unsigned) -ea
;
1713 v
= (rd
== 0x80000000);
1724 /* if (cpu.regs[8] ) abort(); */
1726 if (--poll_count
< 0)
1729 if ((*sim_callback
->poll_quit
) != NULL
1730 && (*sim_callback
->poll_quit
) (sim_callback
))
1735 while (cpu
.state
== SIM_STATE_RUNNING
);
1736 cpu
.ticks
+= get_now () - tick_start
;
1737 cpu
.cycles
+= cycles
;
1743 signal (SIGINT
, prev
);
1750 /* FIXME: unfinished */
1755 sim_write (sd
, addr
, buffer
, size
)
1758 unsigned char *buffer
;
1766 for (i
= 0; i
< size
; i
++)
1768 if (addr
< memory_size
)
1770 cpu
.memory
[addr
+ i
] = buffer
[i
];
1771 cpu
.cache_idx
[addr
+ i
] = 0;
1774 cpu
.eightbit
[(addr
+ i
) & 0xff] = buffer
[i
];
1780 sim_read (sd
, addr
, buffer
, size
)
1783 unsigned char *buffer
;
1789 if (addr
< memory_size
)
1790 memcpy (buffer
, cpu
.memory
+ addr
, size
);
1792 memcpy (buffer
, cpu
.eightbit
+ (addr
& 0xff), size
);
1806 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1807 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1810 #define CCR_REGNUM 8 /* Contains processor status */
1811 #define PC_REGNUM 9 /* Contains program counter */
1813 #define CYCLE_REGNUM 10
1814 #define INST_REGNUM 11
1815 #define TICK_REGNUM 12
1819 sim_store_register (sd
, rn
, value
)
1822 unsigned char *value
;
1827 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
1828 shortval
= (value
[0] << 8) | (value
[1]);
1829 intval
= h8300hmode
? longval
: shortval
;
1847 cpu
.regs
[rn
] = intval
;
1853 cpu
.cycles
= longval
;
1857 cpu
.insts
= longval
;
1861 cpu
.ticks
= longval
;
1867 sim_fetch_register (sd
, rn
, buf
)
1910 if (h8300hmode
|| longreg
)
1925 sim_stop_reason (sd
, reason
, sigrc
)
1927 enum sim_stop
*reason
;
1930 #if 0 /* FIXME: This should work but we can't use it.
1931 grep for SLEEP above. */
1934 case SIM_STATE_EXITED
: *reason
= sim_exited
; break;
1935 case SIM_STATE_SIGNALLED
: *reason
= sim_signalled
; break;
1936 case SIM_STATE_STOPPED
: *reason
= sim_stopped
; break;
1940 *reason
= sim_stopped
;
1942 *sigrc
= cpu
.exception
;
1945 /* FIXME: Rename to sim_set_mem_size. */
1951 /* Memory size is fixed. */
1955 sim_set_simcache_size (n
)
1961 cpu
.cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
1962 memset (cpu
.cache
, 0, sizeof (decoded_inst
) * n
);
1968 sim_info (sd
, verbose
)
1972 double timetaken
= (double) cpu
.ticks
/ (double) now_persec ();
1973 double virttime
= cpu
.cycles
/ 10.0e6
;
1975 (*sim_callback
->printf_filtered
) (sim_callback
,
1976 "\n\n#instructions executed %10d\n",
1978 (*sim_callback
->printf_filtered
) (sim_callback
,
1979 "#cycles (v approximate) %10d\n",
1981 (*sim_callback
->printf_filtered
) (sim_callback
,
1982 "#real time taken %10.4f\n",
1984 (*sim_callback
->printf_filtered
) (sim_callback
,
1985 "#virtual time taked %10.4f\n",
1987 if (timetaken
!= 0.0)
1988 (*sim_callback
->printf_filtered
) (sim_callback
,
1989 "#simulation ratio %10.4f\n",
1990 virttime
/ timetaken
);
1991 (*sim_callback
->printf_filtered
) (sim_callback
,
1994 (*sim_callback
->printf_filtered
) (sim_callback
,
1995 "#cache size %10d\n",
1999 /* This to be conditional on `what' (aka `verbose'),
2000 however it was never passed as non-zero. */
2004 for (i
= 0; i
< O_LAST
; i
++)
2007 (*sim_callback
->printf_filtered
) (sim_callback
,
2008 "%d: %d\n", i
, cpu
.stats
[i
]);
2014 /* Indicate whether the cpu is an h8/300 or h8/300h.
2015 FLAG is non-zero for the h8/300h. */
2021 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2022 This function being replaced by a sim_open:ARGV configuration
2028 sim_open (kind
, ptr
, abfd
, argv
)
2030 struct host_callback_struct
*ptr
;
2034 /* FIXME: Much of the code in sim_load can be moved here */
2039 /* fudge our descriptor */
2040 return (SIM_DESC
) 1;
2044 sim_close (sd
, quitting
)
2051 /* Called by gdb to load a program into memory. */
2054 sim_load (sd
, prog
, abfd
, from_tty
)
2062 /* FIXME: The code below that sets a specific variant of the h8/300
2063 being simulated should be moved to sim_open(). */
2065 /* See if the file is for the h8/300 or h8/300h. */
2066 /* ??? This may not be the most efficient way. The z8k simulator
2067 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2071 prog_bfd
= bfd_openr (prog
, "coff-h8300");
2072 if (prog_bfd
!= NULL
)
2074 /* Set the cpu type. We ignore failure from bfd_check_format
2075 and bfd_openr as sim_load_file checks too. */
2076 if (bfd_check_format (prog_bfd
, bfd_object
))
2078 unsigned long mach
= bfd_get_mach (prog_bfd
);
2079 set_h8300h (mach
== bfd_mach_h8300h
2080 || mach
== bfd_mach_h8300s
);
2084 /* If we're using gdb attached to the simulator, then we have to
2085 reallocate memory for the simulator.
2087 When gdb first starts, it calls fetch_registers (among other
2088 functions), which in turn calls init_pointers, which allocates
2091 The problem is when we do that, we don't know whether we're
2092 debugging an h8/300 or h8/300h program.
2094 This is the first point at which we can make that determination,
2095 so we just reallocate memory now; this will also allow us to handle
2096 switching between h8/300 and h8/300h programs without exiting
2099 memory_size
= H8300H_MSIZE
;
2101 memory_size
= H8300_MSIZE
;
2106 free (cpu
.cache_idx
);
2108 free (cpu
.eightbit
);
2110 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
2111 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
2112 cpu
.eightbit
= (unsigned char *) calloc (sizeof (char), 256);
2114 /* `msize' must be a power of two */
2115 if ((memory_size
& (memory_size
- 1)) != 0)
2117 cpu
.mask
= memory_size
- 1;
2119 if (sim_load_file (sd
, myname
, sim_callback
, prog
, prog_bfd
,
2120 sim_kind
== SIM_OPEN_DEBUG
,
2124 /* Close the bfd if we opened it. */
2125 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2126 bfd_close (prog_bfd
);
2130 /* Close the bfd if we opened it. */
2131 if (abfd
== NULL
&& prog_bfd
!= NULL
)
2132 bfd_close (prog_bfd
);
2137 sim_create_inferior (sd
, abfd
, argv
, env
)
2144 cpu
.pc
= bfd_get_start_address (abfd
);
2151 sim_do_command (sd
, cmd
)
2155 (*sim_callback
->printf_filtered
) (sim_callback
,
2156 "This simulator does not accept any commands.\n");
2160 sim_set_callbacks (ptr
)
2161 struct host_callback_struct
*ptr
;