]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/h8300/compile.c
2 * Simulator for the Hitachi H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
29 #include <sys/param.h>
33 #include "remote-sim.h"
39 #define X(op, size) op*4+size
41 #define SP (h8300hmode ? SL:SW)
54 #define h8_opcodes ops
56 #include "opcode/h8300.h"
60 #define LOW_BYTE(x) ((x) & 0xff)
61 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
62 #define P(X,Y) ((X<<8) | Y)
64 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
67 c = (cpu.ccr >> 0) & 1;\
68 v = (cpu.ccr >> 1) & 1;\
69 nz = !((cpu.ccr >> 2) & 1);\
70 n = (cpu.ccr >> 3) & 1;
72 #ifdef __CHAR_IS_SIGNED__
73 #define SEXTCHAR(x) ((char)(x))
77 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x)
80 #define UEXTCHAR(x) ((x) & 0xff)
81 #define UEXTSHORT(x) ((x) & 0xffff)
82 #define SEXTSHORT(x) ((short)(x))
84 static cpu_state_type cpu
;
88 static int memory_size
;
119 return h8300hmode
? SL
: SW
;
132 return X (OP_IMM
, SP
);
134 return X (OP_REG
, SP
);
138 return X (OP_MEM
, SP
);
145 decode (addr
, data
, dst
)
158 struct h8_opcode
*q
= h8_opcodes
;
162 /* Find the exact opcode/arg combo */
166 unsigned int len
= 0;
172 op_type looking_for
= *nib
;
173 int thisnib
= data
[len
>> 1];
175 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
177 if (looking_for
< 16 && looking_for
>= 0)
179 if (looking_for
!= thisnib
)
184 if ((int) looking_for
& (int) B31
)
186 if (!(((int) thisnib
& 0x8) != 0))
188 looking_for
= (op_type
) ((int) looking_for
& ~(int)
192 if ((int) looking_for
& (int) B30
)
194 if (!(((int) thisnib
& 0x8) == 0))
196 looking_for
= (op_type
) ((int) looking_for
& ~(int) B30
);
198 if (looking_for
& DBIT
)
200 if ((looking_for
& 5) != (thisnib
& 5))
202 abs
= (thisnib
& 0x8) ? 2 : 1;
204 else if (looking_for
& (REG
| IND
| INC
| DEC
))
206 if (looking_for
& REG
)
209 * Can work out size from the
212 size
= bitfrom (looking_for
);
214 if (looking_for
& SRC
)
223 else if (looking_for
& L_16
)
225 abs
= (data
[len
>> 1]) * 256 + data
[(len
+ 2) >> 1];
227 if (looking_for
& (PCREL
| DISP
))
232 else if (looking_for
& ABSJMP
)
239 else if (looking_for
& MEMIND
)
243 else if (looking_for
& L_32
)
246 abs
= (data
[i
] << 24)
247 | (data
[i
+ 1] << 16)
253 else if (looking_for
& L_24
)
256 abs
= (data
[i
] << 16) | (data
[i
+ 1] << 8) | (data
[i
+ 2]);
259 else if (looking_for
& IGNORE
)
263 else if (looking_for
& DISPREG
)
265 rdisp
= thisnib
& 0x7;
267 else if (looking_for
& KBIT
)
282 else if (looking_for
& L_8
)
286 if (looking_for
& PCREL
)
288 abs
= SEXTCHAR (data
[len
>> 1]);
290 else if (looking_for
& ABS8MEM
)
293 abs
= h8300hmode
? ~0xff0000ff : ~0xffff00ff;
294 abs
|= data
[len
>> 1] & 0xff ;
298 abs
= data
[len
>> 1] & 0xff;
301 else if (looking_for
& L_3
)
307 else if (looking_for
== E
)
311 /* Fill in the args */
313 op_type
*args
= q
->args
.nib
;
319 int rn
= (x
& DST
) ? rd
: rs
;
333 p
->type
= X (OP_IMM
, size
);
336 else if (x
& (IMM
| KBIT
| DBIT
))
338 p
->type
= X (OP_IMM
, size
);
343 /* Reset the size, some
344 ops (like mul) have two sizes */
347 p
->type
= X (OP_REG
, size
);
352 p
->type
= X (OP_INC
, size
);
357 p
->type
= X (OP_DEC
, size
);
362 p
->type
= X (OP_DISP
, size
);
366 else if (x
& (ABS
| ABSJMP
| ABS8MEM
))
368 p
->type
= X (OP_DISP
, size
);
374 p
->type
= X (OP_MEM
, size
);
379 p
->type
= X (OP_PCREL
, size
);
380 p
->literal
= abs
+ addr
+ 2;
386 p
->type
= X (OP_IMM
, SP
);
391 p
->type
= X (OP_DISP
, size
);
393 p
->reg
= rdisp
& 0x7;
400 printf ("Hmmmm %x", x
);
407 * But a jmp or a jsr gets
408 * automagically lvalued, since we
409 * branch to their address not their
412 if (q
->how
== O (O_JSR
, SB
)
413 || q
->how
== O (O_JMP
, SB
))
415 dst
->src
.type
= lvalue (dst
->src
.type
, dst
->src
.reg
);
418 if (dst
->dst
.type
== -1)
421 dst
->opcode
= q
->how
;
422 dst
->cycles
= q
->time
;
424 /* And a jsr to 0xc4 is turned into a magic trap */
426 if (dst
->opcode
== O (O_JSR
, SB
))
428 if (dst
->src
.literal
== 0xc4)
430 dst
->opcode
= O (O_SYSCALL
, SB
);
434 dst
->next_pc
= addr
+ len
/ 2;
439 printf ("Dont understand %x \n", looking_for
);
451 dst
->opcode
= O (O_ILL
, SB
);
460 /* find the next cache entry to use */
462 idx
= cpu
.cache_top
+ 1;
464 if (idx
>= cpu
.csize
)
470 /* Throw away its old meaning */
471 cpu
.cache_idx
[cpu
.cache
[idx
].oldpc
] = 0;
473 /* set to new address */
474 cpu
.cache
[idx
].oldpc
= pc
;
476 /* fill in instruction info */
477 decode (pc
, cpu
.memory
+ pc
, cpu
.cache
+ idx
);
479 /* point to new cache entry */
480 cpu
.cache_idx
[pc
] = idx
;
484 static unsigned char *breg
[18];
485 static unsigned short *wreg
[18];
486 static unsigned int *lreg
[18];
488 #define GET_B_REG(x) *(breg[x])
489 #define SET_B_REG(x,y) (*(breg[x])) = (y)
490 #define GET_W_REG(x) *(wreg[x])
491 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
493 #define GET_L_REG(x) *(lreg[x])
494 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
496 #define GET_MEMORY_L(x) \
497 ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3])
499 #define GET_MEMORY_W(x) \
500 ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0))
503 #define SET_MEMORY_B(x,y) \
504 (cpu.memory[(x)] = y)
506 #define SET_MEMORY_W(x,y) \
507 {register unsigned char *_p = cpu.memory+x;\
508 register int __y = y;\
512 #define SET_MEMORY_L(x,y) \
513 {register unsigned char *_p = cpu.memory+x;register int __y = y;\
514 _p[0] = (__y)>>24; _p[1] = (__y)>>16; _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
516 #define GET_MEMORY_B(x) (cpu.memory[x])
523 int abs
= arg
->literal
;
530 return GET_B_REG (rn
);
532 return GET_W_REG (rn
);
534 return GET_L_REG (rn
);
545 r
= GET_MEMORY_B (t
);
554 r
= GET_MEMORY_W (t
);
562 r
= GET_MEMORY_L (t
);
569 case X (OP_DISP
, SB
):
570 t
= GET_L_REG (rn
) + abs
;
572 return GET_MEMORY_B (t
);
574 case X (OP_DISP
, SW
):
575 t
= GET_L_REG (rn
) + abs
;
577 return GET_MEMORY_W (t
);
579 case X (OP_DISP
, SL
):
580 t
= GET_L_REG (rn
) + abs
;
582 return GET_MEMORY_L (t
);
585 t
= GET_MEMORY_L (abs
);
590 t
= GET_MEMORY_W (abs
);
608 int abs
= arg
->literal
;
624 t
= GET_L_REG (rn
) - 1;
631 t
= (GET_L_REG (rn
) - 2) & cpu
.mask
;
637 t
= (GET_L_REG (rn
) - 4) & cpu
.mask
;
642 case X (OP_DISP
, SB
):
643 t
= GET_L_REG (rn
) + abs
;
648 case X (OP_DISP
, SW
):
649 t
= GET_L_REG (rn
) + abs
;
654 case X (OP_DISP
, SL
):
655 t
= GET_L_REG (rn
) + abs
;
692 memory_size
= H8300H_MSIZE
;
694 memory_size
= H8300_MSIZE
;
695 cpu
.memory
= (unsigned char *) calloc (sizeof (char), memory_size
);
696 cpu
.cache_idx
= (unsigned short *) calloc (sizeof (short), memory_size
);
698 /* `msize' must be a power of two */
699 if ((memory_size
& (memory_size
- 1)) != 0)
701 cpu
.mask
= memory_size
- 1;
703 for (i
= 0; i
< 9; i
++)
708 for (i
= 0; i
< 8; i
++)
710 unsigned char *p
= (unsigned char *) (cpu
.regs
+ i
);
711 unsigned char *e
= (unsigned char *) (cpu
.regs
+ i
+ 1);
712 unsigned short *q
= (unsigned short *) (cpu
.regs
+ i
);
713 unsigned short *u
= (unsigned short *) (cpu
.regs
+ i
+ 1);
714 cpu
.regs
[i
] = 0x00112233;
740 lreg
[i
] = &cpu
.regs
[i
];
743 lreg
[8] = &cpu
.regs
[8];
745 /* initialize the seg registers */
752 control_c (sig
, code
, scp
, addr
)
758 cpu
.exception
= SIGINT
;
767 mop (code
, bsize
, sign
)
780 bsize
? SEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
781 SEXTSHORT (GET_W_REG (code
->dst
.reg
));
783 bsize
? SEXTCHAR (GET_B_REG (code
->src
.reg
)) :
784 SEXTSHORT (GET_W_REG (code
->src
.reg
));
788 multiplicand
= bsize
? UEXTCHAR (GET_W_REG (code
->dst
.reg
)) :
789 UEXTSHORT (GET_W_REG (code
->dst
.reg
));
791 bsize
? UEXTCHAR (GET_B_REG (code
->src
.reg
)) :
792 UEXTSHORT (GET_W_REG (code
->src
.reg
));
795 result
= multiplier
* multiplicand
;
799 n
= result
& (bsize
? 0x8000 : 0x80000000);
800 nz
= result
& (bsize
? 0xffff : 0xffffffff);
804 SET_W_REG (code
->dst
.reg
, result
);
808 SET_L_REG (code
->dst
.reg
, result
);
810 /* return ((n==1) << 1) | (nz==1); */
814 #define OSHIFTS(name, how) \
819 rd = GET_B_REG (code->src.reg); \
827 rd = GET_W_REG (code->src.reg); \
834 int hm = 0x80000000; \
835 rd = GET_L_REG (code->src.reg); \
840 #define OBITOP(name,f, s, op) \
845 if (f) ea = fetch (&code->dst); \
846 m=1<< fetch(&code->src); \
848 if(s) store (&code->dst,ea); goto next; \
852 sim_resume (step
, siggnal
)
857 int tick_start
= get_now ();
870 prev
= signal (SIGINT
, control_c
);
874 cpu
.exception
= SIGTRAP
;
893 cidx
= cpu
.cache_idx
[pc
];
894 code
= cpu
.cache
+ cidx
;
897 #define ALUOP(STORE, NAME, HOW) \
898 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
899 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
900 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
903 #define LOGOP(NAME, HOW) \
904 case O(NAME,SB): HOW; goto log8;\
905 case O(NAME, SW): HOW; goto log16;\
906 case O(NAME,SL): HOW; goto log32;
913 printf ("%x %d %s\n", pc
, code
->opcode
,
914 code
->op
? code
->op
->name
: "**");
916 cpu
.stats
[code
->opcode
]++;
920 cycles
+= code
->cycles
;
922 switch (code
->opcode
)
926 * This opcode is a fake for when we get to an
927 * instruction which hasnt been compiled
935 rd
= fetch (&code
->dst
);
936 ea
= fetch (&code
->src
);
942 rd
= fetch (&code
->dst
);
943 ea
= fetch (&code
->src
);
948 #define EA ea = fetch(&code->src);
949 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
951 ALUOP (1, O_SUB
, RD_EA
;
960 rd
= GET_B_REG (code
->dst
.reg
);
961 ea
= fetch (&code
->src
);
965 rd
= GET_W_REG (code
->dst
.reg
);
966 ea
= fetch (&code
->src
);
970 rd
= GET_L_REG (code
->dst
.reg
);
971 ea
= fetch (&code
->src
);
986 case O (O_MOV_TO_MEM
, SB
):
987 res
= GET_B_REG (code
->src
.reg
);
989 case O (O_MOV_TO_MEM
, SW
):
990 res
= GET_W_REG (code
->src
.reg
);
992 case O (O_MOV_TO_MEM
, SL
):
993 res
= GET_L_REG (code
->src
.reg
);
997 case O (O_MOV_TO_REG
, SB
):
998 res
= fetch (&code
->src
);
999 SET_B_REG (code
->dst
.reg
, res
);
1000 goto just_flags_log8
;
1001 case O (O_MOV_TO_REG
, SW
):
1002 res
= fetch (&code
->src
);
1003 SET_W_REG (code
->dst
.reg
, res
);
1004 goto just_flags_log16
;
1005 case O (O_MOV_TO_REG
, SL
):
1006 res
= fetch (&code
->src
);
1007 SET_L_REG (code
->dst
.reg
, res
);
1008 goto just_flags_log32
;
1011 case O (O_ADDS
, SL
):
1012 SET_L_REG (code
->dst
.reg
,
1013 GET_L_REG (code
->dst
.reg
)
1014 + code
->src
.literal
);
1018 case O (O_SUBS
, SL
):
1019 SET_L_REG (code
->dst
.reg
,
1020 GET_L_REG (code
->dst
.reg
)
1021 - code
->src
.literal
);
1025 rd
= fetch (&code
->dst
);
1026 ea
= fetch (&code
->src
);
1029 goto just_flags_alu8
;
1032 rd
= fetch (&code
->dst
);
1033 ea
= fetch (&code
->src
);
1036 goto just_flags_alu16
;
1039 rd
= fetch (&code
->dst
);
1040 ea
= fetch (&code
->src
);
1043 goto just_flags_alu32
;
1047 rd
= GET_B_REG (code
->src
.reg
);
1050 SET_B_REG (code
->src
.reg
, res
);
1051 goto just_flags_inc8
;
1054 rd
= GET_W_REG (code
->dst
.reg
);
1055 ea
= -code
->src
.literal
;
1057 SET_W_REG (code
->dst
.reg
, res
);
1058 goto just_flags_inc16
;
1061 rd
= GET_L_REG (code
->dst
.reg
);
1062 ea
= -code
->src
.literal
;
1064 SET_L_REG (code
->dst
.reg
, res
);
1065 goto just_flags_inc32
;
1069 rd
= GET_B_REG (code
->src
.reg
);
1072 SET_B_REG (code
->src
.reg
, res
);
1073 goto just_flags_inc8
;
1076 rd
= GET_W_REG (code
->dst
.reg
);
1077 ea
= code
->src
.literal
;
1079 SET_W_REG (code
->dst
.reg
, res
);
1080 goto just_flags_inc16
;
1083 rd
= GET_L_REG (code
->dst
.reg
);
1084 ea
= code
->src
.literal
;
1086 SET_L_REG (code
->dst
.reg
, res
);
1087 goto just_flags_inc32
;
1090 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1092 case O (O_ANDC
, SB
):
1094 ea
= code
->src
.literal
;
1100 ea
= code
->src
.literal
;
1104 case O (O_XORC
, SB
):
1106 ea
= code
->src
.literal
;
1147 if (((Z
|| (N
^ V
)) == 0))
1153 if (((Z
|| (N
^ V
)) == 1))
1187 case O (O_SYSCALL
, SB
):
1188 printf ("%c", cpu
.regs
[2]);
1191 OSHIFTS (O_NOT
, rd
= ~rd
; v
= 0;);
1192 OSHIFTS (O_SHLL
, c
= rd
& hm
; v
= 0;
1194 OSHIFTS (O_SHLR
, c
= rd
& 1; v
= 0;
1195 rd
= (unsigned int) rd
>> 1);
1196 OSHIFTS (O_SHAL
, c
= rd
& hm
;
1197 v
= (rd
& hm
) != ((rd
& (hm
>> 1)) << 1);
1199 OSHIFTS (O_SHAR
, t
= rd
& hm
;
1205 OSHIFTS (O_ROTL
, c
= rd
& hm
;
1209 OSHIFTS (O_ROTR
, c
= rd
& 1;
1211 rd
= (unsigned int) rd
>> 1;
1213 OSHIFTS (O_ROTXL
, t
= rd
& hm
;
1219 OSHIFTS (O_ROTXR
, t
= rd
& 1;
1220 rd
= (unsigned int) rd
>> 1;
1221 if (C
) rd
|= hm
; c
= t
;
1226 pc
= fetch (&code
->src
);
1234 pc
= fetch (&code
->src
);
1241 SET_MEMORY_L (tmp
, code
->next_pc
);
1246 SET_MEMORY_W (tmp
, code
->next_pc
);
1253 pc
= code
->src
.literal
;
1264 pc
= GET_MEMORY_L (tmp
);
1269 pc
= GET_MEMORY_W (tmp
);
1278 cpu
.exception
= SIGILL
;
1280 case O (O_SLEEP
, SB
):
1281 /* The format of r0 is defined by devo/include/wait.h.
1282 cpu.exception handling needs some cleanup: we need to make the
1283 the handling of normal exits vs signals, etc. more sensible. */
1284 if (! WIFEXITED (cpu
.regs
[0]) && WIFSIGNALED (cpu
.regs
[0]))
1285 cpu
.exception
= SIGILL
;
1287 cpu
.exception
= SIGTRAP
;
1290 cpu
.exception
= SIGTRAP
;
1293 OBITOP (O_BNOT
, 1, 1, ea
^= m
);
1294 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
);
1295 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
);
1296 OBITOP (O_BSET
, 1, 1, ea
|= m
);
1297 OBITOP (O_BLD
, 1, 0, c
= ea
& m
);
1298 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
));
1299 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
1301 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
1303 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
);
1304 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
);
1305 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
);
1306 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
);
1307 OBITOP (O_BXOR
, 1, 0, c
= (ea
& m
) != C
);
1308 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
);
1311 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1313 case O (O_MULS
, SB
):
1316 case O (O_MULS
, SW
):
1319 case O (O_MULU
, SB
):
1322 case O (O_MULU
, SW
):
1327 case O (O_DIVU
, SB
):
1329 rd
= GET_W_REG (code
->dst
.reg
);
1330 ea
= GET_B_REG (code
->src
.reg
);
1336 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1342 case O (O_DIVU
, SW
):
1344 rd
= GET_L_REG (code
->dst
.reg
);
1345 ea
= GET_W_REG (code
->src
.reg
);
1353 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1357 case O (O_DIVS
, SB
):
1360 rd
= SEXTSHORT (GET_W_REG (code
->dst
.reg
));
1361 ea
= SEXTCHAR (GET_B_REG (code
->src
.reg
));
1364 tmp
= (int) rd
% (int) ea
;
1365 rd
= (int) rd
/ (int) ea
;
1371 SET_W_REG (code
->dst
.reg
, (rd
& 0xff) | (tmp
<< 8));
1374 case O (O_DIVS
, SW
):
1376 rd
= GET_L_REG (code
->dst
.reg
);
1377 ea
= SEXTSHORT (GET_W_REG (code
->src
.reg
));
1380 tmp
= (int) rd
% (int) ea
;
1381 rd
= (int) rd
/ (int) ea
;
1382 n
= rd
& 0x80000000;
1387 SET_L_REG (code
->dst
.reg
, (rd
& 0xffff) | (tmp
<< 16));
1390 case O (O_EXTS
, SW
):
1391 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff; /* Yes, src, not dst. */
1392 ea
= rd
& 0x80 ? -256 : 0;
1395 case O (O_EXTS
, SL
):
1396 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1397 ea
= rd
& 0x8000 ? -65536 : 0;
1400 case O (O_EXTU
, SW
):
1401 rd
= GET_B_REG (code
->src
.reg
+ 8) & 0xff;
1405 case O (O_EXTU
, SL
):
1406 rd
= GET_W_REG (code
->src
.reg
) & 0xffff;
1415 cpu
.exception
= SIGILL
;
1427 /* When a branch works */
1428 pc
= code
->src
.literal
;
1431 /* Set the cond codes from res */
1434 /* Set the flags after an 8 bit inc/dec operation */
1438 v
= (rd
& 0x7f) == 0x7f;
1442 /* Set the flags after an 16 bit inc/dec operation */
1446 v
= (rd
& 0x7fff) == 0x7fff;
1450 /* Set the flags after an 32 bit inc/dec operation */
1452 n
= res
& 0x80000000;
1453 nz
= res
& 0xffffffff;
1454 v
= (rd
& 0x7fffffff) == 0x7fffffff;
1459 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1462 SET_B_REG (code
->src
.reg
, rd
);
1466 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1469 SET_W_REG (code
->src
.reg
, rd
);
1473 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1474 n
= (rd
& 0x80000000);
1475 nz
= rd
& 0xffffffff;
1476 SET_L_REG (code
->src
.reg
, rd
);
1480 store (&code
->dst
, res
);
1482 /* flags after a 32bit logical operation */
1483 n
= res
& 0x80000000;
1484 nz
= res
& 0xffffffff;
1489 store (&code
->dst
, res
);
1491 /* flags after a 16bit logical operation */
1499 store (&code
->dst
, res
);
1507 SET_B_REG (code
->dst
.reg
, res
);
1511 v
= ((ea
& 0x80) == (rd
& 0x80)) && ((ea
& 0x80) != (res
& 0x80));
1516 SET_W_REG (code
->dst
.reg
, res
);
1520 v
= ((ea
& 0x8000) == (rd
& 0x8000)) && ((ea
& 0x8000) != (res
& 0x8000));
1521 c
= (res
& 0x10000);
1525 SET_L_REG (code
->dst
.reg
, res
);
1527 n
= res
& 0x80000000;
1528 nz
= res
& 0xffffffff;
1529 v
= ((ea
& 0x80000000) == (rd
& 0x80000000))
1530 && ((ea
& 0x80000000) != (res
& 0x80000000));
1531 switch (code
->opcode
/ 4)
1534 c
= ((unsigned) res
< (unsigned) rd
) || ((unsigned) res
< (unsigned) ea
);
1538 c
= (unsigned) rd
< (unsigned) -ea
;
1551 /* if (cpu.regs[8] ) abort(); */
1554 /* Poll after every 100th insn, */
1555 if (poll_count
++ > 100)
1558 if (win32pollquit())
1564 #if defined(__GO32__)
1565 /* Poll after every 100th insn, */
1566 if (poll_count
++ > 100)
1578 while (!cpu
.exception
);
1579 cpu
.ticks
+= get_now () - tick_start
;
1580 cpu
.cycles
+= cycles
;
1586 signal (SIGINT
, prev
);
1591 sim_write (addr
, buffer
, size
)
1593 unsigned char *buffer
;
1599 if (addr
< 0 || addr
+ size
> memory_size
)
1601 for (i
= 0; i
< size
; i
++)
1603 cpu
.memory
[addr
+ i
] = buffer
[i
];
1604 cpu
.cache_idx
[addr
+ i
] = 0;
1610 sim_read (addr
, buffer
, size
)
1612 unsigned char *buffer
;
1616 if (addr
< 0 || addr
+ size
> memory_size
)
1618 memcpy (buffer
, cpu
.memory
+ addr
, size
);
1632 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1633 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1636 #define CCR_REGNUM 8 /* Contains processor status */
1637 #define PC_REGNUM 9 /* Contains program counter */
1639 #define CYCLE_REGNUM 10
1640 #define INST_REGNUM 11
1641 #define TICK_REGNUM 12
1645 sim_store_register (rn
, value
)
1647 unsigned char *value
;
1652 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
1653 shortval
= (value
[0] << 8) | (value
[1]);
1654 intval
= h8300hmode
? longval
: shortval
;
1672 cpu
.regs
[rn
] = intval
;
1678 cpu
.cycles
= longval
;
1682 cpu
.insts
= longval
;
1686 cpu
.ticks
= longval
;
1692 sim_fetch_register (rn
, buf
)
1734 if (h8300hmode
|| longreg
)
1749 sim_stop_reason (reason
, sigrc
)
1750 enum sim_stop
*reason
;
1753 *reason
= sim_stopped
;
1754 *sigrc
= cpu
.exception
;
1763 cpu
.cache
= (decoded_inst
*) malloc (sizeof (decoded_inst
) * n
);
1764 memset (cpu
.cache
, 0, sizeof (decoded_inst
) * n
);
1773 double timetaken
= (double) cpu
.ticks
/ (double) now_persec ();
1774 double virttime
= cpu
.cycles
/ 10.0e6
;
1776 printf_filtered ("\n\n#instructions executed %10d\n", cpu
.insts
);
1777 printf_filtered ("#cycles (v approximate) %10d\n", cpu
.cycles
);
1778 printf_filtered ("#real time taken %10.4f\n", timetaken
);
1779 printf_filtered ("#virtual time taked %10.4f\n", virttime
);
1780 if (timetaken
!= 0.0)
1781 printf_filtered ("#simulation ratio %10.4f\n", virttime
/ timetaken
);
1782 printf_filtered ("#compiles %10d\n", cpu
.compiles
);
1783 printf_filtered ("#cache size %10d\n", cpu
.csize
);
1789 for (i
= 0; i
< O_LAST
; i
++)
1792 printf_filtered ("%d: %d\n", i
, cpu
.stats
[i
]);
1798 /* Indicate whether the cpu is an h8/300 or h8/300h.
1799 FLAG is non-zero for the h8/300h. */
1822 sim_close (quitting
)
1828 /* Called by gdb to load a program into memory. */
1831 sim_load (prog
, from_tty
)
1837 /* See if the file is for the h8/300 or h8/300h. */
1838 /* ??? This may not be the most efficient way. The z8k simulator
1839 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
1840 if ((abfd
= bfd_openr (prog
, "coff-h8300")) != 0)
1842 if (bfd_check_format (abfd
, bfd_object
))
1843 set_h8300h (abfd
->arch_info
->mach
== bfd_mach_h8300h
);
1847 /* Return non-zero so gdb will handle it. */
1852 sim_create_inferior (start_address
, argv
, env
)
1853 SIM_ADDR start_address
;
1857 cpu
.pc
= start_address
;
1861 sim_do_command (cmd
)
1864 printf_filtered ("This simulator does not accept any commands.\n");
1870 sim_set_callbacks (ptr
)
1871 struct host_callback_struct
*ptr
;