1 /* Lattice Mico32 CPU model.
2 Contributed by Jon Beniston <jon@beniston.com>
4 Copyright (C) 2009-2021 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* This must come before any other includes. */
30 struct hw_event
*event
;
33 /* input port ID's. */
71 static const struct hw_port_descriptor lm32cpu_ports
[] = {
72 /* interrupt inputs. */
73 {"int0", INT0_PORT
, 0, input_port
,},
74 {"int1", INT1_PORT
, 0, input_port
,},
75 {"int2", INT2_PORT
, 0, input_port
,},
76 {"int3", INT3_PORT
, 0, input_port
,},
77 {"int4", INT4_PORT
, 0, input_port
,},
78 {"int5", INT5_PORT
, 0, input_port
,},
79 {"int6", INT6_PORT
, 0, input_port
,},
80 {"int7", INT7_PORT
, 0, input_port
,},
81 {"int8", INT8_PORT
, 0, input_port
,},
82 {"int9", INT9_PORT
, 0, input_port
,},
83 {"int10", INT10_PORT
, 0, input_port
,},
84 {"int11", INT11_PORT
, 0, input_port
,},
85 {"int12", INT12_PORT
, 0, input_port
,},
86 {"int13", INT13_PORT
, 0, input_port
,},
87 {"int14", INT14_PORT
, 0, input_port
,},
88 {"int15", INT15_PORT
, 0, input_port
,},
89 {"int16", INT16_PORT
, 0, input_port
,},
90 {"int17", INT17_PORT
, 0, input_port
,},
91 {"int18", INT18_PORT
, 0, input_port
,},
92 {"int19", INT19_PORT
, 0, input_port
,},
93 {"int20", INT20_PORT
, 0, input_port
,},
94 {"int21", INT21_PORT
, 0, input_port
,},
95 {"int22", INT22_PORT
, 0, input_port
,},
96 {"int23", INT23_PORT
, 0, input_port
,},
97 {"int24", INT24_PORT
, 0, input_port
,},
98 {"int25", INT25_PORT
, 0, input_port
,},
99 {"int26", INT26_PORT
, 0, input_port
,},
100 {"int27", INT27_PORT
, 0, input_port
,},
101 {"int28", INT28_PORT
, 0, input_port
,},
102 {"int29", INT29_PORT
, 0, input_port
,},
103 {"int30", INT30_PORT
, 0, input_port
,},
104 {"int31", INT31_PORT
, 0, input_port
,},
111 * Finish off the partially created hw device. Attach our local
112 * callbacks. Wire up our port names etc.
114 static hw_port_event_method lm32cpu_port_event
;
118 lm32cpu_finish (struct hw
*me
)
120 struct lm32cpu
*controller
;
122 controller
= HW_ZALLOC (me
, struct lm32cpu
);
123 set_hw_data (me
, controller
);
124 set_hw_ports (me
, lm32cpu_ports
);
125 set_hw_port_event (me
, lm32cpu_port_event
);
127 /* Initialize the pending interrupt flags. */
128 controller
->event
= NULL
;
132 /* An event arrives on an interrupt port. */
133 static unsigned int s_ui_ExtIntrs
= 0;
137 deliver_lm32cpu_interrupt (struct hw
*me
, void *data
)
139 static unsigned int ip
, im
, im_and_ip_result
;
140 struct lm32cpu
*controller
= hw_data (me
);
141 SIM_DESC sd
= hw_system (me
);
142 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* NB: fix CPU 0. */
143 address_word cia
= CPU_PC_GET (cpu
);
144 int interrupt
= (int) data
;
147 HW_TRACE ((me
, "interrupt-check event"));
151 * Determine if an external interrupt is active
152 * and needs to cause an exception.
154 im
= lm32bf_h_csr_get (cpu
, LM32_CSR_IM
);
155 ip
= lm32bf_h_csr_get (cpu
, LM32_CSR_IP
);
156 im_and_ip_result
= im
& ip
;
159 if ((lm32bf_h_csr_get (cpu
, LM32_CSR_IE
) & 1) && (im_and_ip_result
!= 0))
161 /* Save PC in exception address register. */
162 lm32bf_h_gr_set (cpu
, 30, lm32bf_h_pc_get (cpu
));
163 /* Restart at interrupt offset in handler exception table. */
164 lm32bf_h_pc_set (cpu
,
165 lm32bf_h_csr_get (cpu
,
167 LM32_EID_INTERRUPT
* 32);
168 /* Save interrupt enable and then clear. */
169 lm32bf_h_csr_set (cpu
, LM32_CSR_IE
, 0x2);
172 /* reschedule soon. */
173 if (controller
->event
!= NULL
)
174 hw_event_queue_deschedule (me
, controller
->event
);
175 controller
->event
= NULL
;
178 /* if there are external interrupts, schedule an interrupt-check again.
179 * NOTE: THIS MAKES IT VERY INEFFICIENT. INSTEAD, TRIGGER THIS
180 * CHECk_EVENT WHEN THE USER ENABLES IE OR USER MODIFIES IM REGISTERS.
182 if (s_ui_ExtIntrs
!= 0)
184 hw_event_queue_schedule (me
, 1, deliver_lm32cpu_interrupt
, data
);
189 /* Handle an event on one of the CPU's ports. */
191 lm32cpu_port_event (struct hw
*me
,
193 struct hw
*source
, int source_port
, int level
)
195 struct lm32cpu
*controller
= hw_data (me
);
196 SIM_DESC sd
= hw_system (me
);
197 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* NB: fix CPU 0. */
198 address_word cia
= CPU_PC_GET (cpu
);
201 HW_TRACE ((me
, "interrupt event on port %d, level %d", my_port
, level
));
206 * Activate IP if the interrupt's activated; don't do anything if
207 * the interrupt's deactivated.
212 * save state of external interrupt.
214 s_ui_ExtIntrs
|= (1 << my_port
);
216 /* interrupt-activated so set IP. */
217 lm32bf_h_csr_set (cpu
, LM32_CSR_IP
,
218 lm32bf_h_csr_get (cpu
, LM32_CSR_IP
) | (1 << my_port
));
221 * Since interrupt is activated, queue an immediate event
222 * to check if this interrupt is serviceable.
224 if (controller
->event
!= NULL
)
225 hw_event_queue_deschedule (me
, controller
->event
);
229 * Queue an immediate event to check if this interrupt must be serviced;
230 * this will happen after the current instruction is complete.
232 controller
->event
= hw_event_queue_schedule (me
,
234 deliver_lm32cpu_interrupt
,
240 * save state of external interrupt.
242 s_ui_ExtIntrs
&= ~(1 << my_port
);
247 const struct hw_descriptor dv_lm32cpu_descriptor
[] = {
248 {"lm32cpu", lm32cpu_finish
,},