sim/m32r/cpu.h

   1 /* CPU family header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RBF_H
  26 #define CPU_M32RBF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 #define GET_H_CR(a1) CPU (h_cr)[a1]
  50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
  51   /* accumulator */
  52   DI h_accum;
  53 #define GET_H_ACCUM() CPU (h_accum)
  54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
  60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
  61   /* condition bit */
  62   BI h_cond;
  63 #define GET_H_COND() CPU (h_cond)
  64 #define SET_H_COND(x) (CPU (h_cond) = (x))
  65   /* psw part of psw */
  66   UQI h_psw;
  67 #define GET_H_PSW() CPU (h_psw)
  68 #define SET_H_PSW(x) (CPU (h_psw) = (x))
  69   /* backup psw */
  70   UQI h_bpsw;
  71 #define GET_H_BPSW() CPU (h_bpsw)
  72 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  73   /* backup bpsw */
  74   UQI h_bbpsw;
  75 #define GET_H_BBPSW() CPU (h_bbpsw)
  76 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  77   /* lock */
  78   BI h_lock;
  79 #define GET_H_LOCK() CPU (h_lock)
  80 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  81   } hardware;
  82 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  83 } M32RBF_CPU_DATA;
  84
  85 /* Cover fns for register access.  */
  86 USI m32rbf_h_pc_get (SIM_CPU *);
  87 void m32rbf_h_pc_set (SIM_CPU *, USI);
  88 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
  89 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  90 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
  91 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  92 DI m32rbf_h_accum_get (SIM_CPU *);
  93 void m32rbf_h_accum_set (SIM_CPU *, DI);
  94 DI m32rbf_h_accums_get (SIM_CPU *, UINT);
  95 void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
  96 BI m32rbf_h_cond_get (SIM_CPU *);
  97 void m32rbf_h_cond_set (SIM_CPU *, BI);
  98 UQI m32rbf_h_psw_get (SIM_CPU *);
  99 void m32rbf_h_psw_set (SIM_CPU *, UQI);
 100 UQI m32rbf_h_bpsw_get (SIM_CPU *);
 101 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
 102 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
 103 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
 104 BI m32rbf_h_lock_get (SIM_CPU *);
 105 void m32rbf_h_lock_set (SIM_CPU *, BI);
 106
 107 /* These must be hand-written.  */
 108 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 109 extern CPUREG_STORE_FN m32rbf_store_register;
 110
 111 typedef struct {
 112   UINT h_gr;
 113 } MODEL_M32R_D_DATA;
 114
 115 typedef struct {
 116   int empty;
 117 } MODEL_TEST_DATA;
 118
 119 /* The ARGBUF struct.  */
 120 struct argbuf {
 121   /* These are the baseclass definitions.  */
 122   PCADDR addr;
 123   const IDESC *idesc;
 124   char trace_p;
 125   char profile_p;
 126   /* cpu specific data follows */
 127   union sem semantic;
 128   int written;
 129   union {
 130     struct { /* e.g. add $dr,$sr */
 131       SI * i_dr;
 132       SI * i_sr;
 133       unsigned char in_dr;
 134       unsigned char in_sr;
 135       unsigned char out_dr;
 136     } fmt_add;
 137     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 138       SI * i_sr;
 139       HI f_simm16;
 140       SI * i_dr;
 141       unsigned char in_sr;
 142       unsigned char out_dr;
 143     } fmt_add3;
 144     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 145       SI * i_sr;
 146       USI f_uimm16;
 147       SI * i_dr;
 148       unsigned char in_sr;
 149       unsigned char out_dr;
 150     } fmt_and3;
 151     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 152       SI * i_sr;
 153       UHI f_uimm16;
 154       SI * i_dr;
 155       unsigned char in_sr;
 156       unsigned char out_dr;
 157     } fmt_or3;
 158     struct { /* e.g. addi $dr,$simm8 */
 159       SI * i_dr;
 160       SI f_simm8;
 161       unsigned char in_dr;
 162       unsigned char out_dr;
 163     } fmt_addi;
 164     struct { /* e.g. addv $dr,$sr */
 165       SI * i_dr;
 166       SI * i_sr;
 167       unsigned char in_dr;
 168       unsigned char in_sr;
 169       unsigned char out_dr;
 170     } fmt_addv;
 171     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 172       SI * i_sr;
 173       SI f_simm16;
 174       SI * i_dr;
 175       unsigned char in_sr;
 176       unsigned char out_dr;
 177     } fmt_addv3;
 178     struct { /* e.g. addx $dr,$sr */
 179       SI * i_dr;
 180       SI * i_sr;
 181       unsigned char in_dr;
 182       unsigned char in_sr;
 183       unsigned char out_dr;
 184     } fmt_addx;
 185     struct { /* e.g. cmp $src1,$src2 */
 186       SI * i_src1;
 187       SI * i_src2;
 188       unsigned char in_src1;
 189       unsigned char in_src2;
 190     } fmt_cmp;
 191     struct { /* e.g. cmpi $src2,$simm16 */
 192       SI * i_src2;
 193       SI f_simm16;
 194       unsigned char in_src2;
 195     } fmt_cmpi;
 196     struct { /* e.g. div $dr,$sr */
 197       SI * i_sr;
 198       SI * i_dr;
 199       unsigned char in_sr;
 200       unsigned char in_dr;
 201       unsigned char out_dr;
 202     } fmt_div;
 203     struct { /* e.g. ld $dr,@$sr */
 204       SI * i_sr;
 205       SI * i_dr;
 206       unsigned char in_sr;
 207       unsigned char out_dr;
 208     } fmt_ld;
 209     struct { /* e.g. ld $dr,@($slo16,$sr) */
 210       SI * i_sr;
 211       HI f_simm16;
 212       SI * i_dr;
 213       unsigned char in_sr;
 214       unsigned char out_dr;
 215     } fmt_ld_d;
 216     struct { /* e.g. ldb $dr,@$sr */
 217       SI * i_sr;
 218       SI * i_dr;
 219       unsigned char in_sr;
 220       unsigned char out_dr;
 221     } fmt_ldb;
 222     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 223       SI * i_sr;
 224       HI f_simm16;
 225       SI * i_dr;
 226       unsigned char in_sr;
 227       unsigned char out_dr;
 228     } fmt_ldb_d;
 229     struct { /* e.g. ldh $dr,@$sr */
 230       SI * i_sr;
 231       SI * i_dr;
 232       unsigned char in_sr;
 233       unsigned char out_dr;
 234     } fmt_ldh;
 235     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 236       SI * i_sr;
 237       HI f_simm16;
 238       SI * i_dr;
 239       unsigned char in_sr;
 240       unsigned char out_dr;
 241     } fmt_ldh_d;
 242     struct { /* e.g. ld $dr,@$sr+ */
 243       SI * i_sr;
 244       SI * i_dr;
 245       unsigned char in_sr;
 246       unsigned char out_dr;
 247       unsigned char out_sr;
 248     } fmt_ld_plus;
 249     struct { /* e.g. ld24 $dr,$uimm24 */
 250       ADDR f_uimm24;
 251       SI * i_dr;
 252       unsigned char out_dr;
 253     } fmt_ld24;
 254     struct { /* e.g. ldi8 $dr,$simm8 */
 255       SI f_simm8;
 256       SI * i_dr;
 257       unsigned char out_dr;
 258     } fmt_ldi8;
 259     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 260       HI f_simm16;
 261       SI * i_dr;
 262       unsigned char out_dr;
 263     } fmt_ldi16;
 264     struct { /* e.g. lock $dr,@$sr */
 265       SI * i_sr;
 266       SI * i_dr;
 267       unsigned char in_sr;
 268       unsigned char out_dr;
 269     } fmt_lock;
 270     struct { /* e.g. machi $src1,$src2 */
 271       SI * i_src1;
 272       SI * i_src2;
 273       unsigned char in_src1;
 274       unsigned char in_src2;
 275     } fmt_machi;
 276     struct { /* e.g. mulhi $src1,$src2 */
 277       SI * i_src1;
 278       SI * i_src2;
 279       unsigned char in_src1;
 280       unsigned char in_src2;
 281     } fmt_mulhi;
 282     struct { /* e.g. mv $dr,$sr */
 283       SI * i_sr;
 284       SI * i_dr;
 285       unsigned char in_sr;
 286       unsigned char out_dr;
 287     } fmt_mv;
 288     struct { /* e.g. mvfachi $dr */
 289       SI * i_dr;
 290       unsigned char out_dr;
 291     } fmt_mvfachi;
 292     struct { /* e.g. mvfc $dr,$scr */
 293       UINT f_r2;
 294       SI * i_dr;
 295       unsigned char out_dr;
 296     } fmt_mvfc;
 297     struct { /* e.g. mvtachi $src1 */
 298       SI * i_src1;
 299       unsigned char in_src1;
 300     } fmt_mvtachi;
 301     struct { /* e.g. mvtc $sr,$dcr */
 302       SI * i_sr;
 303       UINT f_r1;
 304       unsigned char in_sr;
 305     } fmt_mvtc;
 306     struct { /* e.g. nop */
 307       int empty;
 308     } fmt_nop;
 309     struct { /* e.g. rac */
 310       int empty;
 311     } fmt_rac;
 312     struct { /* e.g. seth $dr,$hash$hi16 */
 313       UHI f_hi16;
 314       SI * i_dr;
 315       unsigned char out_dr;
 316     } fmt_seth;
 317     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 318       SI * i_sr;
 319       SI f_simm16;
 320       SI * i_dr;
 321       unsigned char in_sr;
 322       unsigned char out_dr;
 323     } fmt_sll3;
 324     struct { /* e.g. slli $dr,$uimm5 */
 325       SI * i_dr;
 326       USI f_uimm5;
 327       unsigned char in_dr;
 328       unsigned char out_dr;
 329     } fmt_slli;
 330     struct { /* e.g. st $src1,@$src2 */
 331       SI * i_src2;
 332       SI * i_src1;
 333       unsigned char in_src2;
 334       unsigned char in_src1;
 335     } fmt_st;
 336     struct { /* e.g. st $src1,@($slo16,$src2) */
 337       SI * i_src2;
 338       HI f_simm16;
 339       SI * i_src1;
 340       unsigned char in_src2;
 341       unsigned char in_src1;
 342     } fmt_st_d;
 343     struct { /* e.g. stb $src1,@$src2 */
 344       SI * i_src2;
 345       SI * i_src1;
 346       unsigned char in_src2;
 347       unsigned char in_src1;
 348     } fmt_stb;
 349     struct { /* e.g. stb $src1,@($slo16,$src2) */
 350       SI * i_src2;
 351       HI f_simm16;
 352       SI * i_src1;
 353       unsigned char in_src2;
 354       unsigned char in_src1;
 355     } fmt_stb_d;
 356     struct { /* e.g. sth $src1,@$src2 */
 357       SI * i_src2;
 358       SI * i_src1;
 359       unsigned char in_src2;
 360       unsigned char in_src1;
 361     } fmt_sth;
 362     struct { /* e.g. sth $src1,@($slo16,$src2) */
 363       SI * i_src2;
 364       HI f_simm16;
 365       SI * i_src1;
 366       unsigned char in_src2;
 367       unsigned char in_src1;
 368     } fmt_sth_d;
 369     struct { /* e.g. st $src1,@+$src2 */
 370       SI * i_src2;
 371       SI * i_src1;
 372       unsigned char in_src2;
 373       unsigned char in_src1;
 374       unsigned char out_src2;
 375     } fmt_st_plus;
 376     struct { /* e.g. unlock $src1,@$src2 */
 377       SI * i_src2;
 378       SI * i_src1;
 379       unsigned char in_src2;
 380       unsigned char in_src1;
 381     } fmt_unlock;
 382   /* cti insns, kept separately so addr_cache is in fixed place */
 383   struct {
 384     union {
 385     struct { /* e.g. bc.s $disp8 */
 386       IADDR f_disp8;
 387     } fmt_bc8;
 388     struct { /* e.g. bc.l $disp24 */
 389       IADDR f_disp24;
 390     } fmt_bc24;
 391     struct { /* e.g. beq $src1,$src2,$disp16 */
 392       SI * i_src1;
 393       SI * i_src2;
 394       IADDR f_disp16;
 395       unsigned char in_src1;
 396       unsigned char in_src2;
 397     } fmt_beq;
 398     struct { /* e.g. beqz $src2,$disp16 */
 399       SI * i_src2;
 400       IADDR f_disp16;
 401       unsigned char in_src2;
 402     } fmt_beqz;
 403     struct { /* e.g. bl.s $disp8 */
 404       IADDR f_disp8;
 405       unsigned char out_h_gr_14;
 406     } fmt_bl8;
 407     struct { /* e.g. bl.l $disp24 */
 408       IADDR f_disp24;
 409       unsigned char out_h_gr_14;
 410     } fmt_bl24;
 411     struct { /* e.g. bra.s $disp8 */
 412       IADDR f_disp8;
 413     } fmt_bra8;
 414     struct { /* e.g. bra.l $disp24 */
 415       IADDR f_disp24;
 416     } fmt_bra24;
 417     struct { /* e.g. jl $sr */
 418       SI * i_sr;
 419       unsigned char in_sr;
 420       unsigned char out_h_gr_14;
 421     } fmt_jl;
 422     struct { /* e.g. jmp $sr */
 423       SI * i_sr;
 424       unsigned char in_sr;
 425     } fmt_jmp;
 426     struct { /* e.g. rte */
 427       int empty;
 428     } fmt_rte;
 429     struct { /* e.g. trap $uimm4 */
 430       USI f_uimm4;
 431     } fmt_trap;
 432     } fields;
 433 #if WITH_SCACHE_PBB_M32RBF
 434     SEM_PC addr_cache;
 435 #endif
 436   } cti;
 437 #if WITH_SCACHE_PBB_M32RBF
 438     /* Writeback handler.  */
 439     struct {
 440       /* Pointer to argbuf entry for insn whose results need writing back.  */
 441       const struct argbuf *abuf;
 442     } write;
 443     /* x-before handler */
 444     struct {
 445       /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 446       int first_p;
 447     } before;
 448     /* x-after handler */
 449     struct {
 450       int empty;
 451     } after;
 452     /* This entry is used to terminate each pbb.  */
 453     struct {
 454       /* Number of insns in pbb.  */
 455       int insn_count;
 456       /* Next pbb to execute.  */
 457       SCACHE *next;
 458     } chain;
 459 #endif
 460   } fields;
 461 };
 462
 463 /* A cached insn.
 464
 465    ??? SCACHE used to contain more than just argbuf.  We could delete the
 466    type entirely and always just use ARGBUF, but for future concerns and as
 467    a level of abstraction it is left in.  */
 468
 469 struct scache {
 470   struct argbuf argbuf;
 471 };
 472
 473 /* Macros to simplify extraction, reading and semantic code.
 474    These define and assign the local vars that contain the insn's fields.  */
 475
 476 #define EXTRACT_FMT_ADD_VARS \
 477   /* Instruction fields.  */ \
 478   UINT f_op1; \
 479   UINT f_r1; \
 480   UINT f_op2; \
 481   UINT f_r2; \
 482   unsigned int length;
 483 #define EXTRACT_FMT_ADD_CODE \
 484   length = 2; \
 485   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 486   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 487   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 488   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 489
 490 #define EXTRACT_FMT_ADD3_VARS \
 491   /* Instruction fields.  */ \
 492   UINT f_op1; \
 493   UINT f_r1; \
 494   UINT f_op2; \
 495   UINT f_r2; \
 496   INT f_simm16; \
 497   unsigned int length;
 498 #define EXTRACT_FMT_ADD3_CODE \
 499   length = 4; \
 500   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 501   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 502   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 503   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 504   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 505
 506 #define EXTRACT_FMT_AND3_VARS \
 507   /* Instruction fields.  */ \
 508   UINT f_op1; \
 509   UINT f_r1; \
 510   UINT f_op2; \
 511   UINT f_r2; \
 512   UINT f_uimm16; \
 513   unsigned int length;
 514 #define EXTRACT_FMT_AND3_CODE \
 515   length = 4; \
 516   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 517   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 518   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 519   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 520   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 521
 522 #define EXTRACT_FMT_OR3_VARS \
 523   /* Instruction fields.  */ \
 524   UINT f_op1; \
 525   UINT f_r1; \
 526   UINT f_op2; \
 527   UINT f_r2; \
 528   UINT f_uimm16; \
 529   unsigned int length;
 530 #define EXTRACT_FMT_OR3_CODE \
 531   length = 4; \
 532   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 533   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 534   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 535   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 536   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 537
 538 #define EXTRACT_FMT_ADDI_VARS \
 539   /* Instruction fields.  */ \
 540   UINT f_op1; \
 541   UINT f_r1; \
 542   INT f_simm8; \
 543   unsigned int length;
 544 #define EXTRACT_FMT_ADDI_CODE \
 545   length = 2; \
 546   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 547   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 548   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 549
 550 #define EXTRACT_FMT_ADDV_VARS \
 551   /* Instruction fields.  */ \
 552   UINT f_op1; \
 553   UINT f_r1; \
 554   UINT f_op2; \
 555   UINT f_r2; \
 556   unsigned int length;
 557 #define EXTRACT_FMT_ADDV_CODE \
 558   length = 2; \
 559   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 560   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 561   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 562   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 563
 564 #define EXTRACT_FMT_ADDV3_VARS \
 565   /* Instruction fields.  */ \
 566   UINT f_op1; \
 567   UINT f_r1; \
 568   UINT f_op2; \
 569   UINT f_r2; \
 570   INT f_simm16; \
 571   unsigned int length;
 572 #define EXTRACT_FMT_ADDV3_CODE \
 573   length = 4; \
 574   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 575   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 576   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 577   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 578   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 579
 580 #define EXTRACT_FMT_ADDX_VARS \
 581   /* Instruction fields.  */ \
 582   UINT f_op1; \
 583   UINT f_r1; \
 584   UINT f_op2; \
 585   UINT f_r2; \
 586   unsigned int length;
 587 #define EXTRACT_FMT_ADDX_CODE \
 588   length = 2; \
 589   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 590   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 591   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 592   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 593
 594 #define EXTRACT_FMT_BC8_VARS \
 595   /* Instruction fields.  */ \
 596   UINT f_op1; \
 597   UINT f_r1; \
 598   INT f_disp8; \
 599   unsigned int length;
 600 #define EXTRACT_FMT_BC8_CODE \
 601   length = 2; \
 602   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 603   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 604   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 605
 606 #define EXTRACT_FMT_BC24_VARS \
 607   /* Instruction fields.  */ \
 608   UINT f_op1; \
 609   UINT f_r1; \
 610   INT f_disp24; \
 611   unsigned int length;
 612 #define EXTRACT_FMT_BC24_CODE \
 613   length = 4; \
 614   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 615   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 616   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 617
 618 #define EXTRACT_FMT_BEQ_VARS \
 619   /* Instruction fields.  */ \
 620   UINT f_op1; \
 621   UINT f_r1; \
 622   UINT f_op2; \
 623   UINT f_r2; \
 624   INT f_disp16; \
 625   unsigned int length;
 626 #define EXTRACT_FMT_BEQ_CODE \
 627   length = 4; \
 628   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 629   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 630   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 631   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 632   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 633
 634 #define EXTRACT_FMT_BEQZ_VARS \
 635   /* Instruction fields.  */ \
 636   UINT f_op1; \
 637   UINT f_r1; \
 638   UINT f_op2; \
 639   UINT f_r2; \
 640   INT f_disp16; \
 641   unsigned int length;
 642 #define EXTRACT_FMT_BEQZ_CODE \
 643   length = 4; \
 644   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 645   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 646   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 647   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 648   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 649
 650 #define EXTRACT_FMT_BL8_VARS \
 651   /* Instruction fields.  */ \
 652   UINT f_op1; \
 653   UINT f_r1; \
 654   INT f_disp8; \
 655   unsigned int length;
 656 #define EXTRACT_FMT_BL8_CODE \
 657   length = 2; \
 658   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 659   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 660   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 661
 662 #define EXTRACT_FMT_BL24_VARS \
 663   /* Instruction fields.  */ \
 664   UINT f_op1; \
 665   UINT f_r1; \
 666   INT f_disp24; \
 667   unsigned int length;
 668 #define EXTRACT_FMT_BL24_CODE \
 669   length = 4; \
 670   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 671   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 672   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 673
 674 #define EXTRACT_FMT_BRA8_VARS \
 675   /* Instruction fields.  */ \
 676   UINT f_op1; \
 677   UINT f_r1; \
 678   INT f_disp8; \
 679   unsigned int length;
 680 #define EXTRACT_FMT_BRA8_CODE \
 681   length = 2; \
 682   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 683   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 684   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 685
 686 #define EXTRACT_FMT_BRA24_VARS \
 687   /* Instruction fields.  */ \
 688   UINT f_op1; \
 689   UINT f_r1; \
 690   INT f_disp24; \
 691   unsigned int length;
 692 #define EXTRACT_FMT_BRA24_CODE \
 693   length = 4; \
 694   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 695   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 696   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 697
 698 #define EXTRACT_FMT_CMP_VARS \
 699   /* Instruction fields.  */ \
 700   UINT f_op1; \
 701   UINT f_r1; \
 702   UINT f_op2; \
 703   UINT f_r2; \
 704   unsigned int length;
 705 #define EXTRACT_FMT_CMP_CODE \
 706   length = 2; \
 707   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 708   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 709   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 710   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 711
 712 #define EXTRACT_FMT_CMPI_VARS \
 713   /* Instruction fields.  */ \
 714   UINT f_op1; \
 715   UINT f_r1; \
 716   UINT f_op2; \
 717   UINT f_r2; \
 718   INT f_simm16; \
 719   unsigned int length;
 720 #define EXTRACT_FMT_CMPI_CODE \
 721   length = 4; \
 722   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 723   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 724   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 725   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 726   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 727
 728 #define EXTRACT_FMT_DIV_VARS \
 729   /* Instruction fields.  */ \
 730   UINT f_op1; \
 731   UINT f_r1; \
 732   UINT f_op2; \
 733   UINT f_r2; \
 734   INT f_simm16; \
 735   unsigned int length;
 736 #define EXTRACT_FMT_DIV_CODE \
 737   length = 4; \
 738   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 739   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 740   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 741   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 742   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 743
 744 #define EXTRACT_FMT_JL_VARS \
 745   /* Instruction fields.  */ \
 746   UINT f_op1; \
 747   UINT f_r1; \
 748   UINT f_op2; \
 749   UINT f_r2; \
 750   unsigned int length;
 751 #define EXTRACT_FMT_JL_CODE \
 752   length = 2; \
 753   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 754   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 755   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 756   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 757
 758 #define EXTRACT_FMT_JMP_VARS \
 759   /* Instruction fields.  */ \
 760   UINT f_op1; \
 761   UINT f_r1; \
 762   UINT f_op2; \
 763   UINT f_r2; \
 764   unsigned int length;
 765 #define EXTRACT_FMT_JMP_CODE \
 766   length = 2; \
 767   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 768   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 769   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 770   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 771
 772 #define EXTRACT_FMT_LD_VARS \
 773   /* Instruction fields.  */ \
 774   UINT f_op1; \
 775   UINT f_r1; \
 776   UINT f_op2; \
 777   UINT f_r2; \
 778   unsigned int length;
 779 #define EXTRACT_FMT_LD_CODE \
 780   length = 2; \
 781   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 782   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 783   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 784   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 785
 786 #define EXTRACT_FMT_LD_D_VARS \
 787   /* Instruction fields.  */ \
 788   UINT f_op1; \
 789   UINT f_r1; \
 790   UINT f_op2; \
 791   UINT f_r2; \
 792   INT f_simm16; \
 793   unsigned int length;
 794 #define EXTRACT_FMT_LD_D_CODE \
 795   length = 4; \
 796   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 797   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 798   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 799   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 800   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 801
 802 #define EXTRACT_FMT_LDB_VARS \
 803   /* Instruction fields.  */ \
 804   UINT f_op1; \
 805   UINT f_r1; \
 806   UINT f_op2; \
 807   UINT f_r2; \
 808   unsigned int length;
 809 #define EXTRACT_FMT_LDB_CODE \
 810   length = 2; \
 811   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 812   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 813   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 814   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 815
 816 #define EXTRACT_FMT_LDB_D_VARS \
 817   /* Instruction fields.  */ \
 818   UINT f_op1; \
 819   UINT f_r1; \
 820   UINT f_op2; \
 821   UINT f_r2; \
 822   INT f_simm16; \
 823   unsigned int length;
 824 #define EXTRACT_FMT_LDB_D_CODE \
 825   length = 4; \
 826   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 827   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 828   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 829   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 830   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 831
 832 #define EXTRACT_FMT_LDH_VARS \
 833   /* Instruction fields.  */ \
 834   UINT f_op1; \
 835   UINT f_r1; \
 836   UINT f_op2; \
 837   UINT f_r2; \
 838   unsigned int length;
 839 #define EXTRACT_FMT_LDH_CODE \
 840   length = 2; \
 841   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 842   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 843   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 844   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 845
 846 #define EXTRACT_FMT_LDH_D_VARS \
 847   /* Instruction fields.  */ \
 848   UINT f_op1; \
 849   UINT f_r1; \
 850   UINT f_op2; \
 851   UINT f_r2; \
 852   INT f_simm16; \
 853   unsigned int length;
 854 #define EXTRACT_FMT_LDH_D_CODE \
 855   length = 4; \
 856   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 857   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 858   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 859   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 860   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 861
 862 #define EXTRACT_FMT_LD_PLUS_VARS \
 863   /* Instruction fields.  */ \
 864   UINT f_op1; \
 865   UINT f_r1; \
 866   UINT f_op2; \
 867   UINT f_r2; \
 868   unsigned int length;
 869 #define EXTRACT_FMT_LD_PLUS_CODE \
 870   length = 2; \
 871   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 872   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 873   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 874   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 875
 876 #define EXTRACT_FMT_LD24_VARS \
 877   /* Instruction fields.  */ \
 878   UINT f_op1; \
 879   UINT f_r1; \
 880   UINT f_uimm24; \
 881   unsigned int length;
 882 #define EXTRACT_FMT_LD24_CODE \
 883   length = 4; \
 884   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 885   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 886   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 887
 888 #define EXTRACT_FMT_LDI8_VARS \
 889   /* Instruction fields.  */ \
 890   UINT f_op1; \
 891   UINT f_r1; \
 892   INT f_simm8; \
 893   unsigned int length;
 894 #define EXTRACT_FMT_LDI8_CODE \
 895   length = 2; \
 896   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 897   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 898   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 899
 900 #define EXTRACT_FMT_LDI16_VARS \
 901   /* Instruction fields.  */ \
 902   UINT f_op1; \
 903   UINT f_r1; \
 904   UINT f_op2; \
 905   UINT f_r2; \
 906   INT f_simm16; \
 907   unsigned int length;
 908 #define EXTRACT_FMT_LDI16_CODE \
 909   length = 4; \
 910   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 911   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 912   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 913   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 914   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 915
 916 #define EXTRACT_FMT_LOCK_VARS \
 917   /* Instruction fields.  */ \
 918   UINT f_op1; \
 919   UINT f_r1; \
 920   UINT f_op2; \
 921   UINT f_r2; \
 922   unsigned int length;
 923 #define EXTRACT_FMT_LOCK_CODE \
 924   length = 2; \
 925   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 926   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 927   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 928   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 929
 930 #define EXTRACT_FMT_MACHI_VARS \
 931   /* Instruction fields.  */ \
 932   UINT f_op1; \
 933   UINT f_r1; \
 934   UINT f_op2; \
 935   UINT f_r2; \
 936   unsigned int length;
 937 #define EXTRACT_FMT_MACHI_CODE \
 938   length = 2; \
 939   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 940   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 941   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 942   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 943
 944 #define EXTRACT_FMT_MULHI_VARS \
 945   /* Instruction fields.  */ \
 946   UINT f_op1; \
 947   UINT f_r1; \
 948   UINT f_op2; \
 949   UINT f_r2; \
 950   unsigned int length;
 951 #define EXTRACT_FMT_MULHI_CODE \
 952   length = 2; \
 953   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 954   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 955   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 956   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 957
 958 #define EXTRACT_FMT_MV_VARS \
 959   /* Instruction fields.  */ \
 960   UINT f_op1; \
 961   UINT f_r1; \
 962   UINT f_op2; \
 963   UINT f_r2; \
 964   unsigned int length;
 965 #define EXTRACT_FMT_MV_CODE \
 966   length = 2; \
 967   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 968   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 969   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 970   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 971
 972 #define EXTRACT_FMT_MVFACHI_VARS \
 973   /* Instruction fields.  */ \
 974   UINT f_op1; \
 975   UINT f_r1; \
 976   UINT f_op2; \
 977   UINT f_r2; \
 978   unsigned int length;
 979 #define EXTRACT_FMT_MVFACHI_CODE \
 980   length = 2; \
 981   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 982   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 983   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 984   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 985
 986 #define EXTRACT_FMT_MVFC_VARS \
 987   /* Instruction fields.  */ \
 988   UINT f_op1; \
 989   UINT f_r1; \
 990   UINT f_op2; \
 991   UINT f_r2; \
 992   unsigned int length;
 993 #define EXTRACT_FMT_MVFC_CODE \
 994   length = 2; \
 995   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 996   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 997   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 998   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 999
1000 #define EXTRACT_FMT_MVTACHI_VARS \
1001   /* Instruction fields.  */ \
1002   UINT f_op1; \
1003   UINT f_r1; \
1004   UINT f_op2; \
1005   UINT f_r2; \
1006   unsigned int length;
1007 #define EXTRACT_FMT_MVTACHI_CODE \
1008   length = 2; \
1009   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1010   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1011   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1012   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1013
1014 #define EXTRACT_FMT_MVTC_VARS \
1015   /* Instruction fields.  */ \
1016   UINT f_op1; \
1017   UINT f_r1; \
1018   UINT f_op2; \
1019   UINT f_r2; \
1020   unsigned int length;
1021 #define EXTRACT_FMT_MVTC_CODE \
1022   length = 2; \
1023   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1024   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1025   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1026   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1027
1028 #define EXTRACT_FMT_NOP_VARS \
1029   /* Instruction fields.  */ \
1030   UINT f_op1; \
1031   UINT f_r1; \
1032   UINT f_op2; \
1033   UINT f_r2; \
1034   unsigned int length;
1035 #define EXTRACT_FMT_NOP_CODE \
1036   length = 2; \
1037   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1038   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1039   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1040   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1041
1042 #define EXTRACT_FMT_RAC_VARS \
1043   /* Instruction fields.  */ \
1044   UINT f_op1; \
1045   UINT f_r1; \
1046   UINT f_op2; \
1047   UINT f_r2; \
1048   unsigned int length;
1049 #define EXTRACT_FMT_RAC_CODE \
1050   length = 2; \
1051   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1052   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1053   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1054   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1055
1056 #define EXTRACT_FMT_RTE_VARS \
1057   /* Instruction fields.  */ \
1058   UINT f_op1; \
1059   UINT f_r1; \
1060   UINT f_op2; \
1061   UINT f_r2; \
1062   unsigned int length;
1063 #define EXTRACT_FMT_RTE_CODE \
1064   length = 2; \
1065   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1066   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1067   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1068   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1069
1070 #define EXTRACT_FMT_SETH_VARS \
1071   /* Instruction fields.  */ \
1072   UINT f_op1; \
1073   UINT f_r1; \
1074   UINT f_op2; \
1075   UINT f_r2; \
1076   UINT f_hi16; \
1077   unsigned int length;
1078 #define EXTRACT_FMT_SETH_CODE \
1079   length = 4; \
1080   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1081   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1082   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1083   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1084   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1085
1086 #define EXTRACT_FMT_SLL3_VARS \
1087   /* Instruction fields.  */ \
1088   UINT f_op1; \
1089   UINT f_r1; \
1090   UINT f_op2; \
1091   UINT f_r2; \
1092   INT f_simm16; \
1093   unsigned int length;
1094 #define EXTRACT_FMT_SLL3_CODE \
1095   length = 4; \
1096   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1097   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1098   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1099   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1100   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1101
1102 #define EXTRACT_FMT_SLLI_VARS \
1103   /* Instruction fields.  */ \
1104   UINT f_op1; \
1105   UINT f_r1; \
1106   UINT f_shift_op2; \
1107   UINT f_uimm5; \
1108   unsigned int length;
1109 #define EXTRACT_FMT_SLLI_CODE \
1110   length = 2; \
1111   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1112   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1113   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1114   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1115
1116 #define EXTRACT_FMT_ST_VARS \
1117   /* Instruction fields.  */ \
1118   UINT f_op1; \
1119   UINT f_r1; \
1120   UINT f_op2; \
1121   UINT f_r2; \
1122   unsigned int length;
1123 #define EXTRACT_FMT_ST_CODE \
1124   length = 2; \
1125   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1126   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1127   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1128   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1129
1130 #define EXTRACT_FMT_ST_D_VARS \
1131   /* Instruction fields.  */ \
1132   UINT f_op1; \
1133   UINT f_r1; \
1134   UINT f_op2; \
1135   UINT f_r2; \
1136   INT f_simm16; \
1137   unsigned int length;
1138 #define EXTRACT_FMT_ST_D_CODE \
1139   length = 4; \
1140   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1141   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1142   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1143   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1144   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1145
1146 #define EXTRACT_FMT_STB_VARS \
1147   /* Instruction fields.  */ \
1148   UINT f_op1; \
1149   UINT f_r1; \
1150   UINT f_op2; \
1151   UINT f_r2; \
1152   unsigned int length;
1153 #define EXTRACT_FMT_STB_CODE \
1154   length = 2; \
1155   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1156   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1157   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1158   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1159
1160 #define EXTRACT_FMT_STB_D_VARS \
1161   /* Instruction fields.  */ \
1162   UINT f_op1; \
1163   UINT f_r1; \
1164   UINT f_op2; \
1165   UINT f_r2; \
1166   INT f_simm16; \
1167   unsigned int length;
1168 #define EXTRACT_FMT_STB_D_CODE \
1169   length = 4; \
1170   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1171   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1172   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1173   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1174   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1175
1176 #define EXTRACT_FMT_STH_VARS \
1177   /* Instruction fields.  */ \
1178   UINT f_op1; \
1179   UINT f_r1; \
1180   UINT f_op2; \
1181   UINT f_r2; \
1182   unsigned int length;
1183 #define EXTRACT_FMT_STH_CODE \
1184   length = 2; \
1185   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1186   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1187   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1188   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1189
1190 #define EXTRACT_FMT_STH_D_VARS \
1191   /* Instruction fields.  */ \
1192   UINT f_op1; \
1193   UINT f_r1; \
1194   UINT f_op2; \
1195   UINT f_r2; \
1196   INT f_simm16; \
1197   unsigned int length;
1198 #define EXTRACT_FMT_STH_D_CODE \
1199   length = 4; \
1200   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1201   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1202   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1203   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1204   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1205
1206 #define EXTRACT_FMT_ST_PLUS_VARS \
1207   /* Instruction fields.  */ \
1208   UINT f_op1; \
1209   UINT f_r1; \
1210   UINT f_op2; \
1211   UINT f_r2; \
1212   unsigned int length;
1213 #define EXTRACT_FMT_ST_PLUS_CODE \
1214   length = 2; \
1215   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1216   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1217   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1218   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1219
1220 #define EXTRACT_FMT_TRAP_VARS \
1221   /* Instruction fields.  */ \
1222   UINT f_op1; \
1223   UINT f_r1; \
1224   UINT f_op2; \
1225   UINT f_uimm4; \
1226   unsigned int length;
1227 #define EXTRACT_FMT_TRAP_CODE \
1228   length = 2; \
1229   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1230   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1231   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1232   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1233
1234 #define EXTRACT_FMT_UNLOCK_VARS \
1235   /* Instruction fields.  */ \
1236   UINT f_op1; \
1237   UINT f_r1; \
1238   UINT f_op2; \
1239   UINT f_r2; \
1240   unsigned int length;
1241 #define EXTRACT_FMT_UNLOCK_CODE \
1242   length = 2; \
1243   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1244   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1245   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1246   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1247
1248 /* Collection of various things for the trace handler to use.  */
1249
1250 typedef struct trace_record {
1251   PCADDR pc;
1252   /* FIXME:wip */
1253 } TRACE_RECORD;
1254
1255 #endif /* CPU_M32RBF_H */