sim/m32r/cpu.h

   1 /* CPU family header for m32r.
   2
   3 This file is machine generated with CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32R_H
  26 #define CPU_M32R_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[7];
  49 #define GET_H_CR(a1) CPU (h_cr)[a1]
  50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
  51   /* accumulator */
  52   DI h_accum;
  53 #define GET_H_ACCUM() CPU (h_accum)
  54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
  60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
  61 /* start-sanitize-m32rx */
  62   /* abort flag */
  63   UBI h_abort;
  64 /* end-sanitize-m32rx */
  65 #define GET_H_ABORT() CPU (h_abort)
  66 #define SET_H_ABORT(x) (CPU (h_abort) = (x))
  67   /* condition bit */
  68   UBI h_cond;
  69 #define GET_H_COND() CPU (h_cond)
  70 #define SET_H_COND(x) (CPU (h_cond) = (x))
  71   /* sm */
  72   UBI h_sm;
  73 #define GET_H_SM() CPU (h_sm)
  74 #define SET_H_SM(x) (CPU (h_sm) = (x))
  75   /* bsm */
  76   UBI h_bsm;
  77 #define GET_H_BSM() CPU (h_bsm)
  78 #define SET_H_BSM(x) (CPU (h_bsm) = (x))
  79   /* ie */
  80   UBI h_ie;
  81 #define GET_H_IE() CPU (h_ie)
  82 #define SET_H_IE(x) (CPU (h_ie) = (x))
  83   /* bie */
  84   UBI h_bie;
  85 #define GET_H_BIE() CPU (h_bie)
  86 #define SET_H_BIE(x) (CPU (h_bie) = (x))
  87   /* bcond */
  88   UBI h_bcond;
  89 #define GET_H_BCOND() CPU (h_bcond)
  90 #define SET_H_BCOND(x) (CPU (h_bcond) = (x))
  91   /* bpc */
  92   SI h_bpc;
  93 #define GET_H_BPC() CPU (h_bpc)
  94 #define SET_H_BPC(x) (CPU (h_bpc) = (x))
  95   /* lock */
  96   UBI h_lock;
  97 #define GET_H_LOCK() CPU (h_lock)
  98 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  99   } hardware;
 100 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
 101   /* CPU profiling state information.  */
 102   struct {
 103   /* general registers */
 104   unsigned long h_gr;
 105   } profile;
 106 #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
 107 } M32R_CPU_DATA;
 108
 109 USI m32r_h_pc_get (SIM_CPU *);
 110 void m32r_h_pc_set (SIM_CPU *, USI);
 111 SI m32r_h_gr_get (SIM_CPU *, UINT);
 112 void m32r_h_gr_set (SIM_CPU *, UINT, SI);
 113 USI m32r_h_cr_get (SIM_CPU *, UINT);
 114 void m32r_h_cr_set (SIM_CPU *, UINT, USI);
 115 DI m32r_h_accum_get (SIM_CPU *);
 116 void m32r_h_accum_set (SIM_CPU *, DI);
 117 DI m32r_h_accums_get (SIM_CPU *, UINT);
 118 void m32r_h_accums_set (SIM_CPU *, UINT, DI);
 119 UBI m32r_h_abort_get (SIM_CPU *);
 120 void m32r_h_abort_set (SIM_CPU *, UBI);
 121 UBI m32r_h_cond_get (SIM_CPU *);
 122 void m32r_h_cond_set (SIM_CPU *, UBI);
 123 UBI m32r_h_sm_get (SIM_CPU *);
 124 void m32r_h_sm_set (SIM_CPU *, UBI);
 125 UBI m32r_h_bsm_get (SIM_CPU *);
 126 void m32r_h_bsm_set (SIM_CPU *, UBI);
 127 UBI m32r_h_ie_get (SIM_CPU *);
 128 void m32r_h_ie_set (SIM_CPU *, UBI);
 129 UBI m32r_h_bie_get (SIM_CPU *);
 130 void m32r_h_bie_set (SIM_CPU *, UBI);
 131 UBI m32r_h_bcond_get (SIM_CPU *);
 132 void m32r_h_bcond_set (SIM_CPU *, UBI);
 133 SI m32r_h_bpc_get (SIM_CPU *);
 134 void m32r_h_bpc_set (SIM_CPU *, SI);
 135 UBI m32r_h_lock_get (SIM_CPU *);
 136 void m32r_h_lock_set (SIM_CPU *, UBI);
 137 extern DECODE *m32r_decode (SIM_CPU *, PCADDR, insn_t);
 138
 139 /* The ARGBUF struct.  */
 140 struct argbuf {
 141   /* These are the baseclass definitions.  */
 142   unsigned int length;
 143   PCADDR addr;
 144   const struct cgen_insn *opcode;
 145 #if ! defined (SCACHE_P)
 146   insn_t insn;
 147 #endif
 148   /* cpu specific data follows */
 149   union {
 150     struct { /* e.g. add $dr,$sr */
 151       SI * f_r1;
 152       SI * f_r2;
 153     } fmt_0_add;
 154     struct { /* e.g. add3 $dr,$sr,#$slo16 */
 155       SI * f_r1;
 156       SI * f_r2;
 157       HI f_simm16;
 158     } fmt_1_add3;
 159     struct { /* e.g. and3 $dr,$sr,#$uimm16 */
 160       SI * f_r1;
 161       SI * f_r2;
 162       USI f_uimm16;
 163     } fmt_2_and3;
 164     struct { /* e.g. or3 $dr,$sr,#$ulo16 */
 165       SI * f_r1;
 166       SI * f_r2;
 167       UHI f_uimm16;
 168     } fmt_3_or3;
 169     struct { /* e.g. addi $dr,#$simm8 */
 170       SI * f_r1;
 171       SI f_simm8;
 172     } fmt_4_addi;
 173     struct { /* e.g. addv $dr,$sr */
 174       SI * f_r1;
 175       SI * f_r2;
 176     } fmt_5_addv;
 177     struct { /* e.g. addv3 $dr,$sr,#$simm16 */
 178       SI * f_r1;
 179       SI * f_r2;
 180       SI f_simm16;
 181     } fmt_6_addv3;
 182     struct { /* e.g. addx $dr,$sr */
 183       SI * f_r1;
 184       SI * f_r2;
 185     } fmt_7_addx;
 186     struct { /* e.g. bc $disp8 */
 187       IADDR f_disp8;
 188     } fmt_8_bc8;
 189     struct { /* e.g. bc $disp24 */
 190       IADDR f_disp24;
 191     } fmt_9_bc24;
 192     struct { /* e.g. beq $src1,$src2,$disp16 */
 193       SI * f_r1;
 194       SI * f_r2;
 195       IADDR f_disp16;
 196     } fmt_10_beq;
 197     struct { /* e.g. beqz $src2,$disp16 */
 198       SI * f_r2;
 199       IADDR f_disp16;
 200     } fmt_11_beqz;
 201     struct { /* e.g. bl $disp8 */
 202       IADDR f_disp8;
 203     } fmt_12_bl8;
 204     struct { /* e.g. bl $disp24 */
 205       IADDR f_disp24;
 206     } fmt_13_bl24;
 207     struct { /* e.g. bra $disp8 */
 208       IADDR f_disp8;
 209     } fmt_14_bra8;
 210     struct { /* e.g. bra $disp24 */
 211       IADDR f_disp24;
 212     } fmt_15_bra24;
 213     struct { /* e.g. cmp $src1,$src2 */
 214       SI * f_r1;
 215       SI * f_r2;
 216     } fmt_16_cmp;
 217     struct { /* e.g. cmpi $src2,#$simm16 */
 218       SI * f_r2;
 219       SI f_simm16;
 220     } fmt_17_cmpi;
 221     struct { /* e.g. cmpui $src2,#$uimm16 */
 222       SI * f_r2;
 223       USI f_uimm16;
 224     } fmt_18_cmpui;
 225     struct { /* e.g. div $dr,$sr */
 226       SI * f_r1;
 227       SI * f_r2;
 228     } fmt_19_div;
 229     struct { /* e.g. jl $sr */
 230       SI * f_r2;
 231     } fmt_20_jl;
 232     struct { /* e.g. jmp $sr */
 233       SI * f_r2;
 234     } fmt_21_jmp;
 235     struct { /* e.g. ld $dr,@$sr */
 236       SI * f_r1;
 237       SI * f_r2;
 238     } fmt_22_ld;
 239     struct { /* e.g. ld $dr,@($slo16,$sr) */
 240       SI * f_r1;
 241       SI * f_r2;
 242       HI f_simm16;
 243     } fmt_23_ld_d;
 244     struct { /* e.g. ldb $dr,@$sr */
 245       SI * f_r1;
 246       SI * f_r2;
 247     } fmt_24_ldb;
 248     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 249       SI * f_r1;
 250       SI * f_r2;
 251       HI f_simm16;
 252     } fmt_25_ldb_d;
 253     struct { /* e.g. ldh $dr,@$sr */
 254       SI * f_r1;
 255       SI * f_r2;
 256     } fmt_26_ldh;
 257     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 258       SI * f_r1;
 259       SI * f_r2;
 260       HI f_simm16;
 261     } fmt_27_ldh_d;
 262     struct { /* e.g. ld $dr,@$sr+ */
 263       SI * f_r1;
 264       SI * f_r2;
 265     } fmt_28_ld_plus;
 266     struct { /* e.g. ld24 $dr,#$uimm24 */
 267       SI * f_r1;
 268       ADDR f_uimm24;
 269     } fmt_29_ld24;
 270     struct { /* e.g. ldi $dr,#$simm8 */
 271       SI * f_r1;
 272       SI f_simm8;
 273     } fmt_30_ldi8;
 274     struct { /* e.g. ldi $dr,$slo16 */
 275       SI * f_r1;
 276       HI f_simm16;
 277     } fmt_31_ldi16;
 278     struct { /* e.g. lock $dr,@$sr */
 279       SI * f_r1;
 280       SI * f_r2;
 281     } fmt_32_lock;
 282     struct { /* e.g. machi $src1,$src2 */
 283       SI * f_r1;
 284       SI * f_r2;
 285     } fmt_33_machi;
 286     struct { /* e.g. mulhi $src1,$src2 */
 287       SI * f_r1;
 288       SI * f_r2;
 289     } fmt_34_mulhi;
 290     struct { /* e.g. mv $dr,$sr */
 291       SI * f_r1;
 292       SI * f_r2;
 293     } fmt_35_mv;
 294     struct { /* e.g. mvfachi $dr */
 295       SI * f_r1;
 296     } fmt_36_mvfachi;
 297     struct { /* e.g. mvfc $dr,$scr */
 298       SI * f_r1;
 299       UINT f_r2;
 300     } fmt_37_mvfc;
 301     struct { /* e.g. mvtachi $src1 */
 302       SI * f_r1;
 303     } fmt_38_mvtachi;
 304     struct { /* e.g. mvtc $sr,$dcr */
 305       UINT f_r1;
 306       SI * f_r2;
 307     } fmt_39_mvtc;
 308     struct { /* e.g. nop */
 309       int empty;
 310     } fmt_40_nop;
 311     struct { /* e.g. rac */
 312       int empty;
 313     } fmt_41_rac;
 314     struct { /* e.g. rte */
 315       int empty;
 316     } fmt_42_rte;
 317     struct { /* e.g. seth $dr,#$hi16 */
 318       SI * f_r1;
 319       UHI f_hi16;
 320     } fmt_43_seth;
 321     struct { /* e.g. sll3 $dr,$sr,#$simm16 */
 322       SI * f_r1;
 323       SI * f_r2;
 324       SI f_simm16;
 325     } fmt_44_sll3;
 326     struct { /* e.g. slli $dr,#$uimm5 */
 327       SI * f_r1;
 328       USI f_uimm5;
 329     } fmt_45_slli;
 330     struct { /* e.g. st $src1,@$src2 */
 331       SI * f_r1;
 332       SI * f_r2;
 333     } fmt_46_st;
 334     struct { /* e.g. st $src1,@($slo16,$src2) */
 335       SI * f_r1;
 336       SI * f_r2;
 337       HI f_simm16;
 338     } fmt_47_st_d;
 339     struct { /* e.g. stb $src1,@$src2 */
 340       SI * f_r1;
 341       SI * f_r2;
 342     } fmt_48_stb;
 343     struct { /* e.g. stb $src1,@($slo16,$src2) */
 344       SI * f_r1;
 345       SI * f_r2;
 346       HI f_simm16;
 347     } fmt_49_stb_d;
 348     struct { /* e.g. sth $src1,@$src2 */
 349       SI * f_r1;
 350       SI * f_r2;
 351     } fmt_50_sth;
 352     struct { /* e.g. sth $src1,@($slo16,$src2) */
 353       SI * f_r1;
 354       SI * f_r2;
 355       HI f_simm16;
 356     } fmt_51_sth_d;
 357     struct { /* e.g. st $src1,@+$src2 */
 358       SI * f_r1;
 359       SI * f_r2;
 360     } fmt_52_st_plus;
 361     struct { /* e.g. trap #$uimm4 */
 362       USI f_uimm4;
 363     } fmt_53_trap;
 364     struct { /* e.g. unlock $src1,@$src2 */
 365       SI * f_r1;
 366       SI * f_r2;
 367     } fmt_54_unlock;
 368   } fields;
 369 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
 370   unsigned long h_gr_get;
 371   unsigned long h_gr_set;
 372 #endif
 373 };
 374
 375 /* A cached insn.
 376    This is currently also used in the non-scache case.  In this situation we
 377    assume the cache size is 1, and do a few things a little differently.  */
 378 /* FIXME: non-scache version to be redone.  */
 379
 380 struct scache {
 381   IADDR next;
 382   union {
 383 #if ! WITH_SEM_SWITCH_FULL
 384     SEMANTIC_FN *sem_fn;
 385 #endif
 386 #if ! WITH_SEM_SWITCH_FAST
 387     SEMANTIC_FN *sem_fast_fn;
 388 #endif
 389 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
 390 #ifdef __GNUC__
 391     void *sem_case;
 392 #else
 393     int sem_case;
 394 #endif
 395 #endif
 396   } semantic;
 397   struct argbuf argbuf;
 398 };
 399
 400 /* Macros to simplify extraction, reading and semantic code.
 401    These define and assign the local vars that contain the insn's fields.  */
 402
 403 #define EXTRACT_FMT_0_ADD_VARS \
 404   /* Instruction fields.  */ \
 405   UINT f_op1; \
 406   UINT f_r1; \
 407   UINT f_op2; \
 408   UINT f_r2; \
 409   unsigned int length;
 410 #define EXTRACT_FMT_0_ADD_CODE \
 411   length = 2; \
 412   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 413   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 414   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 415   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 416
 417 #define EXTRACT_FMT_1_ADD3_VARS \
 418   /* Instruction fields.  */ \
 419   UINT f_op1; \
 420   UINT f_r1; \
 421   UINT f_op2; \
 422   UINT f_r2; \
 423   int f_simm16; \
 424   unsigned int length;
 425 #define EXTRACT_FMT_1_ADD3_CODE \
 426   length = 4; \
 427   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 428   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 429   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 430   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 431   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 432
 433 #define EXTRACT_FMT_2_AND3_VARS \
 434   /* Instruction fields.  */ \
 435   UINT f_op1; \
 436   UINT f_r1; \
 437   UINT f_op2; \
 438   UINT f_r2; \
 439   UINT f_uimm16; \
 440   unsigned int length;
 441 #define EXTRACT_FMT_2_AND3_CODE \
 442   length = 4; \
 443   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 444   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 445   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 446   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 447   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 448
 449 #define EXTRACT_FMT_3_OR3_VARS \
 450   /* Instruction fields.  */ \
 451   UINT f_op1; \
 452   UINT f_r1; \
 453   UINT f_op2; \
 454   UINT f_r2; \
 455   UINT f_uimm16; \
 456   unsigned int length;
 457 #define EXTRACT_FMT_3_OR3_CODE \
 458   length = 4; \
 459   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 460   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 461   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 462   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 463   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 464
 465 #define EXTRACT_FMT_4_ADDI_VARS \
 466   /* Instruction fields.  */ \
 467   UINT f_op1; \
 468   UINT f_r1; \
 469   int f_simm8; \
 470   unsigned int length;
 471 #define EXTRACT_FMT_4_ADDI_CODE \
 472   length = 2; \
 473   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 474   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 475   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 476
 477 #define EXTRACT_FMT_5_ADDV_VARS \
 478   /* Instruction fields.  */ \
 479   UINT f_op1; \
 480   UINT f_r1; \
 481   UINT f_op2; \
 482   UINT f_r2; \
 483   unsigned int length;
 484 #define EXTRACT_FMT_5_ADDV_CODE \
 485   length = 2; \
 486   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 487   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 488   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 489   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 490
 491 #define EXTRACT_FMT_6_ADDV3_VARS \
 492   /* Instruction fields.  */ \
 493   UINT f_op1; \
 494   UINT f_r1; \
 495   UINT f_op2; \
 496   UINT f_r2; \
 497   int f_simm16; \
 498   unsigned int length;
 499 #define EXTRACT_FMT_6_ADDV3_CODE \
 500   length = 4; \
 501   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 502   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 503   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 504   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 505   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 506
 507 #define EXTRACT_FMT_7_ADDX_VARS \
 508   /* Instruction fields.  */ \
 509   UINT f_op1; \
 510   UINT f_r1; \
 511   UINT f_op2; \
 512   UINT f_r2; \
 513   unsigned int length;
 514 #define EXTRACT_FMT_7_ADDX_CODE \
 515   length = 2; \
 516   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 517   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 518   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 519   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 520
 521 #define EXTRACT_FMT_8_BC8_VARS \
 522   /* Instruction fields.  */ \
 523   UINT f_op1; \
 524   UINT f_r1; \
 525   int f_disp8; \
 526   unsigned int length;
 527 #define EXTRACT_FMT_8_BC8_CODE \
 528   length = 2; \
 529   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 530   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 531   f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
 532
 533 #define EXTRACT_FMT_9_BC24_VARS \
 534   /* Instruction fields.  */ \
 535   UINT f_op1; \
 536   UINT f_r1; \
 537   int f_disp24; \
 538   unsigned int length;
 539 #define EXTRACT_FMT_9_BC24_CODE \
 540   length = 4; \
 541   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 542   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 543   f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
 544
 545 #define EXTRACT_FMT_10_BEQ_VARS \
 546   /* Instruction fields.  */ \
 547   UINT f_op1; \
 548   UINT f_r1; \
 549   UINT f_op2; \
 550   UINT f_r2; \
 551   int f_disp16; \
 552   unsigned int length;
 553 #define EXTRACT_FMT_10_BEQ_CODE \
 554   length = 4; \
 555   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 556   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 557   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 558   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 559   f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \
 560
 561 #define EXTRACT_FMT_11_BEQZ_VARS \
 562   /* Instruction fields.  */ \
 563   UINT f_op1; \
 564   UINT f_r1; \
 565   UINT f_op2; \
 566   UINT f_r2; \
 567   int f_disp16; \
 568   unsigned int length;
 569 #define EXTRACT_FMT_11_BEQZ_CODE \
 570   length = 4; \
 571   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 572   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 573   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 574   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 575   f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \
 576
 577 #define EXTRACT_FMT_12_BL8_VARS \
 578   /* Instruction fields.  */ \
 579   UINT f_op1; \
 580   UINT f_r1; \
 581   int f_disp8; \
 582   unsigned int length;
 583 #define EXTRACT_FMT_12_BL8_CODE \
 584   length = 2; \
 585   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 586   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 587   f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
 588
 589 #define EXTRACT_FMT_13_BL24_VARS \
 590   /* Instruction fields.  */ \
 591   UINT f_op1; \
 592   UINT f_r1; \
 593   int f_disp24; \
 594   unsigned int length;
 595 #define EXTRACT_FMT_13_BL24_CODE \
 596   length = 4; \
 597   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 598   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 599   f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
 600
 601 #define EXTRACT_FMT_14_BRA8_VARS \
 602   /* Instruction fields.  */ \
 603   UINT f_op1; \
 604   UINT f_r1; \
 605   int f_disp8; \
 606   unsigned int length;
 607 #define EXTRACT_FMT_14_BRA8_CODE \
 608   length = 2; \
 609   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 610   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 611   f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
 612
 613 #define EXTRACT_FMT_15_BRA24_VARS \
 614   /* Instruction fields.  */ \
 615   UINT f_op1; \
 616   UINT f_r1; \
 617   int f_disp24; \
 618   unsigned int length;
 619 #define EXTRACT_FMT_15_BRA24_CODE \
 620   length = 4; \
 621   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 622   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 623   f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
 624
 625 #define EXTRACT_FMT_16_CMP_VARS \
 626   /* Instruction fields.  */ \
 627   UINT f_op1; \
 628   UINT f_r1; \
 629   UINT f_op2; \
 630   UINT f_r2; \
 631   unsigned int length;
 632 #define EXTRACT_FMT_16_CMP_CODE \
 633   length = 2; \
 634   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 635   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 636   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 637   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 638
 639 #define EXTRACT_FMT_17_CMPI_VARS \
 640   /* Instruction fields.  */ \
 641   UINT f_op1; \
 642   UINT f_r1; \
 643   UINT f_op2; \
 644   UINT f_r2; \
 645   int f_simm16; \
 646   unsigned int length;
 647 #define EXTRACT_FMT_17_CMPI_CODE \
 648   length = 4; \
 649   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 650   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 651   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 652   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 653   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 654
 655 #define EXTRACT_FMT_18_CMPUI_VARS \
 656   /* Instruction fields.  */ \
 657   UINT f_op1; \
 658   UINT f_r1; \
 659   UINT f_op2; \
 660   UINT f_r2; \
 661   UINT f_uimm16; \
 662   unsigned int length;
 663 #define EXTRACT_FMT_18_CMPUI_CODE \
 664   length = 4; \
 665   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 666   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 667   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 668   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 669   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 670
 671 #define EXTRACT_FMT_19_DIV_VARS \
 672   /* Instruction fields.  */ \
 673   UINT f_op1; \
 674   UINT f_r1; \
 675   UINT f_op2; \
 676   UINT f_r2; \
 677   int f_simm16; \
 678   unsigned int length;
 679 #define EXTRACT_FMT_19_DIV_CODE \
 680   length = 4; \
 681   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 682   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 683   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 684   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 685   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 686
 687 #define EXTRACT_FMT_20_JL_VARS \
 688   /* Instruction fields.  */ \
 689   UINT f_op1; \
 690   UINT f_r1; \
 691   UINT f_op2; \
 692   UINT f_r2; \
 693   unsigned int length;
 694 #define EXTRACT_FMT_20_JL_CODE \
 695   length = 2; \
 696   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 697   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 698   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 699   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 700
 701 #define EXTRACT_FMT_21_JMP_VARS \
 702   /* Instruction fields.  */ \
 703   UINT f_op1; \
 704   UINT f_r1; \
 705   UINT f_op2; \
 706   UINT f_r2; \
 707   unsigned int length;
 708 #define EXTRACT_FMT_21_JMP_CODE \
 709   length = 2; \
 710   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 711   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 712   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 713   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 714
 715 #define EXTRACT_FMT_22_LD_VARS \
 716   /* Instruction fields.  */ \
 717   UINT f_op1; \
 718   UINT f_r1; \
 719   UINT f_op2; \
 720   UINT f_r2; \
 721   unsigned int length;
 722 #define EXTRACT_FMT_22_LD_CODE \
 723   length = 2; \
 724   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 725   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 726   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 727   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 728
 729 #define EXTRACT_FMT_23_LD_D_VARS \
 730   /* Instruction fields.  */ \
 731   UINT f_op1; \
 732   UINT f_r1; \
 733   UINT f_op2; \
 734   UINT f_r2; \
 735   int f_simm16; \
 736   unsigned int length;
 737 #define EXTRACT_FMT_23_LD_D_CODE \
 738   length = 4; \
 739   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 740   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 741   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 742   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 743   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 744
 745 #define EXTRACT_FMT_24_LDB_VARS \
 746   /* Instruction fields.  */ \
 747   UINT f_op1; \
 748   UINT f_r1; \
 749   UINT f_op2; \
 750   UINT f_r2; \
 751   unsigned int length;
 752 #define EXTRACT_FMT_24_LDB_CODE \
 753   length = 2; \
 754   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 755   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 756   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 757   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 758
 759 #define EXTRACT_FMT_25_LDB_D_VARS \
 760   /* Instruction fields.  */ \
 761   UINT f_op1; \
 762   UINT f_r1; \
 763   UINT f_op2; \
 764   UINT f_r2; \
 765   int f_simm16; \
 766   unsigned int length;
 767 #define EXTRACT_FMT_25_LDB_D_CODE \
 768   length = 4; \
 769   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 770   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 771   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 772   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 773   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 774
 775 #define EXTRACT_FMT_26_LDH_VARS \
 776   /* Instruction fields.  */ \
 777   UINT f_op1; \
 778   UINT f_r1; \
 779   UINT f_op2; \
 780   UINT f_r2; \
 781   unsigned int length;
 782 #define EXTRACT_FMT_26_LDH_CODE \
 783   length = 2; \
 784   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 785   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 786   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 787   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 788
 789 #define EXTRACT_FMT_27_LDH_D_VARS \
 790   /* Instruction fields.  */ \
 791   UINT f_op1; \
 792   UINT f_r1; \
 793   UINT f_op2; \
 794   UINT f_r2; \
 795   int f_simm16; \
 796   unsigned int length;
 797 #define EXTRACT_FMT_27_LDH_D_CODE \
 798   length = 4; \
 799   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 800   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 801   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 802   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 803   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 804
 805 #define EXTRACT_FMT_28_LD_PLUS_VARS \
 806   /* Instruction fields.  */ \
 807   UINT f_op1; \
 808   UINT f_r1; \
 809   UINT f_op2; \
 810   UINT f_r2; \
 811   unsigned int length;
 812 #define EXTRACT_FMT_28_LD_PLUS_CODE \
 813   length = 2; \
 814   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 815   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 816   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 817   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 818
 819 #define EXTRACT_FMT_29_LD24_VARS \
 820   /* Instruction fields.  */ \
 821   UINT f_op1; \
 822   UINT f_r1; \
 823   UINT f_uimm24; \
 824   unsigned int length;
 825 #define EXTRACT_FMT_29_LD24_CODE \
 826   length = 4; \
 827   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 828   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 829   f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
 830
 831 #define EXTRACT_FMT_30_LDI8_VARS \
 832   /* Instruction fields.  */ \
 833   UINT f_op1; \
 834   UINT f_r1; \
 835   int f_simm8; \
 836   unsigned int length;
 837 #define EXTRACT_FMT_30_LDI8_CODE \
 838   length = 2; \
 839   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 840   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 841   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 842
 843 #define EXTRACT_FMT_31_LDI16_VARS \
 844   /* Instruction fields.  */ \
 845   UINT f_op1; \
 846   UINT f_r1; \
 847   UINT f_op2; \
 848   UINT f_r2; \
 849   int f_simm16; \
 850   unsigned int length;
 851 #define EXTRACT_FMT_31_LDI16_CODE \
 852   length = 4; \
 853   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 854   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 855   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 856   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 857   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 858
 859 #define EXTRACT_FMT_32_LOCK_VARS \
 860   /* Instruction fields.  */ \
 861   UINT f_op1; \
 862   UINT f_r1; \
 863   UINT f_op2; \
 864   UINT f_r2; \
 865   unsigned int length;
 866 #define EXTRACT_FMT_32_LOCK_CODE \
 867   length = 2; \
 868   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 869   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 870   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 871   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 872
 873 #define EXTRACT_FMT_33_MACHI_VARS \
 874   /* Instruction fields.  */ \
 875   UINT f_op1; \
 876   UINT f_r1; \
 877   UINT f_op2; \
 878   UINT f_r2; \
 879   unsigned int length;
 880 #define EXTRACT_FMT_33_MACHI_CODE \
 881   length = 2; \
 882   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 883   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 884   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 885   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 886
 887 #define EXTRACT_FMT_34_MULHI_VARS \
 888   /* Instruction fields.  */ \
 889   UINT f_op1; \
 890   UINT f_r1; \
 891   UINT f_op2; \
 892   UINT f_r2; \
 893   unsigned int length;
 894 #define EXTRACT_FMT_34_MULHI_CODE \
 895   length = 2; \
 896   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 897   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 898   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 899   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 900
 901 #define EXTRACT_FMT_35_MV_VARS \
 902   /* Instruction fields.  */ \
 903   UINT f_op1; \
 904   UINT f_r1; \
 905   UINT f_op2; \
 906   UINT f_r2; \
 907   unsigned int length;
 908 #define EXTRACT_FMT_35_MV_CODE \
 909   length = 2; \
 910   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 911   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 912   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 913   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 914
 915 #define EXTRACT_FMT_36_MVFACHI_VARS \
 916   /* Instruction fields.  */ \
 917   UINT f_op1; \
 918   UINT f_r1; \
 919   UINT f_op2; \
 920   UINT f_r2; \
 921   unsigned int length;
 922 #define EXTRACT_FMT_36_MVFACHI_CODE \
 923   length = 2; \
 924   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 925   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 926   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 927   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 928
 929 #define EXTRACT_FMT_37_MVFC_VARS \
 930   /* Instruction fields.  */ \
 931   UINT f_op1; \
 932   UINT f_r1; \
 933   UINT f_op2; \
 934   UINT f_r2; \
 935   unsigned int length;
 936 #define EXTRACT_FMT_37_MVFC_CODE \
 937   length = 2; \
 938   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 939   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 940   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 941   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 942
 943 #define EXTRACT_FMT_38_MVTACHI_VARS \
 944   /* Instruction fields.  */ \
 945   UINT f_op1; \
 946   UINT f_r1; \
 947   UINT f_op2; \
 948   UINT f_r2; \
 949   unsigned int length;
 950 #define EXTRACT_FMT_38_MVTACHI_CODE \
 951   length = 2; \
 952   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 953   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 954   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 955   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 956
 957 #define EXTRACT_FMT_39_MVTC_VARS \
 958   /* Instruction fields.  */ \
 959   UINT f_op1; \
 960   UINT f_r1; \
 961   UINT f_op2; \
 962   UINT f_r2; \
 963   unsigned int length;
 964 #define EXTRACT_FMT_39_MVTC_CODE \
 965   length = 2; \
 966   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 967   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 968   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 969   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 970
 971 #define EXTRACT_FMT_40_NOP_VARS \
 972   /* Instruction fields.  */ \
 973   UINT f_op1; \
 974   UINT f_r1; \
 975   UINT f_op2; \
 976   UINT f_r2; \
 977   unsigned int length;
 978 #define EXTRACT_FMT_40_NOP_CODE \
 979   length = 2; \
 980   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 981   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 982   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 983   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 984
 985 #define EXTRACT_FMT_41_RAC_VARS \
 986   /* Instruction fields.  */ \
 987   UINT f_op1; \
 988   UINT f_r1; \
 989   UINT f_op2; \
 990   UINT f_r2; \
 991   unsigned int length;
 992 #define EXTRACT_FMT_41_RAC_CODE \
 993   length = 2; \
 994   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 995   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 996   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 997   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 998
 999 #define EXTRACT_FMT_42_RTE_VARS \
1000   /* Instruction fields.  */ \
1001   UINT f_op1; \
1002   UINT f_r1; \
1003   UINT f_op2; \
1004   UINT f_r2; \
1005   unsigned int length;
1006 #define EXTRACT_FMT_42_RTE_CODE \
1007   length = 2; \
1008   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1009   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1010   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1011   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1012
1013 #define EXTRACT_FMT_43_SETH_VARS \
1014   /* Instruction fields.  */ \
1015   UINT f_op1; \
1016   UINT f_r1; \
1017   UINT f_op2; \
1018   UINT f_r2; \
1019   UINT f_hi16; \
1020   unsigned int length;
1021 #define EXTRACT_FMT_43_SETH_CODE \
1022   length = 4; \
1023   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1024   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1025   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1026   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1027   f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1028
1029 #define EXTRACT_FMT_44_SLL3_VARS \
1030   /* Instruction fields.  */ \
1031   UINT f_op1; \
1032   UINT f_r1; \
1033   UINT f_op2; \
1034   UINT f_r2; \
1035   int f_simm16; \
1036   unsigned int length;
1037 #define EXTRACT_FMT_44_SLL3_CODE \
1038   length = 4; \
1039   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1040   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1041   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1042   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1043   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1044
1045 #define EXTRACT_FMT_45_SLLI_VARS \
1046   /* Instruction fields.  */ \
1047   UINT f_op1; \
1048   UINT f_r1; \
1049   UINT f_shift_op2; \
1050   UINT f_uimm5; \
1051   unsigned int length;
1052 #define EXTRACT_FMT_45_SLLI_CODE \
1053   length = 2; \
1054   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1055   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1056   f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1057   f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1058
1059 #define EXTRACT_FMT_46_ST_VARS \
1060   /* Instruction fields.  */ \
1061   UINT f_op1; \
1062   UINT f_r1; \
1063   UINT f_op2; \
1064   UINT f_r2; \
1065   unsigned int length;
1066 #define EXTRACT_FMT_46_ST_CODE \
1067   length = 2; \
1068   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1069   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1070   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1071   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1072
1073 #define EXTRACT_FMT_47_ST_D_VARS \
1074   /* Instruction fields.  */ \
1075   UINT f_op1; \
1076   UINT f_r1; \
1077   UINT f_op2; \
1078   UINT f_r2; \
1079   int f_simm16; \
1080   unsigned int length;
1081 #define EXTRACT_FMT_47_ST_D_CODE \
1082   length = 4; \
1083   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1084   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1085   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1086   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1087   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1088
1089 #define EXTRACT_FMT_48_STB_VARS \
1090   /* Instruction fields.  */ \
1091   UINT f_op1; \
1092   UINT f_r1; \
1093   UINT f_op2; \
1094   UINT f_r2; \
1095   unsigned int length;
1096 #define EXTRACT_FMT_48_STB_CODE \
1097   length = 2; \
1098   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1099   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1100   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1101   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1102
1103 #define EXTRACT_FMT_49_STB_D_VARS \
1104   /* Instruction fields.  */ \
1105   UINT f_op1; \
1106   UINT f_r1; \
1107   UINT f_op2; \
1108   UINT f_r2; \
1109   int f_simm16; \
1110   unsigned int length;
1111 #define EXTRACT_FMT_49_STB_D_CODE \
1112   length = 4; \
1113   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1114   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1115   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1116   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1117   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1118
1119 #define EXTRACT_FMT_50_STH_VARS \
1120   /* Instruction fields.  */ \
1121   UINT f_op1; \
1122   UINT f_r1; \
1123   UINT f_op2; \
1124   UINT f_r2; \
1125   unsigned int length;
1126 #define EXTRACT_FMT_50_STH_CODE \
1127   length = 2; \
1128   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1129   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1130   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1131   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1132
1133 #define EXTRACT_FMT_51_STH_D_VARS \
1134   /* Instruction fields.  */ \
1135   UINT f_op1; \
1136   UINT f_r1; \
1137   UINT f_op2; \
1138   UINT f_r2; \
1139   int f_simm16; \
1140   unsigned int length;
1141 #define EXTRACT_FMT_51_STH_D_CODE \
1142   length = 4; \
1143   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1144   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1145   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1146   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1147   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1148
1149 #define EXTRACT_FMT_52_ST_PLUS_VARS \
1150   /* Instruction fields.  */ \
1151   UINT f_op1; \
1152   UINT f_r1; \
1153   UINT f_op2; \
1154   UINT f_r2; \
1155   unsigned int length;
1156 #define EXTRACT_FMT_52_ST_PLUS_CODE \
1157   length = 2; \
1158   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1159   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1160   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1161   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1162
1163 #define EXTRACT_FMT_53_TRAP_VARS \
1164   /* Instruction fields.  */ \
1165   UINT f_op1; \
1166   UINT f_r1; \
1167   UINT f_op2; \
1168   UINT f_uimm4; \
1169   unsigned int length;
1170 #define EXTRACT_FMT_53_TRAP_CODE \
1171   length = 2; \
1172   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1173   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1174   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1175   f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1176
1177 #define EXTRACT_FMT_54_UNLOCK_VARS \
1178   /* Instruction fields.  */ \
1179   UINT f_op1; \
1180   UINT f_r1; \
1181   UINT f_op2; \
1182   UINT f_r2; \
1183   unsigned int length;
1184 #define EXTRACT_FMT_54_UNLOCK_CODE \
1185   length = 2; \
1186   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1187   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1188   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1189   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1190
1191 #endif /* CPU_M32R_H */