sim/m32r/m32r.c

   1 /* m32r simulator support code
   2    Copyright (C) 1996-2024 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* This must come before any other includes.  */
  21 #include "defs.h"
  22
  23 #define WANT_CPU m32rbf
  24 #define WANT_CPU_M32RBF
  25
  26 #include "sim-main.h"
  27 #include "cgen-mem.h"
  28 #include "cgen-ops.h"
  29 #include <stdlib.h>
  30
  31 #include "m32r-sim.h"
  32
  33 /* Return the size of REGNO in bytes.  */
  34
  35 static int
  36 m32rbf_register_size (int regno)
  37 {
  38   return 4;
  39 }
  40
  41 /* Decode gdb ctrl register number.  */
  42
  43 int
  44 m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
  45 {
  46   switch (gdb_regnum)
  47     {
  48       case PSW_REGNUM : return H_CR_PSW;
  49       case CBR_REGNUM : return H_CR_CBR;
  50       case SPI_REGNUM : return H_CR_SPI;
  51       case SPU_REGNUM : return H_CR_SPU;
  52       case BPC_REGNUM : return H_CR_BPC;
  53       case BBPSW_REGNUM : return H_CR_BBPSW;
  54       case BBPC_REGNUM : return H_CR_BBPC;
  55       case EVB_REGNUM : return H_CR_CR5;
  56     }
  57   abort ();
  58 }
  59
  60 /* The contents of BUF are in target byte order.  */
  61
  62 int
  63 m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, void *buf, int len)
  64 {
  65   int size = m32rbf_register_size (rn);
  66   if (len != size)
  67     return -1;
  68
  69   if (rn < 16)
  70     SETTWI (buf, m32rbf_h_gr_get (current_cpu, rn));
  71   else
  72     switch (rn)
  73       {
  74       case PSW_REGNUM :
  75       case CBR_REGNUM :
  76       case SPI_REGNUM :
  77       case SPU_REGNUM :
  78       case BPC_REGNUM :
  79       case BBPSW_REGNUM :
  80       case BBPC_REGNUM :
  81         SETTWI (buf, m32rbf_h_cr_get (current_cpu,
  82                                       m32r_decode_gdb_ctrl_regnum (rn)));
  83         break;
  84       case PC_REGNUM :
  85         SETTWI (buf, m32rbf_h_pc_get (current_cpu));
  86         break;
  87       case ACCL_REGNUM :
  88         SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
  89         break;
  90       case ACCH_REGNUM :
  91         SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
  92         break;
  93       default :
  94         return 0;
  95       }
  96
  97   return size;
  98 }
  99
 100 /* The contents of BUF are in target byte order.  */
 101
 102 int
 103 m32rbf_store_register (SIM_CPU *current_cpu, int rn, const void *buf, int len)
 104 {
 105   int size = m32rbf_register_size (rn);
 106   if (len != size)
 107     return -1;
 108
 109   if (rn < 16)
 110     m32rbf_h_gr_set (current_cpu, rn, GETTWI (buf));
 111   else
 112     switch (rn)
 113       {
 114       case PSW_REGNUM :
 115       case CBR_REGNUM :
 116       case SPI_REGNUM :
 117       case SPU_REGNUM :
 118       case BPC_REGNUM :
 119       case BBPSW_REGNUM :
 120       case BBPC_REGNUM :
 121         m32rbf_h_cr_set (current_cpu,
 122                          m32r_decode_gdb_ctrl_regnum (rn),
 123                          GETTWI (buf));
 124         break;
 125       case PC_REGNUM :
 126         m32rbf_h_pc_set (current_cpu, GETTWI (buf));
 127         break;
 128       case ACCL_REGNUM :
 129         {
 130           DI val = m32rbf_h_accum_get (current_cpu);
 131           SETLODI (val, GETTWI (buf));
 132           m32rbf_h_accum_set (current_cpu, val);
 133           break;
 134         }
 135       case ACCH_REGNUM :
 136         {
 137           DI val = m32rbf_h_accum_get (current_cpu);
 138           SETHIDI (val, GETTWI (buf));
 139           m32rbf_h_accum_set (current_cpu, val);
 140           break;
 141         }
 142       default :
 143         return 0;
 144       }
 145
 146   return size;
 147 }
 148 \f
 149 USI
 150 m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
 151 {
 152   switch (cr)
 153     {
 154     case H_CR_PSW : /* psw */
 155       return (((CPU (h_bpsw) & 0xc1) << 8)
 156               | ((CPU (h_psw) & 0xc0) << 0)
 157               | GET_H_COND ());
 158     case H_CR_BBPSW : /* backup backup psw */
 159       return CPU (h_bbpsw) & 0xc1;
 160     case H_CR_CBR : /* condition bit */
 161       return GET_H_COND ();
 162     case H_CR_SPI : /* interrupt stack pointer */
 163       if (! GET_H_SM ())
 164         return CPU (h_gr[H_GR_SP]);
 165       else
 166         return CPU (h_cr[H_CR_SPI]);
 167     case H_CR_SPU : /* user stack pointer */
 168       if (GET_H_SM ())
 169         return CPU (h_gr[H_GR_SP]);
 170       else
 171         return CPU (h_cr[H_CR_SPU]);
 172     case H_CR_BPC : /* backup pc */
 173       return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
 174     case H_CR_BBPC : /* backup backup pc */
 175       return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
 176     case 4 : /* ??? unspecified, but apparently available */
 177     case 5 : /* ??? unspecified, but apparently available */
 178       return CPU (h_cr[cr]);
 179     default :
 180       return 0;
 181     }
 182 }
 183
 184 void
 185 m32rbf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
 186 {
 187   switch (cr)
 188     {
 189     case H_CR_PSW : /* psw */
 190       {
 191         int old_sm = (CPU (h_psw) & 0x80) != 0;
 192         int new_sm = (newval & 0x80) != 0;
 193         CPU (h_bpsw) = (newval >> 8) & 0xff;
 194         CPU (h_psw) = newval & 0xff;
 195         SET_H_COND (newval & 1);
 196         /* When switching stack modes, update the registers.  */
 197         if (old_sm != new_sm)
 198           {
 199             if (old_sm)
 200               {
 201                 /* Switching user -> system.  */
 202                 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
 203                 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
 204               }
 205             else
 206               {
 207                 /* Switching system -> user.  */
 208                 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
 209                 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
 210               }
 211           }
 212         break;
 213       }
 214     case H_CR_BBPSW : /* backup backup psw */
 215       CPU (h_bbpsw) = newval & 0xff;
 216       break;
 217     case H_CR_CBR : /* condition bit */
 218       SET_H_COND (newval & 1);
 219       break;
 220     case H_CR_SPI : /* interrupt stack pointer */
 221       if (! GET_H_SM ())
 222         CPU (h_gr[H_GR_SP]) = newval;
 223       else
 224         CPU (h_cr[H_CR_SPI]) = newval;
 225       break;
 226     case H_CR_SPU : /* user stack pointer */
 227       if (GET_H_SM ())
 228         CPU (h_gr[H_GR_SP]) = newval;
 229       else
 230         CPU (h_cr[H_CR_SPU]) = newval;
 231       break;
 232     case H_CR_BPC : /* backup pc */
 233       CPU (h_cr[H_CR_BPC]) = newval;
 234       break;
 235     case H_CR_BBPC : /* backup backup pc */
 236       CPU (h_cr[H_CR_BBPC]) = newval;
 237       break;
 238     case 4 : /* ??? unspecified, but apparently available */
 239     case 5 : /* ??? unspecified, but apparently available */
 240       CPU (h_cr[cr]) = newval;
 241       break;
 242     default :
 243       /* ignore */
 244       break;
 245     }
 246 }
 247
 248 /* Cover fns to access h-psw.  */
 249
 250 UQI
 251 m32rbf_h_psw_get_handler (SIM_CPU *current_cpu)
 252 {
 253   return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
 254 }
 255
 256 void
 257 m32rbf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
 258 {
 259   CPU (h_psw) = newval;
 260   CPU (h_cond) = newval & 1;
 261 }
 262
 263 /* Cover fns to access h-accum.  */
 264
 265 DI
 266 m32rbf_h_accum_get_handler (SIM_CPU *current_cpu)
 267 {
 268   /* Sign extend the top 8 bits.  */
 269   DI r;
 270 #if 1
 271   r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
 272   r = XORDI (r, MAKEDI (0x800000, 0));
 273   r = SUBDI (r, MAKEDI (0x800000, 0));
 274 #else
 275   SI hi,lo;
 276   r = CPU (h_accum);
 277   hi = GETHIDI (r);
 278   lo = GETLODI (r);
 279   hi = ((hi & 0xffffff) ^ 0x800000) - 0x800000;
 280   r = MAKEDI (hi, lo);
 281 #endif
 282   return r;
 283 }
 284
 285 void
 286 m32rbf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
 287 {
 288   CPU (h_accum) = newval;
 289 }
 290 \f
 291 #if WITH_PROFILE_MODEL_P
 292
 293 /* FIXME: Some of these should be inline or macros.  Later.  */
 294
 295 /* Initialize cycle counting for an insn.
 296    FIRST_P is non-zero if this is the first insn in a set of parallel
 297    insns.  */
 298
 299 void
 300 m32rbf_model_insn_before (SIM_CPU *cpu, int first_p)
 301 {
 302   M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
 303   mp->cti_stall = 0;
 304   mp->load_stall = 0;
 305   if (first_p)
 306     {
 307       mp->load_regs_pending = 0;
 308       mp->biggest_cycles = 0;
 309     }
 310 }
 311
 312 /* Record the cycles computed for an insn.
 313    LAST_P is non-zero if this is the last insn in a set of parallel insns,
 314    and we update the total cycle count.
 315    CYCLES is the cycle count of the insn.  */
 316
 317 void
 318 m32rbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
 319 {
 320   PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
 321   M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
 322   unsigned long total = cycles + mp->cti_stall + mp->load_stall;
 323
 324   if (last_p)
 325     {
 326       unsigned long biggest = total > mp->biggest_cycles ? total : mp->biggest_cycles;
 327       PROFILE_MODEL_TOTAL_CYCLES (p) += biggest;
 328       PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
 329     }
 330   else
 331     {
 332       /* Here we take advantage of the fact that !last_p -> first_p.  */
 333       mp->biggest_cycles = total;
 334       PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
 335     }
 336
 337   /* Branch and load stall counts are recorded independently of the
 338      total cycle count.  */
 339   PROFILE_MODEL_CTI_STALL_CYCLES (p) += mp->cti_stall;
 340   PROFILE_MODEL_LOAD_STALL_CYCLES (p) += mp->load_stall;
 341
 342   mp->load_regs = mp->load_regs_pending;
 343 }
 344
 345 static INLINE void
 346 check_load_stall (SIM_CPU *cpu, int regno)
 347 {
 348   UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
 349
 350   if (regno != -1
 351       && (h_gr & (1 << regno)) != 0)
 352     {
 353       CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
 354       if (TRACE_INSN_P (cpu))
 355         cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
 356     }
 357 }
 358
 359 int
 360 m32rbf_model_m32r_d_u_exec (SIM_CPU *cpu, const IDESC *idesc,
 361                             int unit_num, int referenced,
 362                             INT sr, INT sr2, INT dr)
 363 {
 364   check_load_stall (cpu, sr);
 365   check_load_stall (cpu, sr2);
 366   return idesc->timing->units[unit_num].done;
 367 }
 368
 369 int
 370 m32rbf_model_m32r_d_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
 371                            int unit_num, int referenced,
 372                            INT src1, INT src2)
 373 {
 374   check_load_stall (cpu, src1);
 375   check_load_stall (cpu, src2);
 376   return idesc->timing->units[unit_num].done;
 377 }
 378
 379 int
 380 m32rbf_model_m32r_d_u_mac (SIM_CPU *cpu, const IDESC *idesc,
 381                            int unit_num, int referenced,
 382                            INT src1, INT src2)
 383 {
 384   check_load_stall (cpu, src1);
 385   check_load_stall (cpu, src2);
 386   return idesc->timing->units[unit_num].done;
 387 }
 388
 389 int
 390 m32rbf_model_m32r_d_u_cti (SIM_CPU *cpu, const IDESC *idesc,
 391                            int unit_num, int referenced,
 392                            INT sr)
 393 {
 394   PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
 395   int taken_p = (referenced & (1 << 1)) != 0;
 396
 397   check_load_stall (cpu, sr);
 398   if (taken_p)
 399     {
 400       CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
 401       PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
 402     }
 403   else
 404     PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
 405   return idesc->timing->units[unit_num].done;
 406 }
 407
 408 int
 409 m32rbf_model_m32r_d_u_load (SIM_CPU *cpu, const IDESC *idesc,
 410                             int unit_num, int referenced,
 411                             INT sr, INT dr)
 412 {
 413   CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
 414   check_load_stall (cpu, sr);
 415   return idesc->timing->units[unit_num].done;
 416 }
 417
 418 int
 419 m32rbf_model_m32r_d_u_store (SIM_CPU *cpu, const IDESC *idesc,
 420                              int unit_num, int referenced,
 421                              INT src1, INT src2)
 422 {
 423   check_load_stall (cpu, src1);
 424   check_load_stall (cpu, src2);
 425   return idesc->timing->units[unit_num].done;
 426 }
 427
 428 int
 429 m32rbf_model_test_u_exec (SIM_CPU *cpu, const IDESC *idesc,
 430                           int unit_num, int referenced)
 431 {
 432   return idesc->timing->units[unit_num].done;
 433 }
 434
 435 #endif /* WITH_PROFILE_MODEL_P */