1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
2 Copyright (C) 1999-2016 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "sim-basics.h"
24 #include "sim-signal.h"
29 #include "opcode/m68hc11.h"
31 #include "gdb/callback.h"
32 #include "gdb/remote-sim.h"
33 #include "opcode/m68hc11.h"
34 #include "sim-types.h"
36 typedef unsigned8 uint8
;
37 typedef unsigned16 uint16
;
38 typedef signed16 int16
;
39 typedef unsigned32 uint32
;
40 typedef signed32 int32
;
41 typedef unsigned64 uint64
;
42 typedef signed64 int64
;
46 #include "interrupts.h"
49 /* Specifies the level of mapping for the IO, EEprom, nvram and external
50 RAM. IO registers are mapped over everything and the external RAM
51 is last (ie, it can be hidden by everything above it in the list). */
52 enum m68hc11_map_level
77 typedef struct m6811_regs
{
88 /* Description of 68HC11 IO registers. Such description is only provided
89 for the info command to display the current setting of IO registers
94 const char *short_name
;
95 const char *long_name
;
97 typedef struct io_reg_desc io_reg_desc
;
99 extern void print_io_reg_desc (SIM_DESC sd
, io_reg_desc
*desc
, int val
,
101 extern void print_io_byte (SIM_DESC sd
, const char *name
,
102 io_reg_desc
*desc
, uint8 val
, uint16 addr
);
103 extern void print_io_word (SIM_DESC sd
, const char *name
,
104 io_reg_desc
*desc
, uint16 val
, uint16 addr
);
107 /* List of special 68HC11&68HC12 instructions that are not handled by the
108 'gencode.c' generator. These complex instructions are implemented
112 /* 68HC11 instructions. */
122 /* 68HC12 instructions. */
141 #define M6811_MAX_PORTS (0x03f+1)
142 #define M6812_MAX_PORTS (0x3ff+1)
143 #define MAX_PORTS (M6812_MAX_PORTS)
147 typedef void (* cpu_interp
) (struct _sim_cpu
*);
151 struct m6811_regs cpu_regs
;
153 /* CPU interrupts. */
154 struct interrupts cpu_interrupts
;
156 /* Pointer to the interpretor routine. */
157 cpu_interp cpu_interpretor
;
159 /* Pointer to the architecture currently configured in the simulator. */
160 const struct bfd_arch_info
*cpu_configured_arch
;
162 /* CPU absolute cycle time. The cycle time is updated after
163 each instruction, by the number of cycles taken by the instruction.
164 It is cleared only when reset occurs. */
165 signed64 cpu_absolute_cycle
;
167 /* Number of cycles to increment after the current instruction.
168 This is also the number of ticks for the generic event scheduler. */
169 uint8 cpu_current_cycle
;
170 int cpu_emul_syscall
;
171 int cpu_is_initialized
;
173 int cpu_check_memory
;
174 int cpu_stop_on_interrupt
;
176 /* When this is set, start execution of program at address specified
177 in the ELF header. This is used for testing some programs that do not
178 have an interrupt table linked with them. Programs created during the
179 GCC validation are like this. A normal 68HC11 does not behave like
180 this (unless there is some OS or downloadable feature). */
181 int cpu_use_elf_start
;
183 /* The starting address specified in ELF header. */
188 /* CPU frequency. This is the quartz frequency. It is divided by 4 to
189 get the cycle time. This is used for the timer rate and for the baud
191 unsigned long cpu_frequency
;
193 /* The mode in which the CPU is configured (MODA and MODB pins). */
194 unsigned int cpu_mode
;
195 const char* cpu_start_mode
;
197 /* The cpu being configured. */
198 enum cpu_type cpu_type
;
200 /* Initial value of the CONFIG register. */
202 uint8 cpu_use_local_config
;
204 uint8 ios
[MAX_PORTS
];
206 /* Memory bank parameters which describe how the memory bank window
207 is mapped in memory and how to convert it in virtual address. */
210 address_word bank_virtual
;
216 /* ... base type ... */
220 /* Returns the cpu absolute cycle time (A virtual counter incremented
221 at each 68HC11 E clock). */
222 #define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
223 #define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
224 #define cpu_is_running(PROC) ((PROC)->cpu_running)
226 /* Get the IO/RAM base addresses depending on the M6811_INIT register. */
227 #define cpu_get_io_base(PROC) \
228 (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
229 #define cpu_get_reg_base(PROC) \
230 (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
232 /* Returns the different CPU registers. */
233 #define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
234 #define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
235 #define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
236 #define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
237 #define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
238 #define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
239 #define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
240 #define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
241 #define cpu_get_page(PROC) ((PROC)->cpu_regs.page)
243 /* 68HC12 specific and Motorola internal registers. */
244 #define cpu_get_tmp3(PROC) (0)
245 #define cpu_get_tmp2(PROC) (0)
247 #define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
248 #define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
249 #define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
250 #define cpu_set_page(PROC,VAL) (((PROC)->cpu_regs.page) = (VAL))
252 /* 68HC12 specific and Motorola internal registers. */
253 #define cpu_set_tmp3(PROC,VAL) (0)
254 #define cpu_set_tmp2(PROC,VAL) (void) (0)
257 /* This is a function in m68hc11_sim.c to keep track of the frame. */
258 #define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
261 #define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
263 #define cpu_set_a(PROC,VAL) \
264 cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
265 #define cpu_set_b(PROC,VAL) \
266 cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
268 #define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
269 #define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
270 #define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
271 #define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
272 #define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
273 #define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
274 #define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
275 #define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
276 #define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
278 #define cpu_set_ccr_flag(S,B,V) \
279 cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
281 #define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
282 #define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
283 #define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
284 #define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
285 #define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
286 #define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
287 #define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
288 #define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
291 #define inline static __inline__
293 extern void cpu_memory_exception (struct _sim_cpu
*proc
,
296 const char *message
);
299 phys_to_virt (sim_cpu
*cpu
, address_word addr
)
301 if (addr
>= cpu
->bank_start
&& addr
< cpu
->bank_end
)
302 return ((address_word
) (addr
- cpu
->bank_start
)
303 + (((address_word
) cpu
->cpu_regs
.page
) << cpu
->bank_shift
)
304 + cpu
->bank_virtual
);
306 return (address_word
) (addr
);
310 memory_read8 (sim_cpu
*cpu
, uint16 addr
)
314 if (sim_core_read_buffer (CPU_STATE (cpu
), cpu
, 0, &val
, addr
, 1) != 1)
316 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
323 memory_write8 (sim_cpu
*cpu
, uint16 addr
, uint8 val
)
325 if (sim_core_write_buffer (CPU_STATE (cpu
), cpu
, 0, &val
, addr
, 1) != 1)
327 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
333 memory_read16 (sim_cpu
*cpu
, uint16 addr
)
337 if (sim_core_read_buffer (CPU_STATE (cpu
), cpu
, 0, b
, addr
, 2) != 2)
339 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
342 return (((uint16
) (b
[0])) << 8) | ((uint16
) b
[1]);
346 memory_write16 (sim_cpu
*cpu
, uint16 addr
, uint16 val
)
352 if (sim_core_write_buffer (CPU_STATE (cpu
), cpu
, 0, b
, addr
, 2) != 2)
354 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
359 cpu_ccr_update_tst8 (sim_cpu
*proc
, uint8 val
);
362 cpu_ccr_update_tst16 (sim_cpu
*proc
, uint16 val
)
364 cpu_set_ccr_V (proc
, 0);
365 cpu_set_ccr_N (proc
, val
& 0x8000 ? 1 : 0);
366 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
370 cpu_ccr_update_shift8 (sim_cpu
*proc
, uint8 val
)
372 cpu_set_ccr_N (proc
, val
& 0x80 ? 1 : 0);
373 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
374 cpu_set_ccr_V (proc
, cpu_get_ccr_N (proc
) ^ cpu_get_ccr_C (proc
));
378 cpu_ccr_update_shift16 (sim_cpu
*proc
, uint16 val
)
380 cpu_set_ccr_N (proc
, val
& 0x8000 ? 1 : 0);
381 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
382 cpu_set_ccr_V (proc
, cpu_get_ccr_N (proc
) ^ cpu_get_ccr_C (proc
));
386 cpu_ccr_update_add8 (sim_cpu
*proc
, uint8 r
, uint8 a
, uint8 b
)
388 cpu_set_ccr_C (proc
, ((a
& b
) | (b
& ~r
) | (a
& ~r
)) & 0x80 ? 1 : 0);
389 cpu_set_ccr_V (proc
, ((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x80 ? 1 : 0);
390 cpu_set_ccr_Z (proc
, r
== 0);
391 cpu_set_ccr_N (proc
, r
& 0x80 ? 1 : 0);
396 cpu_ccr_update_sub8 (sim_cpu
*proc
, uint8 r
, uint8 a
, uint8 b
)
398 cpu_set_ccr_C (proc
, ((~a
& b
) | (b
& r
) | (~a
& r
)) & 0x80 ? 1 : 0);
399 cpu_set_ccr_V (proc
, ((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x80 ? 1 : 0);
400 cpu_set_ccr_Z (proc
, r
== 0);
401 cpu_set_ccr_N (proc
, r
& 0x80 ? 1 : 0);
405 cpu_ccr_update_add16 (sim_cpu
*proc
, uint16 r
, uint16 a
, uint16 b
)
407 cpu_set_ccr_C (proc
, ((a
& b
) | (b
& ~r
) | (a
& ~r
)) & 0x8000 ? 1 : 0);
408 cpu_set_ccr_V (proc
, ((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x8000 ? 1 : 0);
409 cpu_set_ccr_Z (proc
, r
== 0);
410 cpu_set_ccr_N (proc
, r
& 0x8000 ? 1 : 0);
414 cpu_ccr_update_sub16 (sim_cpu
*proc
, uint16 r
, uint16 a
, uint16 b
)
416 cpu_set_ccr_C (proc
, ((~a
& b
) | (b
& r
) | (~a
& r
)) & 0x8000 ? 1 : 0);
417 cpu_set_ccr_V (proc
, ((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x8000 ? 1 : 0);
418 cpu_set_ccr_Z (proc
, r
== 0);
419 cpu_set_ccr_N (proc
, r
& 0x8000 ? 1 : 0);
422 /* Push and pop instructions for 68HC11 (next-available stack mode). */
424 cpu_m68hc11_push_uint8 (sim_cpu
*proc
, uint8 val
)
426 uint16 addr
= proc
->cpu_regs
.sp
;
428 memory_write8 (proc
, addr
, val
);
429 proc
->cpu_regs
.sp
= addr
- 1;
433 cpu_m68hc11_push_uint16 (sim_cpu
*proc
, uint16 val
)
435 uint16 addr
= proc
->cpu_regs
.sp
- 1;
437 memory_write16 (proc
, addr
, val
);
438 proc
->cpu_regs
.sp
= addr
- 1;
442 cpu_m68hc11_pop_uint8 (sim_cpu
*proc
)
444 uint16 addr
= proc
->cpu_regs
.sp
;
447 val
= memory_read8 (proc
, addr
+ 1);
448 proc
->cpu_regs
.sp
= addr
+ 1;
453 cpu_m68hc11_pop_uint16 (sim_cpu
*proc
)
455 uint16 addr
= proc
->cpu_regs
.sp
;
458 val
= memory_read16 (proc
, addr
+ 1);
459 proc
->cpu_regs
.sp
= addr
+ 2;
463 /* Push and pop instructions for 68HC12 (last-used stack mode). */
465 cpu_m68hc12_push_uint8 (sim_cpu
*proc
, uint8 val
)
467 uint16 addr
= proc
->cpu_regs
.sp
;
470 memory_write8 (proc
, addr
, val
);
471 proc
->cpu_regs
.sp
= addr
;
475 cpu_m68hc12_push_uint16 (sim_cpu
*proc
, uint16 val
)
477 uint16 addr
= proc
->cpu_regs
.sp
;
480 memory_write16 (proc
, addr
, val
);
481 proc
->cpu_regs
.sp
= addr
;
485 cpu_m68hc12_pop_uint8 (sim_cpu
*proc
)
487 uint16 addr
= proc
->cpu_regs
.sp
;
490 val
= memory_read8 (proc
, addr
);
491 proc
->cpu_regs
.sp
= addr
+ 1;
496 cpu_m68hc12_pop_uint16 (sim_cpu
*proc
)
498 uint16 addr
= proc
->cpu_regs
.sp
;
501 val
= memory_read16 (proc
, addr
);
502 proc
->cpu_regs
.sp
= addr
+ 2;
506 /* Fetch a 8/16 bit value and update the PC. */
508 cpu_fetch8 (sim_cpu
*proc
)
510 uint16 addr
= proc
->cpu_regs
.pc
;
513 val
= memory_read8 (proc
, addr
);
514 proc
->cpu_regs
.pc
= addr
+ 1;
519 cpu_fetch16 (sim_cpu
*proc
)
521 uint16 addr
= proc
->cpu_regs
.pc
;
524 val
= memory_read16 (proc
, addr
);
525 proc
->cpu_regs
.pc
= addr
+ 2;
529 extern void cpu_call (sim_cpu
* proc
, uint16 addr
);
530 extern void cpu_exg (sim_cpu
* proc
, uint8 code
);
531 extern void cpu_dbcc (sim_cpu
* proc
);
532 extern void cpu_special (sim_cpu
*proc
, enum M6811_Special special
);
533 extern void cpu_move8 (sim_cpu
*proc
, uint8 op
);
534 extern void cpu_move16 (sim_cpu
*proc
, uint8 op
);
536 extern uint16
cpu_fetch_relbranch (sim_cpu
*proc
);
537 extern uint16
cpu_fetch_relbranch16 (sim_cpu
*proc
);
538 extern void cpu_push_all (sim_cpu
*proc
);
539 extern void cpu_single_step (sim_cpu
*proc
);
541 extern void cpu_info (SIM_DESC sd
, sim_cpu
*proc
);
543 extern int cpu_initialize (SIM_DESC sd
, sim_cpu
*cpu
);
545 /* Returns the address of a 68HC12 indexed operand.
546 Pre and post modifications are handled on the source register. */
547 extern uint16
cpu_get_indexed_operand_addr (sim_cpu
*cpu
, int restricted
);
549 extern void cpu_return (sim_cpu
*cpu
);
550 extern void cpu_set_sp (sim_cpu
*cpu
, uint16 val
);
551 extern int cpu_reset (sim_cpu
*cpu
);
552 extern int cpu_restart (sim_cpu
*cpu
);
553 extern void sim_memory_error (sim_cpu
*cpu
, SIM_SIGNAL excep
,
554 uint16 addr
, const char *message
, ...);
555 extern void emul_os (int op
, sim_cpu
*cpu
);
556 extern void cpu_interp_m6811 (sim_cpu
*cpu
);
557 extern void cpu_interp_m6812 (sim_cpu
*cpu
);
559 extern int m68hc11cpu_set_oscillator (SIM_DESC sd
, const char *port
,
560 double ton
, double toff
,
562 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd
, const char *port
);
563 extern void m68hc11cpu_set_port (struct hw
*me
, sim_cpu
*cpu
,
564 unsigned addr
, uint8 val
);
566 /* The current state of the processor; registers, memory, etc. */
569 sim_cpu
*cpu
[MAX_NR_PROCESSORS
];
573 extern void sim_board_reset (SIM_DESC sd
);
575 #define PRINT_TIME 0x01
576 #define PRINT_CYCLE 0x02
577 extern const char *cycle_to_string (sim_cpu
*cpu
, signed64 t
, int flags
);