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git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/mcore/sim-main.h
1 /* Simulator for Motorola's MCore processor
2 Copyright (C) 2009-2021 Free Software Foundation, Inc.
4 This file is part of GDB, the GNU debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #define SIM_HAVE_COMMON_SIM_STATE
24 #include "sim-basics.h"
26 typedef long int word
;
27 typedef unsigned long int uword
;
33 This state is maintained in host byte order. The
34 fetch/store register functions must translate between host
35 byte order and the target processor byte order.
36 Keeping this data in target byte order simplifies the register
37 read/write functions. Keeping this data in native order improves
38 the performance of the simulator. Simulation speed is deemed more
41 /* The ordering of the mcore_regset structure is matched in the
42 gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
45 word gregs
[16]; /* primary registers */
46 word alt_gregs
[16]; /* alt register file */
47 word cregs
[32]; /* control registers */
50 #define LAST_VALID_CREG 32 /* only 0..12 implemented */
51 #define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
57 struct mcore_regset regs
;
58 /* Used by the fetch/store reg helpers to access registers linearly. */
59 word asints
[NUM_MCORE_REGS
];
62 /* Used to switch between gregs/alt_gregs based on the control state. */