1 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
3 * configure: Regenerated to track ../common/aclocal.m4 changes.
5 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
7 * configure: Regenerated to track ../common/aclocal.m4 changes.
10 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
12 * acconfig.h: New file.
13 * configure.in: Reverted change of Apr 24; use sinclude again.
15 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
17 * configure: Regenerated to track ../common/aclocal.m4 changes.
20 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
22 * configure.in: Don't call sinclude.
24 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
26 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
28 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
30 * mips.igen (ERET): Implement.
32 * interp.c (decode_coproc): Return sign-extended EPC.
34 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
36 * interp.c (signal_exception): Do not ignore Trap.
37 (signal_exception): On TRAP, restart at exception address.
38 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
39 (signal_exception): Update.
40 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
41 so that TRAP instructions are caught.
43 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
45 * sim-main.h (struct hilo_access, struct hilo_history): Define,
46 contains HI/LO access history.
47 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
48 (HIACCESS, LOACCESS): Delete, replace with
49 (HIHISTORY, LOHISTORY): New macros.
50 (start-sanitize-r5900):
51 (struct sim_5900_cpu): Make hi1access, lo1access of type
53 (HI1ACCESS, LO1ACCESS): Delete, replace with
54 (HI1HISTORY, LO1HISTORY): New macros.
56 (CHECKHILO): Delete all, moved to mips.igen
58 * gencode.c (build_instruction): Do not generate checks for
59 correct HI/LO register usage.
61 * interp.c (old_engine_run): Delete checks for correct HI/LO
64 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
65 check_mf_cycles): New functions.
66 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
67 do_divu, domultx, do_mult, do_multu): Use.
69 * tx.igen ("madd", "maddu"): Use.
70 (start-sanitize-r5900):
72 r5900.igen: Update all HI/LO checks.
73 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
74 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
75 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
76 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
77 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
82 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
84 * interp.c (decode_coproc): Correct CMFC2/QMTC2
87 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
88 instead of a single 128-bit access.
92 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
94 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
95 * interp.c (cop_[ls]q): Fixes corresponding to above.
99 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
101 * interp.c (decode_coproc): Adapt COP2 micro interlock to
102 clarified specs. Reset "M" bit; exit also on "E" bit.
106 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
108 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
109 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
111 * r5900.igen (r59fp_unpack): New function.
112 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
113 RSQRT.S, SQRT.S): Use.
114 (r59fp_zero): New function.
115 (r59fp_overflow): Generate r5900 specific overflow value.
116 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
118 (CVT.S.W, CVT.W.S): Exchange implementations.
120 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
124 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
126 * configure.in (tx19, sim_use_gen): Switch to igen.
127 * configure: Re-build.
131 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
133 * interp.c (decode_coproc): Make COP2 branch code compile after
134 igen signature changes.
137 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
139 * mips.igen (DSRAV): Use function do_dsrav.
140 (SRAV): Use new function do_srav.
142 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
143 (B): Sign extend 11 bit immediate.
144 (EXT-B*): Shift 16 bit immediate left by 1.
145 (ADDIU*): Don't sign extend immediate value.
147 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
149 * m16run.c (sim_engine_run): Restore CIA after handling an event.
152 * mips.igen (mtc0): Valid tx19 instruction.
155 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
158 * mips.igen (delayslot32, nullify_next_insn): New functions.
159 (m16.igen): Always include.
160 (do_*): Add more tracing.
162 * m16.igen (delayslot16): Add NIA argument, could be called by a
163 32 bit MIPS16 instruction.
165 * interp.c (ifetch16): Move function from here.
166 * sim-main.c (ifetch16): To here.
168 * sim-main.c (ifetch16, ifetch32): Update to match current
169 implementations of LH, LW.
170 (signal_exception): Don't print out incorrect hex value of illegal
173 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
175 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
178 * m16.igen: Implement MIPS16 instructions.
180 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
181 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
182 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
183 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
184 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
185 bodies of corresponding code from 32 bit insn to these. Also used
186 by MIPS16 versions of functions.
188 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
189 (IMEM16): Drop NR argument from macro.
192 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
194 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
195 of VU lower instruction.
199 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
201 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
204 * sim-main.h: Removed attempt at allowing 128-bit access.
208 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
210 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
212 * interp.c (decode_coproc): Refer to VU CIA as a "special"
213 register, not as a "misc" register. Aha. Add activity
214 assertions after VCALLMS* instructions.
218 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
220 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
221 to upper code of generated VU instruction.
225 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
227 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
229 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
232 * r5900.igen (SQC2): Thinko.
236 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
238 * interp.c (*): Adapt code to merged VU device & state structs.
239 (decode_coproc): Execute COP2 each macroinstruction without
240 pipelining, by stepping VU to completion state. Adapted to
241 read_vu_*_reg style of register access.
243 * mips.igen ([SL]QC2): Removed these COP2 instructions.
245 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
247 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
250 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
252 * Makefile.in (SIM_OBJS): Add sim-main.o.
254 * sim-main.h (address_translation, load_memory, store_memory,
255 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
257 (pr_addr, pr_uword64): Declare.
258 (sim-main.c): Include when H_REVEALS_MODULE_P.
260 * interp.c (address_translation, load_memory, store_memory,
261 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
263 * sim-main.c: To here. Fix compilation problems.
265 * configure.in: Enable inlining.
266 * configure: Re-config.
268 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
270 * configure: Regenerated to track ../common/aclocal.m4 changes.
272 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
274 * mips.igen: Include tx.igen.
275 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
276 * tx.igen: New file, contains MADD and MADDU.
278 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
279 the hardwired constant `7'.
280 (store_memory): Ditto.
281 (LOADDRMASK): Move definition to sim-main.h.
283 mips.igen (MTC0): Enable for r3900.
286 mips.igen (do_load_byte): Delete.
287 (do_load, do_store, do_load_left, do_load_write, do_store_left,
288 do_store_right): New functions.
289 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
291 configure.in: Let the tx39 use igen again.
294 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
296 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
297 not an address sized quantity. Return zero for cache sizes.
299 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
301 * mips.igen (r3900): r3900 does not support 64 bit integer
305 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
307 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
311 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
313 * interp.c (decode_coproc): Continuing COP2 work.
314 (cop_[ls]q): Make sky-target-only.
316 * sim-main.h (COP_[LS]Q): Make sky-target-only.
318 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
320 * configure.in (mipstx39*-*-*): Use gencode simulator rather
322 * configure : Rebuild.
325 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
327 * interp.c (decode_coproc): Added a missing TARGET_SKY check
328 around COP2 implementation skeleton.
332 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
334 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
336 * interp.c (sim_{load,store}_register): Use new vu[01]_device
337 static to access VU registers.
338 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
339 decoding. Work in progress.
341 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
342 overlapping/redundant bit pattern.
343 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
346 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
349 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
350 access to coprocessor registers.
352 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
354 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
356 * configure: Regenerated to track ../common/aclocal.m4 changes.
358 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
360 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
362 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
364 * configure: Regenerated to track ../common/aclocal.m4 changes.
365 * config.in: Regenerated to track ../common/aclocal.m4 changes.
367 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
369 * configure: Regenerated to track ../common/aclocal.m4 changes.
371 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
373 * interp.c (Max, Min): Comment out functions. Not yet used.
375 start-sanitize-vr4320
376 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
378 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
381 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
383 * configure: Regenerated to track ../common/aclocal.m4 changes.
385 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
387 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
388 configurable settings for stand-alone simulator.
391 * configure.in: Added --with-sim-gpu2 option to specify path of
392 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
393 links/compiles stand-alone simulator with this library.
395 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
397 * configure.in: Added X11 search, just in case.
399 * configure: Regenerated.
401 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
403 * interp.c (sim_write, sim_read, load_memory, store_memory):
404 Replace sim_core_*_map with read_map, write_map, exec_map resp.
406 start-sanitize-vr4320
407 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
409 * vr4320.igen (clz,dclz) : Added.
410 (dmac): Replaced 99, with LO.
413 start-sanitize-vr5400
414 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
416 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
419 start-sanitize-vr4320
420 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
422 * vr4320.igen: New file.
423 * Makefile.in (vr4320.igen) : Added.
424 * configure.in (mips64vr4320-*-*): Added.
425 * configure : Rebuilt.
426 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
427 Add the vr4320 model entry and mark the vr4320 insn as necessary.
430 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
432 * sim-main.h (GETFCC): Return an unsigned value.
435 * r5900.igen: Use an unsigned array index variable `i'.
436 (QFSRV): Ditto for variable bytes.
439 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
441 * mips.igen (DIV): Fix check for -1 / MIN_INT.
442 (DADD): Result destination is RD not RT.
445 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
446 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
450 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
452 * sim-main.h (HIACCESS, LOACCESS): Always define.
454 * mdmx.igen (Maxi, Mini): Rename Max, Min.
456 * interp.c (sim_info): Delete.
458 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
460 * interp.c (DECLARE_OPTION_HANDLER): Use it.
461 (mips_option_handler): New argument `cpu'.
462 (sim_open): Update call to sim_add_option_table.
464 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
466 * mips.igen (CxC1): Add tracing.
469 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
471 * r5900.igen (StoreFP): Delete.
472 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
474 (rsqrt.s, sqrt.s): Implement.
475 (r59cond): New function.
476 (C.COND.S): Call r59cond in assembler line.
477 (cvt.w.s, cvt.s.w): Implement.
479 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
482 * sim-main.h: Define an enum of r5900 FCSR bit fields.
486 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
488 * r5900.igen: Add tracing to all p* instructions.
490 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
492 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
493 to get gdb talking to re-aranged sim_cpu register structure.
496 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
498 * sim-main.h (Max, Min): Declare.
500 * interp.c (Max, Min): New functions.
502 * mips.igen (BC1): Add tracing.
504 start-sanitize-vr5400
505 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
507 * mdmx.igen: Tag all functions as requiring either with mdmx or
512 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
514 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
516 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
518 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
520 * r5900.igen: Rewrite.
522 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
524 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
525 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
528 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
530 * interp.c Added memory map for stack in vr4100
532 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
534 * interp.c (load_memory): Add missing "break"'s.
536 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
538 * interp.c (sim_store_register, sim_fetch_register): Pass in
539 length parameter. Return -1.
541 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
543 * interp.c: Added hardware init hook, fixed warnings.
545 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
547 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
549 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
551 * interp.c (ifetch16): New function.
553 * sim-main.h (IMEM32): Rename IMEM.
554 (IMEM16_IMMED): Define.
556 (DELAY_SLOT): Update.
558 * m16run.c (sim_engine_run): New file.
560 * m16.igen: All instructions except LB.
561 (LB): Call do_load_byte.
562 * mips.igen (do_load_byte): New function.
563 (LB): Call do_load_byte.
565 * mips.igen: Move spec for insn bit size and high bit from here.
566 * Makefile.in (tmp-igen, tmp-m16): To here.
568 * m16.dc: New file, decode mips16 instructions.
570 * Makefile.in (SIM_NO_ALL): Define.
571 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
574 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
578 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
580 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
581 point unit to 32 bit registers.
582 * configure: Re-generate.
584 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
586 * configure.in (sim_use_gen): Make IGEN the default simulator
587 generator for generic 32 and 64 bit mips targets.
588 * configure: Re-generate.
590 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
592 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
595 * interp.c (sim_fetch_register, sim_store_register): Read/write
596 FGR from correct location.
597 (sim_open): Set size of FGR's according to
598 WITH_TARGET_FLOATING_POINT_BITSIZE.
600 * sim-main.h (FGR): Store floating point registers in a separate
603 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
605 * configure: Regenerated to track ../common/aclocal.m4 changes.
607 start-sanitize-vr5400
608 * mdmx.igen: Mark all instructions as 64bit/fp specific.
611 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
613 * interp.c (ColdReset): Call PENDING_INVALIDATE.
615 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
617 * interp.c (pending_tick): New function. Deliver pending writes.
619 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
620 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
621 it can handle mixed sized quantites and single bits.
623 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
625 * interp.c (oengine.h): Do not include when building with IGEN.
626 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
627 (sim_info): Ditto for PROCESSOR_64BIT.
628 (sim_monitor): Replace ut_reg with unsigned_word.
629 (*): Ditto for t_reg.
630 (LOADDRMASK): Define.
631 (sim_open): Remove defunct check that host FP is IEEE compliant,
632 using software to emulate floating point.
633 (value_fpr, ...): Always compile, was conditional on HASFPU.
635 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
637 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
640 * interp.c (SD, CPU): Define.
641 (mips_option_handler): Set flags in each CPU.
642 (interrupt_event): Assume CPU 0 is the one being iterrupted.
643 (sim_close): Do not clear STATE, deleted anyway.
644 (sim_write, sim_read): Assume CPU zero's vm should be used for
646 (sim_create_inferior): Set the PC for all processors.
647 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
649 (mips16_entry): Pass correct nr of args to store_word, load_word.
650 (ColdReset): Cold reset all cpu's.
651 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
652 (sim_monitor, load_memory, store_memory, signal_exception): Use
653 `CPU' instead of STATE_CPU.
656 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
659 * sim-main.h (signal_exception): Add sim_cpu arg.
660 (SignalException*): Pass both SD and CPU to signal_exception.
661 * interp.c (signal_exception): Update.
663 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
665 (sync_operation, prefetch, cache_op, store_memory, load_memory,
666 address_translation): Ditto
667 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
669 start-sanitize-vr5400
670 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
672 (ByteAlign): Use StoreFPR, pass args in correct order.
676 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
678 * configure.in (sim_igen_filter): For r5900, configure as SMP.
681 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
683 * configure: Regenerated to track ../common/aclocal.m4 changes.
685 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
688 * configure.in (sim_igen_filter): For r5900, use igen.
689 * configure: Re-generate.
692 * interp.c (sim_engine_run): Add `nr_cpus' argument.
694 * mips.igen (model): Map processor names onto BFD name.
696 * sim-main.h (CPU_CIA): Delete.
697 (SET_CIA, GET_CIA): Define
699 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
701 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
704 * configure.in (default_endian): Configure a big-endian simulator
706 * configure: Re-generate.
708 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
710 * configure: Regenerated to track ../common/aclocal.m4 changes.
712 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
714 * interp.c (sim_monitor): Handle Densan monitor outbyte
715 and inbyte functions.
717 1997-12-29 Felix Lee <flee@cygnus.com>
719 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
721 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
723 * Makefile.in (tmp-igen): Arrange for $zero to always be
724 reset to zero after every instruction.
726 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
728 * configure: Regenerated to track ../common/aclocal.m4 changes.
731 start-sanitize-vr5400
732 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
734 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
738 start-sanitize-vr5400
739 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
741 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
742 vr5400 with the vr5000 as the default.
745 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
747 * mips.igen (MSUB): Fix to work like MADD.
748 * gencode.c (MSUB): Similarly.
750 start-sanitize-vr5400
751 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
753 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
757 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
759 * configure: Regenerated to track ../common/aclocal.m4 changes.
761 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
763 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
765 start-sanitize-vr5400
766 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
767 (value_cc, store_cc): Implement.
769 * sim-main.h: Add 8*3*8 bit accumulator.
771 * vr5400.igen: Move mdmx instructins from here
772 * mdmx.igen: To here - new file. Add/fix missing instructions.
773 * mips.igen: Include mdmx.igen.
774 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
777 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
779 * sim-main.h (sim-fpu.h): Include.
781 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
782 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
783 using host independant sim_fpu module.
785 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
787 * interp.c (signal_exception): Report internal errors with SIGABRT
790 * sim-main.h (C0_CONFIG): New register.
791 (signal.h): No longer include.
793 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
795 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
797 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
799 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
801 * mips.igen: Tag vr5000 instructions.
802 (ANDI): Was missing mipsIV model, fix assembler syntax.
803 (do_c_cond_fmt): New function.
804 (C.cond.fmt): Handle mips I-III which do not support CC field
806 (bc1): Handle mips IV which do not have a delaed FCC separatly.
807 (SDR): Mask paddr when BigEndianMem, not the converse as specified
809 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
810 vr5000 which saves LO in a GPR separatly.
812 * configure.in (enable-sim-igen): For vr5000, select vr5000
813 specific instructions.
814 * configure: Re-generate.
816 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
818 * Makefile.in (SIM_OBJS): Add sim-fpu module.
820 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
821 fmt_uninterpreted_64 bit cases to switch. Convert to
824 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
826 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
827 as specified in IV3.2 spec.
828 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
830 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
832 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
833 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
834 (start-sanitize-r5900):
835 (LWXC1, SWXC1): Delete from r5900 instruction set.
836 (end-sanitize-r5900):
837 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
838 PENDING_FILL versions of instructions. Simplify.
840 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
842 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
844 (MTHI, MFHI): Disable code checking HI-LO.
846 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
848 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
850 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
852 * gencode.c (build_mips16_operands): Replace IPC with cia.
854 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
855 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
857 (UndefinedResult): Replace function with macro/function
859 (sim_engine_run): Don't save PC in IPC.
861 * sim-main.h (IPC): Delete.
863 start-sanitize-vr5400
864 * vr5400.igen (vr): Add missing cia argument to value_fpr.
865 (do_select): Rename function select.
868 * interp.c (signal_exception, store_word, load_word,
869 address_translation, load_memory, store_memory, cache_op,
870 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
871 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
872 current instruction address - cia - argument.
873 (sim_read, sim_write): Call address_translation directly.
874 (sim_engine_run): Rename variable vaddr to cia.
875 (signal_exception): Pass cia to sim_monitor
877 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
878 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
879 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
881 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
882 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
885 * interp.c (signal_exception): Pass restart address to
888 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
889 idecode.o): Add dependency.
891 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
893 (DELAY_SLOT): Update NIA not PC with branch address.
894 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
896 * mips.igen: Use CIA not PC in branch calculations.
897 (illegal): Call SignalException.
898 (BEQ, ADDIU): Fix assembler.
900 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
902 * m16.igen (JALX): Was missing.
904 * configure.in (enable-sim-igen): New configuration option.
905 * configure: Re-generate.
907 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
909 * interp.c (load_memory, store_memory): Delete parameter RAW.
910 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
911 bypassing {load,store}_memory.
913 * sim-main.h (ByteSwapMem): Delete definition.
915 * Makefile.in (SIM_OBJS): Add sim-memopt module.
917 * interp.c (sim_do_command, sim_commands): Delete mips specific
918 commands. Handled by module sim-options.
920 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
921 (WITH_MODULO_MEMORY): Define.
923 * interp.c (sim_info): Delete code printing memory size.
925 * interp.c (mips_size): Nee sim_size, delete function.
927 (monitor, monitor_base, monitor_size): Delete global variables.
928 (sim_open, sim_close): Delete code creating monitor and other
929 memory regions. Use sim-memopts module, via sim_do_commandf, to
930 manage memory regions.
931 (load_memory, store_memory): Use sim-core for memory model.
933 * interp.c (address_translation): Delete all memory map code
934 except line forcing 32 bit addresses.
936 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
938 * sim-main.h (WITH_TRACE): Delete definition. Enables common
941 * interp.c (logfh, logfile): Delete globals.
942 (sim_open, sim_close): Delete code opening & closing log file.
943 (mips_option_handler): Delete -l and -n options.
944 (OPTION mips_options): Ditto.
946 * interp.c (OPTION mips_options): Rename option trace to dinero.
947 (mips_option_handler): Update.
949 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
951 * interp.c (fetch_str): New function.
952 (sim_monitor): Rewrite using sim_read & sim_write.
953 (sim_open): Check magic number.
954 (sim_open): Write monitor vectors into memory using sim_write.
955 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
956 (sim_read, sim_write): Simplify - transfer data one byte at a
958 (load_memory, store_memory): Clarify meaning of parameter RAW.
960 * sim-main.h (isHOST): Defete definition.
961 (isTARGET): Mark as depreciated.
962 (address_translation): Delete parameter HOST.
964 * interp.c (address_translation): Delete parameter HOST.
967 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
969 * gencode.c: Add tx49 configury and insns.
970 * configure.in: Add tx49 configury.
974 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
978 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
979 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
981 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
983 * mips.igen: Add model filter field to records.
985 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
987 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
989 interp.c (sim_engine_run): Do not compile function sim_engine_run
992 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
995 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
996 igen. Replace with configuration variables sim_igen_flags /
1000 * r5900.igen: New file. Copy r5900 insns here.
1002 start-sanitize-vr5400
1003 * vr5400.igen: New file.
1005 * m16.igen: New file. Copy mips16 insns here.
1006 * mips.igen: From here.
1008 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1010 start-sanitize-vr5400
1011 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1013 * configure.in: Add mips64vr5400 target.
1014 * configure: Re-generate.
1017 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1019 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1021 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1023 * gencode.c (build_instruction): Follow sim_write's lead in using
1024 BigEndianMem instead of !ByteSwapMem.
1026 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1028 * configure.in (sim_gen): Dependent on target, select type of
1029 generator. Always select old style generator.
1031 configure: Re-generate.
1033 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1035 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1036 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1037 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1038 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1039 SIM_@sim_gen@_*, set by autoconf.
1041 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1043 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1045 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1046 CURRENT_FLOATING_POINT instead.
1048 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1049 (address_translation): Raise exception InstructionFetch when
1050 translation fails and isINSTRUCTION.
1052 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1053 sim_engine_run): Change type of of vaddr and paddr to
1055 (address_translation, prefetch, load_memory, store_memory,
1056 cache_op): Change type of vAddr and pAddr to address_word.
1058 * gencode.c (build_instruction): Change type of vaddr and paddr to
1061 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1063 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1064 macro to obtain result of ALU op.
1066 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1068 * interp.c (sim_info): Call profile_print.
1070 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1072 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1074 * sim-main.h (WITH_PROFILE): Do not define, defined in
1075 common/sim-config.h. Use sim-profile module.
1076 (simPROFILE): Delete defintion.
1078 * interp.c (PROFILE): Delete definition.
1079 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1080 (sim_close): Delete code writing profile histogram.
1081 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1083 (sim_engine_run): Delete code profiling the PC.
1085 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1087 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1089 * interp.c (sim_monitor): Make register pointers of type
1092 * sim-main.h: Make registers of type unsigned_word not
1095 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1097 start-sanitize-r5900
1098 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1099 ...): Move to sim-main.h
1102 * interp.c (sync_operation): Rename from SyncOperation, make
1103 global, add SD argument.
1104 (prefetch): Rename from Prefetch, make global, add SD argument.
1105 (decode_coproc): Make global.
1107 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1109 * gencode.c (build_instruction): Generate DecodeCoproc not
1110 decode_coproc calls.
1112 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1113 (SizeFGR): Move to sim-main.h
1114 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1115 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1116 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1118 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1119 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1120 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1121 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1122 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1123 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1125 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1127 (sim-alu.h): Include.
1128 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1129 (sim_cia): Typedef to instruction_address.
1131 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1133 * Makefile.in (interp.o): Rename generated file engine.c to
1138 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1140 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1142 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1144 * gencode.c (build_instruction): For "FPSQRT", output correct
1145 number of arguments to Recip.
1147 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1149 * Makefile.in (interp.o): Depends on sim-main.h
1151 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1153 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1154 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1155 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1156 STATE, DSSTATE): Define
1157 (GPR, FGRIDX, ..): Define.
1159 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1160 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1161 (GPR, FGRIDX, ...): Delete macros.
1163 * interp.c: Update names to match defines from sim-main.h
1165 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1167 * interp.c (sim_monitor): Add SD argument.
1168 (sim_warning): Delete. Replace calls with calls to
1170 (sim_error): Delete. Replace calls with sim_io_error.
1171 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1172 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1173 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1175 (mips_size): Rename from sim_size. Add SD argument.
1177 * interp.c (simulator): Delete global variable.
1178 (callback): Delete global variable.
1179 (mips_option_handler, sim_open, sim_write, sim_read,
1180 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1181 sim_size,sim_monitor): Use sim_io_* not callback->*.
1182 (sim_open): ZALLOC simulator struct.
1183 (PROFILE): Do not define.
1185 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1187 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1188 support.h with corresponding code.
1190 * sim-main.h (word64, uword64), support.h: Move definition to
1192 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1195 * Makefile.in: Update dependencies
1196 * interp.c: Do not include.
1198 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1200 * interp.c (address_translation, load_memory, store_memory,
1201 cache_op): Rename to from AddressTranslation et.al., make global,
1204 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1207 * interp.c (SignalException): Rename to signal_exception, make
1210 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1212 * sim-main.h (SignalException, SignalExceptionInterrupt,
1213 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1214 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1215 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1218 * interp.c, support.h: Use.
1220 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1222 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1223 to value_fpr / store_fpr. Add SD argument.
1224 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1225 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1227 * sim-main.h (ValueFPR, StoreFPR): Define.
1229 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1231 * interp.c (sim_engine_run): Check consistency between configure
1232 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1235 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1236 (mips_fpu): Configure WITH_FLOATING_POINT.
1237 (mips_endian): Configure WITH_TARGET_ENDIAN.
1238 * configure: Update.
1240 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1242 * configure: Regenerated to track ../common/aclocal.m4 changes.
1244 start-sanitize-r5900
1245 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1247 * interp.c (MAX_REG): Allow up-to 128 registers.
1248 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1249 (REGISTER_SA): Ditto.
1250 (sim_open): Initialize register_widths for r5900 specific
1252 (sim_fetch_register, sim_store_register): Check for request of
1253 r5900 specific SA register. Check for request for hi 64 bits of
1254 r5900 specific registers.
1257 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1259 * configure: Regenerated.
1261 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1263 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1265 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1267 * gencode.c (print_igen_insn_models): Assume certain architectures
1268 include all mips* instructions.
1269 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1272 * Makefile.in (tmp.igen): Add target. Generate igen input from
1275 * gencode.c (FEATURE_IGEN): Define.
1276 (main): Add --igen option. Generate output in igen format.
1277 (process_instructions): Format output according to igen option.
1278 (print_igen_insn_format): New function.
1279 (print_igen_insn_models): New function.
1280 (process_instructions): Only issue warnings and ignore
1281 instructions when no FEATURE_IGEN.
1283 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1285 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1288 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1290 * configure: Regenerated to track ../common/aclocal.m4 changes.
1292 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1294 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1295 SIM_RESERVED_BITS): Delete, moved to common.
1296 (SIM_EXTRA_CFLAGS): Update.
1298 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1300 * configure.in: Configure non-strict memory alignment.
1301 * configure: Regenerated to track ../common/aclocal.m4 changes.
1303 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1305 * configure: Regenerated to track ../common/aclocal.m4 changes.
1307 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1309 * gencode.c (SDBBP,DERET): Added (3900) insns.
1310 (RFE): Turn on for 3900.
1311 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1312 (dsstate): Made global.
1313 (SUBTARGET_R3900): Added.
1314 (CANCELDELAYSLOT): New.
1315 (SignalException): Ignore SystemCall rather than ignore and
1316 terminate. Add DebugBreakPoint handling.
1317 (decode_coproc): New insns RFE, DERET; and new registers Debug
1318 and DEPC protected by SUBTARGET_R3900.
1319 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1321 * Makefile.in,configure.in: Add mips subtarget option.
1322 * configure: Update.
1324 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1326 * gencode.c: Add r3900 (tx39).
1329 * gencode.c: Fix some configuration problems by improving
1330 the relationship between tx19 and tx39.
1333 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1335 * gencode.c (build_instruction): Don't need to subtract 4 for
1338 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1340 * interp.c: Correct some HASFPU problems.
1342 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1344 * configure: Regenerated to track ../common/aclocal.m4 changes.
1346 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1348 * interp.c (mips_options): Fix samples option short form, should
1351 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1353 * interp.c (sim_info): Enable info code. Was just returning.
1355 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1357 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1360 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1362 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1364 (build_instruction): Ditto for LL.
1367 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1369 * mips/configure.in, mips/gencode: Add tx19/r1900.
1372 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1374 * configure: Regenerated to track ../common/aclocal.m4 changes.
1376 start-sanitize-r5900
1377 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1379 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1380 for overflow due to ABS of MININT, set result to MAXINT.
1381 (build_instruction): For "psrlvw", signextend bit 31.
1384 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1386 * configure: Regenerated to track ../common/aclocal.m4 changes.
1389 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1391 * interp.c (sim_open): Add call to sim_analyze_program, update
1394 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1396 * interp.c (sim_kill): Delete.
1397 (sim_create_inferior): Add ABFD argument. Set PC from same.
1398 (sim_load): Move code initializing trap handlers from here.
1399 (sim_open): To here.
1400 (sim_load): Delete, use sim-hload.c.
1402 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1404 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1406 * configure: Regenerated to track ../common/aclocal.m4 changes.
1409 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1411 * interp.c (sim_open): Add ABFD argument.
1412 (sim_load): Move call to sim_config from here.
1413 (sim_open): To here. Check return status.
1415 start-sanitize-r5900
1416 * gencode.c (build_instruction): Do not define x8000000000000000,
1417 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1420 start-sanitize-r5900
1421 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1423 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1424 "pdivuw" check for overflow due to signed divide by -1.
1427 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1429 * gencode.c (build_instruction): Two arg MADD should
1430 not assign result to $0.
1432 start-sanitize-r5900
1433 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1435 * gencode.c (build_instruction): For "ppac5" use unsigned
1436 arrithmetic so that the sign bit doesn't smear when right shifted.
1437 (build_instruction): For "pdiv" perform sign extension when
1438 storing results in HI and LO.
1439 (build_instructions): For "pdiv" and "pdivbw" check for
1441 (build_instruction): For "pmfhl.slw" update hi part of dest
1442 register as well as low part.
1443 (build_instruction): For "pmfhl" portably handle long long values.
1444 (build_instruction): For "pmfhl.sh" correctly negative values.
1445 Store half words 2 and three in the correct place.
1446 (build_instruction): For "psllvw", sign extend value after shift.
1449 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1451 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1452 * sim/mips/configure.in: Regenerate.
1454 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1456 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1457 signed8, unsigned8 et.al. types.
1459 start-sanitize-r5900
1460 * gencode.c (build_instruction): For PMULTU* do not sign extend
1461 registers. Make generated code easier to debug.
1464 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1465 hosts when selecting subreg.
1467 start-sanitize-r5900
1468 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1470 * gencode.c (type_for_data_len): For 32bit operations concerned
1471 with overflow, perform op using 64bits.
1472 (build_instruction): For PADD, always compute operation using type
1473 returned by type_for_data_len.
1474 (build_instruction): For PSUBU, when overflow, saturate to zero as
1478 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1480 start-sanitize-r5900
1481 * gencode.c (build_instruction): Handle "pext5" according to
1482 version 1.95 of the r5900 ISA.
1484 * gencode.c (build_instruction): Handle "ppac5" according to
1485 version 1.95 of the r5900 ISA.
1488 * interp.c (sim_engine_run): Reset the ZERO register to zero
1489 regardless of FEATURE_WARN_ZERO.
1490 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1492 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1494 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1495 (SignalException): For BreakPoints ignore any mode bits and just
1497 (SignalException): Always set the CAUSE register.
1499 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1501 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1502 exception has been taken.
1504 * interp.c: Implement the ERET and mt/f sr instructions.
1506 start-sanitize-r5900
1507 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1509 * gencode.c (build_instruction): For paddu, extract unsigned
1512 * gencode.c (build_instruction): Saturate padds instead of padd
1516 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1518 * interp.c (SignalException): Don't bother restarting an
1521 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1523 * interp.c (SignalException): Really take an interrupt.
1524 (interrupt_event): Only deliver interrupts when enabled.
1526 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1528 * interp.c (sim_info): Only print info when verbose.
1529 (sim_info) Use sim_io_printf for output.
1531 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1533 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1536 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1538 * interp.c (sim_do_command): Check for common commands if a
1539 simulator specific command fails.
1541 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1543 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1544 and simBE when DEBUG is defined.
1546 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1548 * interp.c (interrupt_event): New function. Pass exception event
1549 onto exception handler.
1551 * configure.in: Check for stdlib.h.
1552 * configure: Regenerate.
1554 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1555 variable declaration.
1556 (build_instruction): Initialize memval1.
1557 (build_instruction): Add UNUSED attribute to byte, bigend,
1559 (build_operands): Ditto.
1561 * interp.c: Fix GCC warnings.
1562 (sim_get_quit_code): Delete.
1564 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1565 * Makefile.in: Ditto.
1566 * configure: Re-generate.
1568 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1570 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1572 * interp.c (mips_option_handler): New function parse argumes using
1574 (myname): Replace with STATE_MY_NAME.
1575 (sim_open): Delete check for host endianness - performed by
1577 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1578 (sim_open): Move much of the initialization from here.
1579 (sim_load): To here. After the image has been loaded and
1581 (sim_open): Move ColdReset from here.
1582 (sim_create_inferior): To here.
1583 (sim_open): Make FP check less dependant on host endianness.
1585 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1587 * interp.c (sim_set_callbacks): Delete.
1589 * interp.c (membank, membank_base, membank_size): Replace with
1590 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1591 (sim_open): Remove call to callback->init. gdb/run do this.
1595 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1597 * interp.c (big_endian_p): Delete, replaced by
1598 current_target_byte_order.
1600 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1602 * interp.c (host_read_long, host_read_word, host_swap_word,
1603 host_swap_long): Delete. Using common sim-endian.
1604 (sim_fetch_register, sim_store_register): Use H2T.
1605 (pipeline_ticks): Delete. Handled by sim-events.
1607 (sim_engine_run): Update.
1609 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1611 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1613 (SignalException): To here. Signal using sim_engine_halt.
1614 (sim_stop_reason): Delete, moved to common.
1616 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1618 * interp.c (sim_open): Add callback argument.
1619 (sim_set_callbacks): Delete SIM_DESC argument.
1622 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1624 * Makefile.in (SIM_OBJS): Add common modules.
1626 * interp.c (sim_set_callbacks): Also set SD callback.
1627 (set_endianness, xfer_*, swap_*): Delete.
1628 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1629 Change to functions using sim-endian macros.
1630 (control_c, sim_stop): Delete, use common version.
1631 (simulate): Convert into.
1632 (sim_engine_run): This function.
1633 (sim_resume): Delete.
1635 * interp.c (simulation): New variable - the simulator object.
1636 (sim_kind): Delete global - merged into simulation.
1637 (sim_load): Cleanup. Move PC assignment from here.
1638 (sim_create_inferior): To here.
1640 * sim-main.h: New file.
1641 * interp.c (sim-main.h): Include.
1643 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1645 * configure: Regenerated to track ../common/aclocal.m4 changes.
1647 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1649 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1651 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1653 * gencode.c (build_instruction): DIV instructions: check
1654 for division by zero and integer overflow before using
1655 host's division operation.
1657 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1659 * Makefile.in (SIM_OBJS): Add sim-load.o.
1660 * interp.c: #include bfd.h.
1661 (target_byte_order): Delete.
1662 (sim_kind, myname, big_endian_p): New static locals.
1663 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1664 after argument parsing. Recognize -E arg, set endianness accordingly.
1665 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1666 load file into simulator. Set PC from bfd.
1667 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1668 (set_endianness): Use big_endian_p instead of target_byte_order.
1670 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1672 * interp.c (sim_size): Delete prototype - conflicts with
1673 definition in remote-sim.h. Correct definition.
1675 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1677 * configure: Regenerated to track ../common/aclocal.m4 changes.
1680 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1682 * interp.c (sim_open): New arg `kind'.
1684 * configure: Regenerated to track ../common/aclocal.m4 changes.
1686 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1688 * configure: Regenerated to track ../common/aclocal.m4 changes.
1690 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1692 * interp.c (sim_open): Set optind to 0 before calling getopt.
1694 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1696 * configure: Regenerated to track ../common/aclocal.m4 changes.
1698 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1700 * interp.c : Replace uses of pr_addr with pr_uword64
1701 where the bit length is always 64 independent of SIM_ADDR.
1702 (pr_uword64) : added.
1704 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1706 * configure: Re-generate.
1708 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1710 * configure: Regenerate to track ../common/aclocal.m4 changes.
1712 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1714 * interp.c (sim_open): New SIM_DESC result. Argument is now
1716 (other sim_*): New SIM_DESC argument.
1718 start-sanitize-r5900
1719 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1721 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1722 Change values to avoid overloading DOUBLEWORD which is tested
1724 * gencode.c: reinstate "offending code".
1727 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1729 * interp.c: Fix printing of addresses for non-64-bit targets.
1730 (pr_addr): Add function to print address based on size.
1731 start-sanitize-r5900
1732 * gencode.c: #ifdef out offending code until a permanent fix
1733 can be added. Code is causing build errors for non-5900 mips targets.
1736 start-sanitize-r5900
1737 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1739 * gencode.c (process_instructions): Correct test for ISA dependent
1740 architecture bits in isa field of MIPS_DECODE.
1743 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1745 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1747 start-sanitize-r5900
1748 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
1750 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1754 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1756 * gencode.c (build_mips16_operands): Correct computation of base
1757 address for extended PC relative instruction.
1759 start-sanitize-r5900
1760 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
1762 * Makefile.in, configure, configure.in, gencode.c,
1763 interp.c, support.h: add r5900.
1766 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1768 * interp.c (mips16_entry): Add support for floating point cases.
1769 (SignalException): Pass floating point cases to mips16_entry.
1770 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1772 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1774 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1775 and then set the state to fmt_uninterpreted.
1776 (COP_SW): Temporarily set the state to fmt_word while calling
1779 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1781 * gencode.c (build_instruction): The high order may be set in the
1782 comparison flags at any ISA level, not just ISA 4.
1784 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1786 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1787 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1788 * configure.in: sinclude ../common/aclocal.m4.
1789 * configure: Regenerated.
1791 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1793 * configure: Rebuild after change to aclocal.m4.
1795 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1797 * configure configure.in Makefile.in: Update to new configure
1798 scheme which is more compatible with WinGDB builds.
1799 * configure.in: Improve comment on how to run autoconf.
1800 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1801 * Makefile.in: Use autoconf substitution to install common
1804 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1806 * gencode.c (build_instruction): Use BigEndianCPU instead of
1809 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1811 * interp.c (sim_monitor): Make output to stdout visible in
1812 wingdb's I/O log window.
1814 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1816 * support.h: Undo previous change to SIGTRAP
1819 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1821 * interp.c (store_word, load_word): New static functions.
1822 (mips16_entry): New static function.
1823 (SignalException): Look for mips16 entry and exit instructions.
1824 (simulate): Use the correct index when setting fpr_state after
1825 doing a pending move.
1827 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1829 * interp.c: Fix byte-swapping code throughout to work on
1830 both little- and big-endian hosts.
1832 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1834 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1835 with gdb/config/i386/xm-windows.h.
1837 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1839 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1840 that messes up arithmetic shifts.
1842 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1844 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1845 SIGTRAP and SIGQUIT for _WIN32.
1847 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1849 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1850 force a 64 bit multiplication.
1851 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1852 destination register is 0, since that is the default mips16 nop
1855 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1857 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1858 (build_endian_shift): Don't check proc64.
1859 (build_instruction): Always set memval to uword64. Cast op2 to
1860 uword64 when shifting it left in memory instructions. Always use
1861 the same code for stores--don't special case proc64.
1863 * gencode.c (build_mips16_operands): Fix base PC value for PC
1865 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1867 * interp.c (simJALDELAYSLOT): Define.
1868 (JALDELAYSLOT): Define.
1869 (INDELAYSLOT, INJALDELAYSLOT): Define.
1870 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1872 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1874 * interp.c (sim_open): add flush_cache as a PMON routine
1875 (sim_monitor): handle flush_cache by ignoring it
1877 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1879 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1881 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1882 (BigEndianMem): Rename to ByteSwapMem and change sense.
1883 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1884 BigEndianMem references to !ByteSwapMem.
1885 (set_endianness): New function, with prototype.
1886 (sim_open): Call set_endianness.
1887 (sim_info): Use simBE instead of BigEndianMem.
1888 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1889 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1890 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1891 ifdefs, keeping the prototype declaration.
1892 (swap_word): Rewrite correctly.
1893 (ColdReset): Delete references to CONFIG. Delete endianness related
1894 code; moved to set_endianness.
1896 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1898 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1899 * interp.c (CHECKHILO): Define away.
1900 (simSIGINT): New macro.
1901 (membank_size): Increase from 1MB to 2MB.
1902 (control_c): New function.
1903 (sim_resume): Rename parameter signal to signal_number. Add local
1904 variable prev. Call signal before and after simulate.
1905 (sim_stop_reason): Add simSIGINT support.
1906 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1908 (sim_warning): Delete call to SignalException. Do call printf_filtered
1910 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1911 a call to sim_warning.
1913 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1915 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1916 16 bit instructions.
1918 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1920 Add support for mips16 (16 bit MIPS implementation):
1921 * gencode.c (inst_type): Add mips16 instruction encoding types.
1922 (GETDATASIZEINSN): Define.
1923 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1924 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1926 (MIPS16_DECODE): New table, for mips16 instructions.
1927 (bitmap_val): New static function.
1928 (struct mips16_op): Define.
1929 (mips16_op_table): New table, for mips16 operands.
1930 (build_mips16_operands): New static function.
1931 (process_instructions): If PC is odd, decode a mips16
1932 instruction. Break out instruction handling into new
1933 build_instruction function.
1934 (build_instruction): New static function, broken out of
1935 process_instructions. Check modifiers rather than flags for SHIFT
1936 bit count and m[ft]{hi,lo} direction.
1937 (usage): Pass program name to fprintf.
1938 (main): Remove unused variable this_option_optind. Change
1939 ``*loptarg++'' to ``loptarg++''.
1940 (my_strtoul): Parenthesize && within ||.
1941 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1942 (simulate): If PC is odd, fetch a 16 bit instruction, and
1943 increment PC by 2 rather than 4.
1944 * configure.in: Add case for mips16*-*-*.
1945 * configure: Rebuild.
1947 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1949 * interp.c: Allow -t to enable tracing in standalone simulator.
1950 Fix garbage output in trace file and error messages.
1952 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1954 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1955 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1956 * configure.in: Simplify using macros in ../common/aclocal.m4.
1957 * configure: Regenerated.
1958 * tconfig.in: New file.
1960 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1962 * interp.c: Fix bugs in 64-bit port.
1963 Use ansi function declarations for msvc compiler.
1964 Initialize and test file pointer in trace code.
1965 Prevent duplicate definition of LAST_EMED_REGNUM.
1967 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1969 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1971 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1973 * interp.c (SignalException): Check for explicit terminating
1975 * gencode.c: Pass instruction value through SignalException()
1976 calls for Trap, Breakpoint and Syscall.
1978 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1980 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1981 only used on those hosts that provide it.
1982 * configure.in: Add sqrt() to list of functions to be checked for.
1983 * config.in: Re-generated.
1984 * configure: Re-generated.
1986 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1988 * gencode.c (process_instructions): Call build_endian_shift when
1989 expanding STORE RIGHT, to fix swr.
1990 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1991 clear the high bits.
1992 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1993 Fix float to int conversions to produce signed values.
1995 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1997 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1998 (process_instructions): Correct handling of nor instruction.
1999 Correct shift count for 32 bit shift instructions. Correct sign
2000 extension for arithmetic shifts to not shift the number of bits in
2001 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2002 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2004 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2005 It's OK to have a mult follow a mult. What's not OK is to have a
2006 mult follow an mfhi.
2007 (Convert): Comment out incorrect rounding code.
2009 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2011 * interp.c (sim_monitor): Improved monitor printf
2012 simulation. Tidied up simulator warnings, and added "--log" option
2013 for directing warning message output.
2014 * gencode.c: Use sim_warning() rather than WARNING macro.
2016 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2018 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2019 getopt1.o, rather than on gencode.c. Link objects together.
2020 Don't link against -liberty.
2021 (gencode.o, getopt.o, getopt1.o): New targets.
2022 * gencode.c: Include <ctype.h> and "ansidecl.h".
2023 (AND): Undefine after including "ansidecl.h".
2024 (ULONG_MAX): Define if not defined.
2025 (OP_*): Don't define macros; now defined in opcode/mips.h.
2026 (main): Call my_strtoul rather than strtoul.
2027 (my_strtoul): New static function.
2029 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2031 * gencode.c (process_instructions): Generate word64 and uword64
2032 instead of `long long' and `unsigned long long' data types.
2033 * interp.c: #include sysdep.h to get signals, and define default
2035 * (Convert): Work around for Visual-C++ compiler bug with type
2037 * support.h: Make things compile under Visual-C++ by using
2038 __int64 instead of `long long'. Change many refs to long long
2039 into word64/uword64 typedefs.
2041 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2043 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2044 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2046 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2047 (AC_PROG_INSTALL): Added.
2048 (AC_PROG_CC): Moved to before configure.host call.
2049 * configure: Rebuilt.
2051 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2053 * configure.in: Define @SIMCONF@ depending on mips target.
2054 * configure: Rebuild.
2055 * Makefile.in (run): Add @SIMCONF@ to control simulator
2057 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2058 * interp.c: Remove some debugging, provide more detailed error
2059 messages, update memory accesses to use LOADDRMASK.
2061 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2063 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2064 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2066 * configure: Rebuild.
2067 * config.in: New file, generated by autoheader.
2068 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2069 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2070 HAVE_ANINT and HAVE_AINT, as appropriate.
2071 * Makefile.in (run): Use @LIBS@ rather than -lm.
2072 (interp.o): Depend upon config.h.
2073 (Makefile): Just rebuild Makefile.
2074 (clean): Remove stamp-h.
2075 (mostlyclean): Make the same as clean, not as distclean.
2076 (config.h, stamp-h): New targets.
2078 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2080 * interp.c (ColdReset): Fix boolean test. Make all simulator
2083 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2085 * interp.c (xfer_direct_word, xfer_direct_long,
2086 swap_direct_word, swap_direct_long, xfer_big_word,
2087 xfer_big_long, xfer_little_word, xfer_little_long,
2088 swap_word,swap_long): Added.
2089 * interp.c (ColdReset): Provide function indirection to
2090 host<->simulated_target transfer routines.
2091 * interp.c (sim_store_register, sim_fetch_register): Updated to
2092 make use of indirected transfer routines.
2094 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2096 * gencode.c (process_instructions): Ensure FP ABS instruction
2098 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2099 system call support.
2101 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2103 * interp.c (sim_do_command): Complain if callback structure not
2106 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2108 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2109 support for Sun hosts.
2110 * Makefile.in (gencode): Ensure the host compiler and libraries
2111 used for cross-hosted build.
2113 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2115 * interp.c, gencode.c: Some more (TODO) tidying.
2117 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2119 * gencode.c, interp.c: Replaced explicit long long references with
2120 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2121 * support.h (SET64LO, SET64HI): Macros added.
2123 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2125 * configure: Regenerate with autoconf 2.7.
2127 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2129 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2130 * support.h: Remove superfluous "1" from #if.
2131 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2133 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2135 * interp.c (StoreFPR): Control UndefinedResult() call on
2136 WARN_RESULT manifest.
2138 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2140 * gencode.c: Tidied instruction decoding, and added FP instruction
2143 * interp.c: Added dineroIII, and BSD profiling support. Also
2144 run-time FP handling.
2146 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2148 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2149 gencode.c, interp.c, support.h: created.